1// SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause 2/* 3 * Copyright (C) 2005-2014, 2018-2023 Intel Corporation 4 * Copyright (C) 2013-2015 Intel Mobile Communications GmbH 5 * Copyright (C) 2015-2017 Intel Deutschland GmbH 6 */ 7#include <linux/devcoredump.h> 8#if defined(__FreeBSD__) 9#include <linux/delay.h> 10#endif 11#include "iwl-drv.h" 12#include "runtime.h" 13#include "dbg.h" 14#include "debugfs.h" 15#include "iwl-io.h" 16#include "iwl-prph.h" 17#include "iwl-csr.h" 18#include "iwl-fh.h" 19/** 20 * struct iwl_fw_dump_ptrs - set of pointers needed for the fw-error-dump 21 * 22 * @fwrt_ptr: pointer to the buffer coming from fwrt 23 * @trans_ptr: pointer to struct %iwl_trans_dump_data which contains the 24 * transport's data. 25 * @trans_len: length of the valid data in trans_ptr 26 * @fwrt_len: length of the valid data in fwrt_ptr 27 */ 28struct iwl_fw_dump_ptrs { 29 struct iwl_trans_dump_data *trans_ptr; 30 void *fwrt_ptr; 31 u32 fwrt_len; 32}; 33 34#define RADIO_REG_MAX_READ 0x2ad 35static void iwl_read_radio_regs(struct iwl_fw_runtime *fwrt, 36 struct iwl_fw_error_dump_data **dump_data) 37{ 38 u8 *pos = (void *)(*dump_data)->data; 39 int i; 40 41 IWL_DEBUG_INFO(fwrt, "WRT radio registers dump\n"); 42 43 if (!iwl_trans_grab_nic_access(fwrt->trans)) 44 return; 45 46 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RADIO_REG); 47 (*dump_data)->len = cpu_to_le32(RADIO_REG_MAX_READ); 48 49 for (i = 0; i < RADIO_REG_MAX_READ; i++) { 50 u32 rd_cmd = RADIO_RSP_RD_CMD; 51 52 rd_cmd |= i << RADIO_RSP_ADDR_POS; 53 iwl_write_prph_no_grab(fwrt->trans, RSP_RADIO_CMD, rd_cmd); 54 *pos = (u8)iwl_read_prph_no_grab(fwrt->trans, RSP_RADIO_RDDAT); 55 56 pos++; 57 } 58 59 *dump_data = iwl_fw_error_next_data(*dump_data); 60 61 iwl_trans_release_nic_access(fwrt->trans); 62} 63 64static void iwl_fwrt_dump_rxf(struct iwl_fw_runtime *fwrt, 65 struct iwl_fw_error_dump_data **dump_data, 66 int size, u32 offset, int fifo_num) 67{ 68 struct iwl_fw_error_dump_fifo *fifo_hdr; 69 u32 *fifo_data; 70 u32 fifo_len; 71 int i; 72 73 fifo_hdr = (void *)(*dump_data)->data; 74 fifo_data = (void *)fifo_hdr->data; 75 fifo_len = size; 76 77 /* No need to try to read the data if the length is 0 */ 78 if (fifo_len == 0) 79 return; 80 81 /* Add a TLV for the RXF */ 82 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_RXF); 83 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 84 85 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 86 fifo_hdr->available_bytes = 87 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 88 RXF_RD_D_SPACE + offset)); 89 fifo_hdr->wr_ptr = 90 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 91 RXF_RD_WR_PTR + offset)); 92 fifo_hdr->rd_ptr = 93 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 94 RXF_RD_RD_PTR + offset)); 95 fifo_hdr->fence_ptr = 96 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 97 RXF_RD_FENCE_PTR + offset)); 98 fifo_hdr->fence_mode = 99 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 100 RXF_SET_FENCE_MODE + offset)); 101 102 /* Lock fence */ 103 iwl_trans_write_prph(fwrt->trans, RXF_SET_FENCE_MODE + offset, 0x1); 104 /* Set fence pointer to the same place like WR pointer */ 105 iwl_trans_write_prph(fwrt->trans, RXF_LD_WR2FENCE + offset, 0x1); 106 /* Set fence offset */ 107 iwl_trans_write_prph(fwrt->trans, 108 RXF_LD_FENCE_OFFSET_ADDR + offset, 0x0); 109 110 /* Read FIFO */ 111 fifo_len /= sizeof(u32); /* Size in DWORDS */ 112 for (i = 0; i < fifo_len; i++) 113 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 114 RXF_FIFO_RD_FENCE_INC + 115 offset); 116 *dump_data = iwl_fw_error_next_data(*dump_data); 117} 118 119static void iwl_fwrt_dump_txf(struct iwl_fw_runtime *fwrt, 120 struct iwl_fw_error_dump_data **dump_data, 121 int size, u32 offset, int fifo_num) 122{ 123 struct iwl_fw_error_dump_fifo *fifo_hdr; 124 u32 *fifo_data; 125 u32 fifo_len; 126 int i; 127 128 fifo_hdr = (void *)(*dump_data)->data; 129 fifo_data = (void *)fifo_hdr->data; 130 fifo_len = size; 131 132 /* No need to try to read the data if the length is 0 */ 133 if (fifo_len == 0) 134 return; 135 136 /* Add a TLV for the FIFO */ 137 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_TXF); 138 (*dump_data)->len = cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 139 140 fifo_hdr->fifo_num = cpu_to_le32(fifo_num); 141 fifo_hdr->available_bytes = 142 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 143 TXF_FIFO_ITEM_CNT + offset)); 144 fifo_hdr->wr_ptr = 145 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 146 TXF_WR_PTR + offset)); 147 fifo_hdr->rd_ptr = 148 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 149 TXF_RD_PTR + offset)); 150 fifo_hdr->fence_ptr = 151 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 152 TXF_FENCE_PTR + offset)); 153 fifo_hdr->fence_mode = 154 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 155 TXF_LOCK_FENCE + offset)); 156 157 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 158 iwl_trans_write_prph(fwrt->trans, TXF_READ_MODIFY_ADDR + offset, 159 TXF_WR_PTR + offset); 160 161 /* Dummy-read to advance the read pointer to the head */ 162 iwl_trans_read_prph(fwrt->trans, TXF_READ_MODIFY_DATA + offset); 163 164 /* Read FIFO */ 165 for (i = 0; i < fifo_len / sizeof(u32); i++) 166 fifo_data[i] = iwl_trans_read_prph(fwrt->trans, 167 TXF_READ_MODIFY_DATA + 168 offset); 169 170 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 171 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 172 fifo_data, fifo_len); 173 174 *dump_data = iwl_fw_error_next_data(*dump_data); 175} 176 177static void iwl_fw_dump_rxf(struct iwl_fw_runtime *fwrt, 178 struct iwl_fw_error_dump_data **dump_data) 179{ 180 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 181 182 IWL_DEBUG_INFO(fwrt, "WRT RX FIFO dump\n"); 183 184 if (!iwl_trans_grab_nic_access(fwrt->trans)) 185 return; 186 187 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) { 188 /* Pull RXF1 */ 189 iwl_fwrt_dump_rxf(fwrt, dump_data, 190 cfg->lmac[0].rxfifo1_size, 0, 0); 191 /* Pull RXF2 */ 192 iwl_fwrt_dump_rxf(fwrt, dump_data, cfg->rxfifo2_size, 193 RXF_DIFF_FROM_PREV + 194 fwrt->trans->trans_cfg->umac_prph_offset, 1); 195 /* Pull LMAC2 RXF1 */ 196 if (fwrt->smem_cfg.num_lmacs > 1) 197 iwl_fwrt_dump_rxf(fwrt, dump_data, 198 cfg->lmac[1].rxfifo1_size, 199 LMAC2_PRPH_OFFSET, 2); 200 } 201 202 iwl_trans_release_nic_access(fwrt->trans); 203} 204 205static void iwl_fw_dump_txf(struct iwl_fw_runtime *fwrt, 206 struct iwl_fw_error_dump_data **dump_data) 207{ 208 struct iwl_fw_error_dump_fifo *fifo_hdr; 209 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 210 u32 *fifo_data; 211 u32 fifo_len; 212 int i, j; 213 214 IWL_DEBUG_INFO(fwrt, "WRT TX FIFO dump\n"); 215 216 if (!iwl_trans_grab_nic_access(fwrt->trans)) 217 return; 218 219 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) { 220 /* Pull TXF data from LMAC1 */ 221 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; i++) { 222 /* Mark the number of TXF we're pulling now */ 223 iwl_trans_write_prph(fwrt->trans, TXF_LARC_NUM, i); 224 iwl_fwrt_dump_txf(fwrt, dump_data, 225 cfg->lmac[0].txfifo_size[i], 0, i); 226 } 227 228 /* Pull TXF data from LMAC2 */ 229 if (fwrt->smem_cfg.num_lmacs > 1) { 230 for (i = 0; i < fwrt->smem_cfg.num_txfifo_entries; 231 i++) { 232 /* Mark the number of TXF we're pulling now */ 233 iwl_trans_write_prph(fwrt->trans, 234 TXF_LARC_NUM + 235 LMAC2_PRPH_OFFSET, i); 236 iwl_fwrt_dump_txf(fwrt, dump_data, 237 cfg->lmac[1].txfifo_size[i], 238 LMAC2_PRPH_OFFSET, 239 i + cfg->num_txfifo_entries); 240 } 241 } 242 } 243 244 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 245 fw_has_capa(&fwrt->fw->ucode_capa, 246 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) { 247 /* Pull UMAC internal TXF data from all TXFs */ 248 for (i = 0; 249 i < ARRAY_SIZE(fwrt->smem_cfg.internal_txfifo_size); 250 i++) { 251 fifo_hdr = (void *)(*dump_data)->data; 252 fifo_data = (void *)fifo_hdr->data; 253 fifo_len = fwrt->smem_cfg.internal_txfifo_size[i]; 254 255 /* No need to try to read the data if the length is 0 */ 256 if (fifo_len == 0) 257 continue; 258 259 /* Add a TLV for the internal FIFOs */ 260 (*dump_data)->type = 261 cpu_to_le32(IWL_FW_ERROR_DUMP_INTERNAL_TXF); 262 (*dump_data)->len = 263 cpu_to_le32(fifo_len + sizeof(*fifo_hdr)); 264 265 fifo_hdr->fifo_num = cpu_to_le32(i); 266 267 /* Mark the number of TXF we're pulling now */ 268 iwl_trans_write_prph(fwrt->trans, TXF_CPU2_NUM, i + 269 fwrt->smem_cfg.num_txfifo_entries); 270 271 fifo_hdr->available_bytes = 272 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 273 TXF_CPU2_FIFO_ITEM_CNT)); 274 fifo_hdr->wr_ptr = 275 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 276 TXF_CPU2_WR_PTR)); 277 fifo_hdr->rd_ptr = 278 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 279 TXF_CPU2_RD_PTR)); 280 fifo_hdr->fence_ptr = 281 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 282 TXF_CPU2_FENCE_PTR)); 283 fifo_hdr->fence_mode = 284 cpu_to_le32(iwl_trans_read_prph(fwrt->trans, 285 TXF_CPU2_LOCK_FENCE)); 286 287 /* Set TXF_CPU2_READ_MODIFY_ADDR to TXF_CPU2_WR_PTR */ 288 iwl_trans_write_prph(fwrt->trans, 289 TXF_CPU2_READ_MODIFY_ADDR, 290 TXF_CPU2_WR_PTR); 291 292 /* Dummy-read to advance the read pointer to head */ 293 iwl_trans_read_prph(fwrt->trans, 294 TXF_CPU2_READ_MODIFY_DATA); 295 296 /* Read FIFO */ 297 fifo_len /= sizeof(u32); /* Size in DWORDS */ 298 for (j = 0; j < fifo_len; j++) 299 fifo_data[j] = 300 iwl_trans_read_prph(fwrt->trans, 301 TXF_CPU2_READ_MODIFY_DATA); 302 *dump_data = iwl_fw_error_next_data(*dump_data); 303 } 304 } 305 306 iwl_trans_release_nic_access(fwrt->trans); 307} 308 309struct iwl_prph_range { 310 u32 start, end; 311}; 312 313static const struct iwl_prph_range iwl_prph_dump_addr_comm[] = { 314 { .start = 0x00a00000, .end = 0x00a00000 }, 315 { .start = 0x00a0000c, .end = 0x00a00024 }, 316 { .start = 0x00a0002c, .end = 0x00a0003c }, 317 { .start = 0x00a00410, .end = 0x00a00418 }, 318 { .start = 0x00a00420, .end = 0x00a00420 }, 319 { .start = 0x00a00428, .end = 0x00a00428 }, 320 { .start = 0x00a00430, .end = 0x00a0043c }, 321 { .start = 0x00a00444, .end = 0x00a00444 }, 322 { .start = 0x00a004c0, .end = 0x00a004cc }, 323 { .start = 0x00a004d8, .end = 0x00a004d8 }, 324 { .start = 0x00a004e0, .end = 0x00a004f0 }, 325 { .start = 0x00a00840, .end = 0x00a00840 }, 326 { .start = 0x00a00850, .end = 0x00a00858 }, 327 { .start = 0x00a01004, .end = 0x00a01008 }, 328 { .start = 0x00a01010, .end = 0x00a01010 }, 329 { .start = 0x00a01018, .end = 0x00a01018 }, 330 { .start = 0x00a01024, .end = 0x00a01024 }, 331 { .start = 0x00a0102c, .end = 0x00a01034 }, 332 { .start = 0x00a0103c, .end = 0x00a01040 }, 333 { .start = 0x00a01048, .end = 0x00a01094 }, 334 { .start = 0x00a01c00, .end = 0x00a01c20 }, 335 { .start = 0x00a01c58, .end = 0x00a01c58 }, 336 { .start = 0x00a01c7c, .end = 0x00a01c7c }, 337 { .start = 0x00a01c28, .end = 0x00a01c54 }, 338 { .start = 0x00a01c5c, .end = 0x00a01c5c }, 339 { .start = 0x00a01c60, .end = 0x00a01cdc }, 340 { .start = 0x00a01ce0, .end = 0x00a01d0c }, 341 { .start = 0x00a01d18, .end = 0x00a01d20 }, 342 { .start = 0x00a01d2c, .end = 0x00a01d30 }, 343 { .start = 0x00a01d40, .end = 0x00a01d5c }, 344 { .start = 0x00a01d80, .end = 0x00a01d80 }, 345 { .start = 0x00a01d98, .end = 0x00a01d9c }, 346 { .start = 0x00a01da8, .end = 0x00a01da8 }, 347 { .start = 0x00a01db8, .end = 0x00a01df4 }, 348 { .start = 0x00a01dc0, .end = 0x00a01dfc }, 349 { .start = 0x00a01e00, .end = 0x00a01e2c }, 350 { .start = 0x00a01e40, .end = 0x00a01e60 }, 351 { .start = 0x00a01e68, .end = 0x00a01e6c }, 352 { .start = 0x00a01e74, .end = 0x00a01e74 }, 353 { .start = 0x00a01e84, .end = 0x00a01e90 }, 354 { .start = 0x00a01e9c, .end = 0x00a01ec4 }, 355 { .start = 0x00a01ed0, .end = 0x00a01ee0 }, 356 { .start = 0x00a01f00, .end = 0x00a01f1c }, 357 { .start = 0x00a01f44, .end = 0x00a01ffc }, 358 { .start = 0x00a02000, .end = 0x00a02048 }, 359 { .start = 0x00a02068, .end = 0x00a020f0 }, 360 { .start = 0x00a02100, .end = 0x00a02118 }, 361 { .start = 0x00a02140, .end = 0x00a0214c }, 362 { .start = 0x00a02168, .end = 0x00a0218c }, 363 { .start = 0x00a021c0, .end = 0x00a021c0 }, 364 { .start = 0x00a02400, .end = 0x00a02410 }, 365 { .start = 0x00a02418, .end = 0x00a02420 }, 366 { .start = 0x00a02428, .end = 0x00a0242c }, 367 { .start = 0x00a02434, .end = 0x00a02434 }, 368 { .start = 0x00a02440, .end = 0x00a02460 }, 369 { .start = 0x00a02468, .end = 0x00a024b0 }, 370 { .start = 0x00a024c8, .end = 0x00a024cc }, 371 { .start = 0x00a02500, .end = 0x00a02504 }, 372 { .start = 0x00a0250c, .end = 0x00a02510 }, 373 { .start = 0x00a02540, .end = 0x00a02554 }, 374 { .start = 0x00a02580, .end = 0x00a025f4 }, 375 { .start = 0x00a02600, .end = 0x00a0260c }, 376 { .start = 0x00a02648, .end = 0x00a02650 }, 377 { .start = 0x00a02680, .end = 0x00a02680 }, 378 { .start = 0x00a026c0, .end = 0x00a026d0 }, 379 { .start = 0x00a02700, .end = 0x00a0270c }, 380 { .start = 0x00a02804, .end = 0x00a02804 }, 381 { .start = 0x00a02818, .end = 0x00a0281c }, 382 { .start = 0x00a02c00, .end = 0x00a02db4 }, 383 { .start = 0x00a02df4, .end = 0x00a02fb0 }, 384 { .start = 0x00a03000, .end = 0x00a03014 }, 385 { .start = 0x00a0301c, .end = 0x00a0302c }, 386 { .start = 0x00a03034, .end = 0x00a03038 }, 387 { .start = 0x00a03040, .end = 0x00a03048 }, 388 { .start = 0x00a03060, .end = 0x00a03068 }, 389 { .start = 0x00a03070, .end = 0x00a03074 }, 390 { .start = 0x00a0307c, .end = 0x00a0307c }, 391 { .start = 0x00a03080, .end = 0x00a03084 }, 392 { .start = 0x00a0308c, .end = 0x00a03090 }, 393 { .start = 0x00a03098, .end = 0x00a03098 }, 394 { .start = 0x00a030a0, .end = 0x00a030a0 }, 395 { .start = 0x00a030a8, .end = 0x00a030b4 }, 396 { .start = 0x00a030bc, .end = 0x00a030bc }, 397 { .start = 0x00a030c0, .end = 0x00a0312c }, 398 { .start = 0x00a03c00, .end = 0x00a03c5c }, 399 { .start = 0x00a04400, .end = 0x00a04454 }, 400 { .start = 0x00a04460, .end = 0x00a04474 }, 401 { .start = 0x00a044c0, .end = 0x00a044ec }, 402 { .start = 0x00a04500, .end = 0x00a04504 }, 403 { .start = 0x00a04510, .end = 0x00a04538 }, 404 { .start = 0x00a04540, .end = 0x00a04548 }, 405 { .start = 0x00a04560, .end = 0x00a0457c }, 406 { .start = 0x00a04590, .end = 0x00a04598 }, 407 { .start = 0x00a045c0, .end = 0x00a045f4 }, 408}; 409 410static const struct iwl_prph_range iwl_prph_dump_addr_9000[] = { 411 { .start = 0x00a05c00, .end = 0x00a05c18 }, 412 { .start = 0x00a05400, .end = 0x00a056e8 }, 413 { .start = 0x00a08000, .end = 0x00a098bc }, 414 { .start = 0x00a02400, .end = 0x00a02758 }, 415 { .start = 0x00a04764, .end = 0x00a0476c }, 416 { .start = 0x00a04770, .end = 0x00a04774 }, 417 { .start = 0x00a04620, .end = 0x00a04624 }, 418}; 419 420static const struct iwl_prph_range iwl_prph_dump_addr_22000[] = { 421 { .start = 0x00a00000, .end = 0x00a00000 }, 422 { .start = 0x00a0000c, .end = 0x00a00024 }, 423 { .start = 0x00a0002c, .end = 0x00a00034 }, 424 { .start = 0x00a0003c, .end = 0x00a0003c }, 425 { .start = 0x00a00410, .end = 0x00a00418 }, 426 { .start = 0x00a00420, .end = 0x00a00420 }, 427 { .start = 0x00a00428, .end = 0x00a00428 }, 428 { .start = 0x00a00430, .end = 0x00a0043c }, 429 { .start = 0x00a00444, .end = 0x00a00444 }, 430 { .start = 0x00a00840, .end = 0x00a00840 }, 431 { .start = 0x00a00850, .end = 0x00a00858 }, 432 { .start = 0x00a01004, .end = 0x00a01008 }, 433 { .start = 0x00a01010, .end = 0x00a01010 }, 434 { .start = 0x00a01018, .end = 0x00a01018 }, 435 { .start = 0x00a01024, .end = 0x00a01024 }, 436 { .start = 0x00a0102c, .end = 0x00a01034 }, 437 { .start = 0x00a0103c, .end = 0x00a01040 }, 438 { .start = 0x00a01048, .end = 0x00a01050 }, 439 { .start = 0x00a01058, .end = 0x00a01058 }, 440 { .start = 0x00a01060, .end = 0x00a01070 }, 441 { .start = 0x00a0108c, .end = 0x00a0108c }, 442 { .start = 0x00a01c20, .end = 0x00a01c28 }, 443 { .start = 0x00a01d10, .end = 0x00a01d10 }, 444 { .start = 0x00a01e28, .end = 0x00a01e2c }, 445 { .start = 0x00a01e60, .end = 0x00a01e60 }, 446 { .start = 0x00a01e80, .end = 0x00a01e80 }, 447 { .start = 0x00a01ea0, .end = 0x00a01ea0 }, 448 { .start = 0x00a02000, .end = 0x00a0201c }, 449 { .start = 0x00a02024, .end = 0x00a02024 }, 450 { .start = 0x00a02040, .end = 0x00a02048 }, 451 { .start = 0x00a020c0, .end = 0x00a020e0 }, 452 { .start = 0x00a02400, .end = 0x00a02404 }, 453 { .start = 0x00a0240c, .end = 0x00a02414 }, 454 { .start = 0x00a0241c, .end = 0x00a0243c }, 455 { .start = 0x00a02448, .end = 0x00a024bc }, 456 { .start = 0x00a024c4, .end = 0x00a024cc }, 457 { .start = 0x00a02508, .end = 0x00a02508 }, 458 { .start = 0x00a02510, .end = 0x00a02514 }, 459 { .start = 0x00a0251c, .end = 0x00a0251c }, 460 { .start = 0x00a0252c, .end = 0x00a0255c }, 461 { .start = 0x00a02564, .end = 0x00a025a0 }, 462 { .start = 0x00a025a8, .end = 0x00a025b4 }, 463 { .start = 0x00a025c0, .end = 0x00a025c0 }, 464 { .start = 0x00a025e8, .end = 0x00a025f4 }, 465 { .start = 0x00a02c08, .end = 0x00a02c18 }, 466 { .start = 0x00a02c2c, .end = 0x00a02c38 }, 467 { .start = 0x00a02c68, .end = 0x00a02c78 }, 468 { .start = 0x00a03000, .end = 0x00a03000 }, 469 { .start = 0x00a03010, .end = 0x00a03014 }, 470 { .start = 0x00a0301c, .end = 0x00a0302c }, 471 { .start = 0x00a03034, .end = 0x00a03038 }, 472 { .start = 0x00a03040, .end = 0x00a03044 }, 473 { .start = 0x00a03060, .end = 0x00a03068 }, 474 { .start = 0x00a03070, .end = 0x00a03070 }, 475 { .start = 0x00a0307c, .end = 0x00a03084 }, 476 { .start = 0x00a0308c, .end = 0x00a03090 }, 477 { .start = 0x00a03098, .end = 0x00a03098 }, 478 { .start = 0x00a030a0, .end = 0x00a030a0 }, 479 { .start = 0x00a030a8, .end = 0x00a030b4 }, 480 { .start = 0x00a030bc, .end = 0x00a030c0 }, 481 { .start = 0x00a030c8, .end = 0x00a030f4 }, 482 { .start = 0x00a03100, .end = 0x00a0312c }, 483 { .start = 0x00a03c00, .end = 0x00a03c5c }, 484 { .start = 0x00a04400, .end = 0x00a04454 }, 485 { .start = 0x00a04460, .end = 0x00a04474 }, 486 { .start = 0x00a044c0, .end = 0x00a044ec }, 487 { .start = 0x00a04500, .end = 0x00a04504 }, 488 { .start = 0x00a04510, .end = 0x00a04538 }, 489 { .start = 0x00a04540, .end = 0x00a04548 }, 490 { .start = 0x00a04560, .end = 0x00a04560 }, 491 { .start = 0x00a04570, .end = 0x00a0457c }, 492 { .start = 0x00a04590, .end = 0x00a04590 }, 493 { .start = 0x00a04598, .end = 0x00a04598 }, 494 { .start = 0x00a045c0, .end = 0x00a045f4 }, 495 { .start = 0x00a05c18, .end = 0x00a05c1c }, 496 { .start = 0x00a0c000, .end = 0x00a0c018 }, 497 { .start = 0x00a0c020, .end = 0x00a0c028 }, 498 { .start = 0x00a0c038, .end = 0x00a0c094 }, 499 { .start = 0x00a0c0c0, .end = 0x00a0c104 }, 500 { .start = 0x00a0c10c, .end = 0x00a0c118 }, 501 { .start = 0x00a0c150, .end = 0x00a0c174 }, 502 { .start = 0x00a0c17c, .end = 0x00a0c188 }, 503 { .start = 0x00a0c190, .end = 0x00a0c198 }, 504 { .start = 0x00a0c1a0, .end = 0x00a0c1a8 }, 505 { .start = 0x00a0c1b0, .end = 0x00a0c1b8 }, 506}; 507 508static const struct iwl_prph_range iwl_prph_dump_addr_ax210[] = { 509 { .start = 0x00d03c00, .end = 0x00d03c64 }, 510 { .start = 0x00d05c18, .end = 0x00d05c1c }, 511 { .start = 0x00d0c000, .end = 0x00d0c174 }, 512}; 513 514static void iwl_read_prph_block(struct iwl_trans *trans, u32 start, 515 u32 len_bytes, __le32 *data) 516{ 517 u32 i; 518 519 for (i = 0; i < len_bytes; i += 4) 520 *data++ = cpu_to_le32(iwl_read_prph_no_grab(trans, start + i)); 521} 522 523static void iwl_dump_prph(struct iwl_fw_runtime *fwrt, 524 const struct iwl_prph_range *iwl_prph_dump_addr, 525 u32 range_len, void *ptr) 526{ 527 struct iwl_fw_error_dump_prph *prph; 528 struct iwl_trans *trans = fwrt->trans; 529 struct iwl_fw_error_dump_data **data = 530 (struct iwl_fw_error_dump_data **)ptr; 531 u32 i; 532 533 if (!data) 534 return; 535 536 IWL_DEBUG_INFO(trans, "WRT PRPH dump\n"); 537 538 if (!iwl_trans_grab_nic_access(trans)) 539 return; 540 541 for (i = 0; i < range_len; i++) { 542 /* The range includes both boundaries */ 543 int num_bytes_in_chunk = iwl_prph_dump_addr[i].end - 544 iwl_prph_dump_addr[i].start + 4; 545 546 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PRPH); 547 (*data)->len = cpu_to_le32(sizeof(*prph) + 548 num_bytes_in_chunk); 549 prph = (void *)(*data)->data; 550 prph->prph_start = cpu_to_le32(iwl_prph_dump_addr[i].start); 551 552 iwl_read_prph_block(trans, iwl_prph_dump_addr[i].start, 553 /* our range is inclusive, hence + 4 */ 554 iwl_prph_dump_addr[i].end - 555 iwl_prph_dump_addr[i].start + 4, 556 (void *)prph->data); 557 558 *data = iwl_fw_error_next_data(*data); 559 } 560 561 iwl_trans_release_nic_access(trans); 562} 563 564/* 565 * alloc_sgtable - allocates scallerlist table in the given size, 566 * fills it with pages and returns it 567 * @size: the size (in bytes) of the table 568*/ 569static struct scatterlist *alloc_sgtable(int size) 570{ 571 int alloc_size, nents, i; 572 struct page *new_page; 573 struct scatterlist *iter; 574 struct scatterlist *table; 575 576 nents = DIV_ROUND_UP(size, PAGE_SIZE); 577 table = kcalloc(nents, sizeof(*table), GFP_KERNEL); 578 if (!table) 579 return NULL; 580 sg_init_table(table, nents); 581 iter = table; 582 for_each_sg(table, iter, sg_nents(table), i) { 583 new_page = alloc_page(GFP_KERNEL); 584 if (!new_page) { 585 /* release all previous allocated pages in the table */ 586 iter = table; 587 for_each_sg(table, iter, sg_nents(table), i) { 588 new_page = sg_page(iter); 589 if (new_page) 590 __free_page(new_page); 591 } 592 kfree(table); 593 return NULL; 594 } 595 alloc_size = min_t(int, size, PAGE_SIZE); 596 size -= PAGE_SIZE; 597 sg_set_page(iter, new_page, alloc_size, 0); 598 } 599 return table; 600} 601 602static void iwl_fw_get_prph_len(struct iwl_fw_runtime *fwrt, 603 const struct iwl_prph_range *iwl_prph_dump_addr, 604 u32 range_len, void *ptr) 605{ 606 u32 *prph_len = (u32 *)ptr; 607 int i, num_bytes_in_chunk; 608 609 if (!prph_len) 610 return; 611 612 for (i = 0; i < range_len; i++) { 613 /* The range includes both boundaries */ 614 num_bytes_in_chunk = 615 iwl_prph_dump_addr[i].end - 616 iwl_prph_dump_addr[i].start + 4; 617 618 *prph_len += sizeof(struct iwl_fw_error_dump_data) + 619 sizeof(struct iwl_fw_error_dump_prph) + 620 num_bytes_in_chunk; 621 } 622} 623 624static void iwl_fw_prph_handler(struct iwl_fw_runtime *fwrt, void *ptr, 625 void (*handler)(struct iwl_fw_runtime *, 626 const struct iwl_prph_range *, 627 u32, void *)) 628{ 629 u32 range_len; 630 631 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 632 range_len = ARRAY_SIZE(iwl_prph_dump_addr_ax210); 633 handler(fwrt, iwl_prph_dump_addr_ax210, range_len, ptr); 634 } else if (fwrt->trans->trans_cfg->device_family >= 635 IWL_DEVICE_FAMILY_22000) { 636 range_len = ARRAY_SIZE(iwl_prph_dump_addr_22000); 637 handler(fwrt, iwl_prph_dump_addr_22000, range_len, ptr); 638 } else { 639 range_len = ARRAY_SIZE(iwl_prph_dump_addr_comm); 640 handler(fwrt, iwl_prph_dump_addr_comm, range_len, ptr); 641 642 if (fwrt->trans->trans_cfg->mq_rx_supported) { 643 range_len = ARRAY_SIZE(iwl_prph_dump_addr_9000); 644 handler(fwrt, iwl_prph_dump_addr_9000, range_len, ptr); 645 } 646 } 647} 648 649static void iwl_fw_dump_mem(struct iwl_fw_runtime *fwrt, 650 struct iwl_fw_error_dump_data **dump_data, 651 u32 len, u32 ofs, u32 type) 652{ 653 struct iwl_fw_error_dump_mem *dump_mem; 654 655 if (!len) 656 return; 657 658 (*dump_data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM); 659 (*dump_data)->len = cpu_to_le32(len + sizeof(*dump_mem)); 660 dump_mem = (void *)(*dump_data)->data; 661 dump_mem->type = cpu_to_le32(type); 662 dump_mem->offset = cpu_to_le32(ofs); 663 iwl_trans_read_mem_bytes(fwrt->trans, ofs, dump_mem->data, len); 664 *dump_data = iwl_fw_error_next_data(*dump_data); 665 666 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 667 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, ofs, 668 dump_mem->data, len); 669 670 IWL_DEBUG_INFO(fwrt, "WRT memory dump. Type=%u\n", dump_mem->type); 671} 672 673#define ADD_LEN(len, item_len, const_len) \ 674 do {size_t item = item_len; len += (!!item) * const_len + item; } \ 675 while (0) 676 677static int iwl_fw_rxf_len(struct iwl_fw_runtime *fwrt, 678 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 679{ 680 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 681 sizeof(struct iwl_fw_error_dump_fifo); 682 u32 fifo_len = 0; 683 int i; 684 685 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RXF)) 686 return 0; 687 688 /* Count RXF2 size */ 689 ADD_LEN(fifo_len, mem_cfg->rxfifo2_size, hdr_len); 690 691 /* Count RXF1 sizes */ 692 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 693 mem_cfg->num_lmacs = MAX_NUM_LMAC; 694 695 for (i = 0; i < mem_cfg->num_lmacs; i++) 696 ADD_LEN(fifo_len, mem_cfg->lmac[i].rxfifo1_size, hdr_len); 697 698 return fifo_len; 699} 700 701static int iwl_fw_txf_len(struct iwl_fw_runtime *fwrt, 702 struct iwl_fwrt_shared_mem_cfg *mem_cfg) 703{ 704 size_t hdr_len = sizeof(struct iwl_fw_error_dump_data) + 705 sizeof(struct iwl_fw_error_dump_fifo); 706 u32 fifo_len = 0; 707 int i; 708 709 if (!iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_TXF)) 710 goto dump_internal_txf; 711 712 /* Count TXF sizes */ 713 if (WARN_ON(mem_cfg->num_lmacs > MAX_NUM_LMAC)) 714 mem_cfg->num_lmacs = MAX_NUM_LMAC; 715 716 for (i = 0; i < mem_cfg->num_lmacs; i++) { 717 int j; 718 719 for (j = 0; j < mem_cfg->num_txfifo_entries; j++) 720 ADD_LEN(fifo_len, mem_cfg->lmac[i].txfifo_size[j], 721 hdr_len); 722 } 723 724dump_internal_txf: 725 if (!(iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_INTERNAL_TXF) && 726 fw_has_capa(&fwrt->fw->ucode_capa, 727 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG))) 728 goto out; 729 730 for (i = 0; i < ARRAY_SIZE(mem_cfg->internal_txfifo_size); i++) 731 ADD_LEN(fifo_len, mem_cfg->internal_txfifo_size[i], hdr_len); 732 733out: 734 return fifo_len; 735} 736 737static void iwl_dump_paging(struct iwl_fw_runtime *fwrt, 738 struct iwl_fw_error_dump_data **data) 739{ 740 int i; 741 742 IWL_DEBUG_INFO(fwrt, "WRT paging dump\n"); 743 for (i = 1; i < fwrt->num_of_paging_blk + 1; i++) { 744 struct iwl_fw_error_dump_paging *paging; 745 struct page *pages = 746 fwrt->fw_paging_db[i].fw_paging_block; 747 dma_addr_t addr = fwrt->fw_paging_db[i].fw_paging_phys; 748 749 (*data)->type = cpu_to_le32(IWL_FW_ERROR_DUMP_PAGING); 750 (*data)->len = cpu_to_le32(sizeof(*paging) + 751 PAGING_BLOCK_SIZE); 752 paging = (void *)(*data)->data; 753 paging->index = cpu_to_le32(i); 754 dma_sync_single_for_cpu(fwrt->trans->dev, addr, 755 PAGING_BLOCK_SIZE, 756 DMA_BIDIRECTIONAL); 757 memcpy(paging->data, page_address(pages), 758 PAGING_BLOCK_SIZE); 759 dma_sync_single_for_device(fwrt->trans->dev, addr, 760 PAGING_BLOCK_SIZE, 761 DMA_BIDIRECTIONAL); 762 (*data) = iwl_fw_error_next_data(*data); 763 764 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 765 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 766 fwrt->fw_paging_db[i].fw_offs, 767 paging->data, 768 PAGING_BLOCK_SIZE); 769 } 770} 771 772static struct iwl_fw_error_dump_file * 773iwl_fw_error_dump_file(struct iwl_fw_runtime *fwrt, 774 struct iwl_fw_dump_ptrs *fw_error_dump, 775 struct iwl_fwrt_dump_data *data) 776{ 777 struct iwl_fw_error_dump_file *dump_file; 778 struct iwl_fw_error_dump_data *dump_data; 779 struct iwl_fw_error_dump_info *dump_info; 780 struct iwl_fw_error_dump_smem_cfg *dump_smem_cfg; 781 struct iwl_fw_error_dump_trigger_desc *dump_trig; 782 u32 sram_len, sram_ofs; 783 const struct iwl_fw_dbg_mem_seg_tlv *fw_mem = fwrt->fw->dbg.mem_tlv; 784 struct iwl_fwrt_shared_mem_cfg *mem_cfg = &fwrt->smem_cfg; 785 u32 file_len, fifo_len = 0, prph_len = 0, radio_len = 0; 786 u32 smem_len = fwrt->fw->dbg.n_mem_tlv ? 0 : fwrt->trans->cfg->smem_len; 787 u32 sram2_len = fwrt->fw->dbg.n_mem_tlv ? 788 0 : fwrt->trans->cfg->dccm2_len; 789 int i; 790 791 /* SRAM - include stack CCM if driver knows the values for it */ 792 if (!fwrt->trans->cfg->dccm_offset || !fwrt->trans->cfg->dccm_len) { 793 const struct fw_img *img; 794 795 if (fwrt->cur_fw_img >= IWL_UCODE_TYPE_MAX) 796 return NULL; 797 img = &fwrt->fw->img[fwrt->cur_fw_img]; 798 sram_ofs = img->sec[IWL_UCODE_SECTION_DATA].offset; 799 sram_len = img->sec[IWL_UCODE_SECTION_DATA].len; 800 } else { 801 sram_ofs = fwrt->trans->cfg->dccm_offset; 802 sram_len = fwrt->trans->cfg->dccm_len; 803 } 804 805 /* reading RXF/TXF sizes */ 806 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) { 807 fifo_len = iwl_fw_rxf_len(fwrt, mem_cfg); 808 fifo_len += iwl_fw_txf_len(fwrt, mem_cfg); 809 810 /* Make room for PRPH registers */ 811 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_PRPH)) 812 iwl_fw_prph_handler(fwrt, &prph_len, 813 iwl_fw_get_prph_len); 814 815 if (fwrt->trans->trans_cfg->device_family == 816 IWL_DEVICE_FAMILY_7000 && 817 iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_RADIO_REG)) 818 radio_len = sizeof(*dump_data) + RADIO_REG_MAX_READ; 819 } 820 821 file_len = sizeof(*dump_file) + fifo_len + prph_len + radio_len; 822 823 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) 824 file_len += sizeof(*dump_data) + sizeof(*dump_info); 825 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) 826 file_len += sizeof(*dump_data) + sizeof(*dump_smem_cfg); 827 828 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 829 size_t hdr_len = sizeof(*dump_data) + 830 sizeof(struct iwl_fw_error_dump_mem); 831 832 /* Dump SRAM only if no mem_tlvs */ 833 if (!fwrt->fw->dbg.n_mem_tlv) 834 ADD_LEN(file_len, sram_len, hdr_len); 835 836 /* Make room for all mem types that exist */ 837 ADD_LEN(file_len, smem_len, hdr_len); 838 ADD_LEN(file_len, sram2_len, hdr_len); 839 840 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) 841 ADD_LEN(file_len, le32_to_cpu(fw_mem[i].len), hdr_len); 842 } 843 844 /* Make room for fw's virtual image pages, if it exists */ 845 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 846 file_len += fwrt->num_of_paging_blk * 847 (sizeof(*dump_data) + 848 sizeof(struct iwl_fw_error_dump_paging) + 849 PAGING_BLOCK_SIZE); 850 851 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 852 file_len += sizeof(*dump_data) + 853 fwrt->trans->cfg->d3_debug_data_length * 2; 854 } 855 856 /* If we only want a monitor dump, reset the file length */ 857 if (data->monitor_only) { 858 file_len = sizeof(*dump_file) + sizeof(*dump_data) * 2 + 859 sizeof(*dump_info) + sizeof(*dump_smem_cfg); 860 } 861 862 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 863 data->desc) 864 file_len += sizeof(*dump_data) + sizeof(*dump_trig) + 865 data->desc->len; 866 867 dump_file = vzalloc(file_len); 868 if (!dump_file) 869 return NULL; 870 871 fw_error_dump->fwrt_ptr = dump_file; 872 873 dump_file->barker = cpu_to_le32(IWL_FW_ERROR_DUMP_BARKER); 874 dump_data = (void *)dump_file->data; 875 876 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_DEV_FW_INFO)) { 877 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_DEV_FW_INFO); 878 dump_data->len = cpu_to_le32(sizeof(*dump_info)); 879 dump_info = (void *)dump_data->data; 880 dump_info->hw_type = 881 cpu_to_le32(CSR_HW_REV_TYPE(fwrt->trans->hw_rev)); 882 dump_info->hw_step = 883 cpu_to_le32(fwrt->trans->hw_rev_step); 884 memcpy(dump_info->fw_human_readable, fwrt->fw->human_readable, 885 sizeof(dump_info->fw_human_readable)); 886 strncpy(dump_info->dev_human_readable, fwrt->trans->name, 887 sizeof(dump_info->dev_human_readable) - 1); 888#if defined(__linux__) 889 strncpy(dump_info->bus_human_readable, fwrt->dev->bus->name, 890 sizeof(dump_info->bus_human_readable) - 1); 891#elif defined(__FreeBSD__) /* XXX TODO */ 892 strncpy(dump_info->bus_human_readable, "<bus>", 893 sizeof(dump_info->bus_human_readable) - 1); 894#endif 895 dump_info->num_of_lmacs = fwrt->smem_cfg.num_lmacs; 896 dump_info->lmac_err_id[0] = 897 cpu_to_le32(fwrt->dump.lmac_err_id[0]); 898 if (fwrt->smem_cfg.num_lmacs > 1) 899 dump_info->lmac_err_id[1] = 900 cpu_to_le32(fwrt->dump.lmac_err_id[1]); 901 dump_info->umac_err_id = cpu_to_le32(fwrt->dump.umac_err_id); 902 903 dump_data = iwl_fw_error_next_data(dump_data); 904 } 905 906 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM_CFG)) { 907 /* Dump shared memory configuration */ 908 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_MEM_CFG); 909 dump_data->len = cpu_to_le32(sizeof(*dump_smem_cfg)); 910 dump_smem_cfg = (void *)dump_data->data; 911 dump_smem_cfg->num_lmacs = cpu_to_le32(mem_cfg->num_lmacs); 912 dump_smem_cfg->num_txfifo_entries = 913 cpu_to_le32(mem_cfg->num_txfifo_entries); 914 for (i = 0; i < MAX_NUM_LMAC; i++) { 915 int j; 916 u32 *txf_size = mem_cfg->lmac[i].txfifo_size; 917 918 for (j = 0; j < TX_FIFO_MAX_NUM; j++) 919 dump_smem_cfg->lmac[i].txfifo_size[j] = 920 cpu_to_le32(txf_size[j]); 921 dump_smem_cfg->lmac[i].rxfifo1_size = 922 cpu_to_le32(mem_cfg->lmac[i].rxfifo1_size); 923 } 924 dump_smem_cfg->rxfifo2_size = 925 cpu_to_le32(mem_cfg->rxfifo2_size); 926 dump_smem_cfg->internal_txfifo_addr = 927 cpu_to_le32(mem_cfg->internal_txfifo_addr); 928 for (i = 0; i < TX_FIFO_INTERNAL_MAX_NUM; i++) { 929 dump_smem_cfg->internal_txfifo_size[i] = 930 cpu_to_le32(mem_cfg->internal_txfifo_size[i]); 931 } 932 933 dump_data = iwl_fw_error_next_data(dump_data); 934 } 935 936 /* We only dump the FIFOs if the FW is in error state */ 937 if (fifo_len) { 938 iwl_fw_dump_rxf(fwrt, &dump_data); 939 iwl_fw_dump_txf(fwrt, &dump_data); 940 } 941 942 if (radio_len) 943 iwl_read_radio_regs(fwrt, &dump_data); 944 945 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_ERROR_INFO) && 946 data->desc) { 947 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_ERROR_INFO); 948 dump_data->len = cpu_to_le32(sizeof(*dump_trig) + 949 data->desc->len); 950 dump_trig = (void *)dump_data->data; 951 memcpy(dump_trig, &data->desc->trig_desc, 952 sizeof(*dump_trig) + data->desc->len); 953 954 dump_data = iwl_fw_error_next_data(dump_data); 955 } 956 957 /* In case we only want monitor dump, skip to dump trasport data */ 958 if (data->monitor_only) 959 goto out; 960 961 if (iwl_fw_dbg_type_on(fwrt, IWL_FW_ERROR_DUMP_MEM)) { 962 const struct iwl_fw_dbg_mem_seg_tlv *fw_dbg_mem = 963 fwrt->fw->dbg.mem_tlv; 964 965 if (!fwrt->fw->dbg.n_mem_tlv) 966 iwl_fw_dump_mem(fwrt, &dump_data, sram_len, sram_ofs, 967 IWL_FW_ERROR_DUMP_MEM_SRAM); 968 969 for (i = 0; i < fwrt->fw->dbg.n_mem_tlv; i++) { 970 u32 len = le32_to_cpu(fw_dbg_mem[i].len); 971 u32 ofs = le32_to_cpu(fw_dbg_mem[i].ofs); 972 973 iwl_fw_dump_mem(fwrt, &dump_data, len, ofs, 974 le32_to_cpu(fw_dbg_mem[i].data_type)); 975 } 976 977 iwl_fw_dump_mem(fwrt, &dump_data, smem_len, 978 fwrt->trans->cfg->smem_offset, 979 IWL_FW_ERROR_DUMP_MEM_SMEM); 980 981 iwl_fw_dump_mem(fwrt, &dump_data, sram2_len, 982 fwrt->trans->cfg->dccm2_offset, 983 IWL_FW_ERROR_DUMP_MEM_SRAM); 984 } 985 986 if (iwl_fw_dbg_is_d3_debug_enabled(fwrt) && fwrt->dump.d3_debug_data) { 987 u32 addr = fwrt->trans->cfg->d3_debug_data_base_addr; 988 size_t data_size = fwrt->trans->cfg->d3_debug_data_length; 989 990 dump_data->type = cpu_to_le32(IWL_FW_ERROR_DUMP_D3_DEBUG_DATA); 991 dump_data->len = cpu_to_le32(data_size * 2); 992 993 memcpy(dump_data->data, fwrt->dump.d3_debug_data, data_size); 994 995 kfree(fwrt->dump.d3_debug_data); 996 fwrt->dump.d3_debug_data = NULL; 997 998 iwl_trans_read_mem_bytes(fwrt->trans, addr, 999 dump_data->data + data_size, 1000 data_size); 1001 1002 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 1003 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, addr, 1004 dump_data->data + data_size, 1005 data_size); 1006 1007 dump_data = iwl_fw_error_next_data(dump_data); 1008 } 1009 1010 /* Dump fw's virtual image */ 1011 if (iwl_fw_dbg_is_paging_enabled(fwrt)) 1012 iwl_dump_paging(fwrt, &dump_data); 1013 1014 if (prph_len) 1015 iwl_fw_prph_handler(fwrt, &dump_data, iwl_dump_prph); 1016 1017out: 1018 dump_file->file_len = cpu_to_le32(file_len); 1019 return dump_file; 1020} 1021 1022/** 1023 * struct iwl_dump_ini_region_data - region data 1024 * @reg_tlv: region TLV 1025 * @dump_data: dump data 1026 */ 1027struct iwl_dump_ini_region_data { 1028 struct iwl_ucode_tlv *reg_tlv; 1029 struct iwl_fwrt_dump_data *dump_data; 1030}; 1031 1032static int 1033iwl_dump_ini_prph_mac_iter(struct iwl_fw_runtime *fwrt, 1034 struct iwl_dump_ini_region_data *reg_data, 1035 void *range_ptr, u32 range_len, int idx) 1036{ 1037 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1038 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1039 __le32 *val = range->data; 1040 u32 prph_val; 1041 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1042 le32_to_cpu(reg->dev_addr.offset); 1043 int i; 1044 1045 range->internal_base_addr = cpu_to_le32(addr); 1046 range->range_data_size = reg->dev_addr.size; 1047 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1048 prph_val = iwl_read_prph(fwrt->trans, addr + i); 1049 if (iwl_trans_is_hw_error_value(prph_val)) 1050 return -EBUSY; 1051 *val++ = cpu_to_le32(prph_val); 1052 } 1053 1054 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1055} 1056 1057static int 1058iwl_dump_ini_prph_phy_iter(struct iwl_fw_runtime *fwrt, 1059 struct iwl_dump_ini_region_data *reg_data, 1060 void *range_ptr, u32 range_len, int idx) 1061{ 1062 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1063 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1064 __le32 *val = range->data; 1065 u32 indirect_wr_addr = WMAL_INDRCT_RD_CMD1; 1066 u32 indirect_rd_addr = WMAL_MRSPF_1; 1067 u32 prph_val; 1068 u32 addr = le32_to_cpu(reg->addrs[idx]); 1069 u32 dphy_state; 1070 u32 dphy_addr; 1071 int i; 1072 1073 range->internal_base_addr = cpu_to_le32(addr); 1074 range->range_data_size = reg->dev_addr.size; 1075 1076 if (fwrt->trans->trans_cfg->device_family < IWL_DEVICE_FAMILY_AX210) 1077 indirect_wr_addr = WMAL_INDRCT_CMD1; 1078 1079 indirect_wr_addr += le32_to_cpu(reg->dev_addr.offset); 1080 indirect_rd_addr += le32_to_cpu(reg->dev_addr.offset); 1081 1082 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1083 return -EBUSY; 1084 1085 dphy_addr = (reg->dev_addr.offset) ? WFPM_LMAC2_PS_CTL_RW : 1086 WFPM_LMAC1_PS_CTL_RW; 1087 dphy_state = iwl_read_umac_prph_no_grab(fwrt->trans, dphy_addr); 1088 1089 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1090 if (dphy_state == HBUS_TIMEOUT || 1091 (dphy_state & WFPM_PS_CTL_RW_PHYRF_PD_FSM_CURSTATE_MSK) != 1092 WFPM_PHYRF_STATE_ON) { 1093 *val++ = cpu_to_le32(WFPM_DPHY_OFF); 1094 continue; 1095 } 1096 1097 iwl_write_prph_no_grab(fwrt->trans, indirect_wr_addr, 1098 WMAL_INDRCT_CMD(addr + i)); 1099 prph_val = iwl_read_prph_no_grab(fwrt->trans, 1100 indirect_rd_addr); 1101 *val++ = cpu_to_le32(prph_val); 1102 } 1103 1104 iwl_trans_release_nic_access(fwrt->trans); 1105 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1106} 1107 1108static int iwl_dump_ini_csr_iter(struct iwl_fw_runtime *fwrt, 1109 struct iwl_dump_ini_region_data *reg_data, 1110 void *range_ptr, u32 range_len, int idx) 1111{ 1112 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1113 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1114 __le32 *val = range->data; 1115 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1116 le32_to_cpu(reg->dev_addr.offset); 1117 int i; 1118 1119 range->internal_base_addr = cpu_to_le32(addr); 1120 range->range_data_size = reg->dev_addr.size; 1121 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) 1122 *val++ = cpu_to_le32(iwl_trans_read32(fwrt->trans, addr + i)); 1123 1124 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1125} 1126 1127static int iwl_dump_ini_config_iter(struct iwl_fw_runtime *fwrt, 1128 struct iwl_dump_ini_region_data *reg_data, 1129 void *range_ptr, u32 range_len, int idx) 1130{ 1131 struct iwl_trans *trans = fwrt->trans; 1132 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1133 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1134 __le32 *val = range->data; 1135 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1136 le32_to_cpu(reg->dev_addr.offset); 1137 int i; 1138 1139 /* we shouldn't get here if the trans doesn't have read_config32 */ 1140 if (WARN_ON_ONCE(!trans->ops->read_config32)) 1141 return -EOPNOTSUPP; 1142 1143 range->internal_base_addr = cpu_to_le32(addr); 1144 range->range_data_size = reg->dev_addr.size; 1145 for (i = 0; i < le32_to_cpu(reg->dev_addr.size); i += 4) { 1146 int ret; 1147 u32 tmp; 1148 1149 ret = trans->ops->read_config32(trans, addr + i, &tmp); 1150 if (ret < 0) 1151 return ret; 1152 1153 *val++ = cpu_to_le32(tmp); 1154 } 1155 1156 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1157} 1158 1159static int iwl_dump_ini_dev_mem_iter(struct iwl_fw_runtime *fwrt, 1160 struct iwl_dump_ini_region_data *reg_data, 1161 void *range_ptr, u32 range_len, int idx) 1162{ 1163 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1164 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1165 u32 addr = le32_to_cpu(reg->addrs[idx]) + 1166 le32_to_cpu(reg->dev_addr.offset); 1167 1168 range->internal_base_addr = cpu_to_le32(addr); 1169 range->range_data_size = reg->dev_addr.size; 1170 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1171 le32_to_cpu(reg->dev_addr.size)); 1172 1173 if (reg->sub_type == IWL_FW_INI_REGION_DEVICE_MEMORY_SUBTYPE_HW_SMEM && 1174 fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1175 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1176 range->data, 1177 le32_to_cpu(reg->dev_addr.size)); 1178 1179 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1180} 1181 1182static int _iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1183 void *range_ptr, u32 range_len, int idx) 1184{ 1185 struct page *page = fwrt->fw_paging_db[idx].fw_paging_block; 1186 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1187 dma_addr_t addr = fwrt->fw_paging_db[idx].fw_paging_phys; 1188 u32 page_size = fwrt->fw_paging_db[idx].fw_paging_size; 1189 1190 range->page_num = cpu_to_le32(idx); 1191 range->range_data_size = cpu_to_le32(page_size); 1192 dma_sync_single_for_cpu(fwrt->trans->dev, addr, page_size, 1193 DMA_BIDIRECTIONAL); 1194 memcpy(range->data, page_address(page), page_size); 1195 dma_sync_single_for_device(fwrt->trans->dev, addr, page_size, 1196 DMA_BIDIRECTIONAL); 1197 1198 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1199} 1200 1201static int iwl_dump_ini_paging_iter(struct iwl_fw_runtime *fwrt, 1202 struct iwl_dump_ini_region_data *reg_data, 1203 void *range_ptr, u32 range_len, int idx) 1204{ 1205 struct iwl_fw_ini_error_dump_range *range; 1206 u32 page_size; 1207 1208 /* all paged index start from 1 to skip CSS section */ 1209 idx++; 1210 1211 if (!fwrt->trans->trans_cfg->gen2) 1212 return _iwl_dump_ini_paging_iter(fwrt, range_ptr, range_len, idx); 1213 1214 range = range_ptr; 1215 page_size = fwrt->trans->init_dram.paging[idx].size; 1216 1217 range->page_num = cpu_to_le32(idx); 1218 range->range_data_size = cpu_to_le32(page_size); 1219 memcpy(range->data, fwrt->trans->init_dram.paging[idx].block, 1220 page_size); 1221 1222 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1223} 1224 1225static int 1226iwl_dump_ini_mon_dram_iter(struct iwl_fw_runtime *fwrt, 1227 struct iwl_dump_ini_region_data *reg_data, 1228 void *range_ptr, u32 range_len, int idx) 1229{ 1230 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1231 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1232 struct iwl_dram_data *frag; 1233 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1234 1235 frag = &fwrt->trans->dbg.fw_mon_ini[alloc_id].frags[idx]; 1236 1237 range->dram_base_addr = cpu_to_le64(frag->physical); 1238 range->range_data_size = cpu_to_le32(frag->size); 1239 1240 memcpy(range->data, frag->block, frag->size); 1241 1242 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1243} 1244 1245static int iwl_dump_ini_mon_smem_iter(struct iwl_fw_runtime *fwrt, 1246 struct iwl_dump_ini_region_data *reg_data, 1247 void *range_ptr, u32 range_len, int idx) 1248{ 1249 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1250 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1251 u32 addr = le32_to_cpu(reg->internal_buffer.base_addr); 1252 1253 range->internal_base_addr = cpu_to_le32(addr); 1254 range->range_data_size = reg->internal_buffer.size; 1255 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1256 le32_to_cpu(reg->internal_buffer.size)); 1257 1258 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1259} 1260 1261static bool iwl_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1262 struct iwl_dump_ini_region_data *reg_data, int idx) 1263{ 1264 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1265 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1266 struct iwl_fwrt_shared_mem_cfg *cfg = &fwrt->smem_cfg; 1267 int txf_num = cfg->num_txfifo_entries; 1268 int int_txf_num = ARRAY_SIZE(cfg->internal_txfifo_size); 1269 u32 lmac_bitmap = le32_to_cpu(reg->fifos.fid[0]); 1270 1271 if (!idx) { 1272 if (le32_to_cpu(reg->fifos.offset) && cfg->num_lmacs == 1) { 1273 IWL_ERR(fwrt, "WRT: Invalid lmac offset 0x%x\n", 1274 le32_to_cpu(reg->fifos.offset)); 1275 return false; 1276 } 1277 1278 iter->internal_txf = 0; 1279 iter->fifo_size = 0; 1280 iter->fifo = -1; 1281 if (le32_to_cpu(reg->fifos.offset)) 1282 iter->lmac = 1; 1283 else 1284 iter->lmac = 0; 1285 } 1286 1287 if (!iter->internal_txf) { 1288 for (iter->fifo++; iter->fifo < txf_num; iter->fifo++) { 1289 iter->fifo_size = 1290 cfg->lmac[iter->lmac].txfifo_size[iter->fifo]; 1291 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1292 return true; 1293 } 1294 iter->fifo--; 1295 } 1296 1297 iter->internal_txf = 1; 1298 1299 if (!fw_has_capa(&fwrt->fw->ucode_capa, 1300 IWL_UCODE_TLV_CAPA_EXTEND_SHARED_MEM_CFG)) 1301 return false; 1302 1303 for (iter->fifo++; iter->fifo < int_txf_num + txf_num; iter->fifo++) { 1304 iter->fifo_size = 1305 cfg->internal_txfifo_size[iter->fifo - txf_num]; 1306 if (iter->fifo_size && (lmac_bitmap & BIT(iter->fifo))) 1307 return true; 1308 } 1309 1310 return false; 1311} 1312 1313static int iwl_dump_ini_txf_iter(struct iwl_fw_runtime *fwrt, 1314 struct iwl_dump_ini_region_data *reg_data, 1315 void *range_ptr, u32 range_len, int idx) 1316{ 1317 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1318 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1319 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1320 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1321 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1322 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1323 u32 registers_size = registers_num * sizeof(*reg_dump); 1324 __le32 *data; 1325 int i; 1326 1327 if (!iwl_ini_txf_iter(fwrt, reg_data, idx)) 1328 return -EIO; 1329 1330 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1331 return -EBUSY; 1332 1333 range->fifo_hdr.fifo_num = cpu_to_le32(iter->fifo); 1334 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1335 range->range_data_size = cpu_to_le32(iter->fifo_size + registers_size); 1336 1337 iwl_write_prph_no_grab(fwrt->trans, TXF_LARC_NUM + offs, iter->fifo); 1338 1339 /* 1340 * read txf registers. for each register, write to the dump the 1341 * register address and its value 1342 */ 1343 for (i = 0; i < registers_num; i++) { 1344 addr = le32_to_cpu(reg->addrs[i]) + offs; 1345 1346 reg_dump->addr = cpu_to_le32(addr); 1347 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1348 addr)); 1349 1350 reg_dump++; 1351 } 1352 1353 if (reg->fifos.hdr_only) { 1354 range->range_data_size = cpu_to_le32(registers_size); 1355 goto out; 1356 } 1357 1358 /* Set the TXF_READ_MODIFY_ADDR to TXF_WR_PTR */ 1359 iwl_write_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_ADDR + offs, 1360 TXF_WR_PTR + offs); 1361 1362 /* Dummy-read to advance the read pointer to the head */ 1363 iwl_read_prph_no_grab(fwrt->trans, TXF_READ_MODIFY_DATA + offs); 1364 1365 /* Read FIFO */ 1366 addr = TXF_READ_MODIFY_DATA + offs; 1367 data = (void *)reg_dump; 1368 for (i = 0; i < iter->fifo_size; i += sizeof(*data)) 1369 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1370 1371 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_txf) 1372 fwrt->sanitize_ops->frob_txf(fwrt->sanitize_ctx, 1373 reg_dump, iter->fifo_size); 1374 1375out: 1376 iwl_trans_release_nic_access(fwrt->trans); 1377 1378 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1379} 1380 1381struct iwl_ini_rxf_data { 1382 u32 fifo_num; 1383 u32 size; 1384 u32 offset; 1385}; 1386 1387static void iwl_ini_get_rxf_data(struct iwl_fw_runtime *fwrt, 1388 struct iwl_dump_ini_region_data *reg_data, 1389 struct iwl_ini_rxf_data *data) 1390{ 1391 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1392 u32 fid1 = le32_to_cpu(reg->fifos.fid[0]); 1393 u32 fid2 = le32_to_cpu(reg->fifos.fid[1]); 1394 u8 fifo_idx; 1395 1396 if (!data) 1397 return; 1398 1399 memset(data, 0, sizeof(*data)); 1400 1401 /* make sure only one bit is set in only one fid */ 1402 if (WARN_ONCE(hweight_long(fid1) + hweight_long(fid2) != 1, 1403 "fid1=%x, fid2=%x\n", fid1, fid2)) 1404 return; 1405 1406 if (fid1) { 1407 fifo_idx = ffs(fid1) - 1; 1408 if (WARN_ONCE(fifo_idx >= MAX_NUM_LMAC, "fifo_idx=%d\n", 1409 fifo_idx)) 1410 return; 1411 1412 data->size = fwrt->smem_cfg.lmac[fifo_idx].rxfifo1_size; 1413 data->fifo_num = fifo_idx; 1414 } else { 1415 u8 max_idx; 1416 1417 fifo_idx = ffs(fid2) - 1; 1418 if (iwl_fw_lookup_notif_ver(fwrt->fw, SYSTEM_GROUP, 1419 SHARED_MEM_CFG_CMD, 0) <= 3) 1420 max_idx = 0; 1421 else 1422 max_idx = 1; 1423 1424 if (WARN_ONCE(fifo_idx > max_idx, 1425 "invalid umac fifo idx %d", fifo_idx)) 1426 return; 1427 1428 /* use bit 31 to distinguish between umac and lmac rxf while 1429 * parsing the dump 1430 */ 1431 data->fifo_num = fifo_idx | IWL_RXF_UMAC_BIT; 1432 1433 switch (fifo_idx) { 1434 case 0: 1435 data->size = fwrt->smem_cfg.rxfifo2_size; 1436 data->offset = iwl_umac_prph(fwrt->trans, 1437 RXF_DIFF_FROM_PREV); 1438 break; 1439 case 1: 1440 data->size = fwrt->smem_cfg.rxfifo2_control_size; 1441 data->offset = iwl_umac_prph(fwrt->trans, 1442 RXF2C_DIFF_FROM_PREV); 1443 break; 1444 } 1445 } 1446} 1447 1448static int iwl_dump_ini_rxf_iter(struct iwl_fw_runtime *fwrt, 1449 struct iwl_dump_ini_region_data *reg_data, 1450 void *range_ptr, u32 range_len, int idx) 1451{ 1452 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1453 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1454 struct iwl_ini_rxf_data rxf_data; 1455 struct iwl_fw_ini_error_dump_register *reg_dump = (void *)range->data; 1456 u32 offs = le32_to_cpu(reg->fifos.offset), addr; 1457 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1458 u32 registers_size = registers_num * sizeof(*reg_dump); 1459 __le32 *data; 1460 int i; 1461 1462#if defined(__FreeBSD__) 1463 rxf_data.size = 0; 1464#endif 1465 iwl_ini_get_rxf_data(fwrt, reg_data, &rxf_data); 1466 if (!rxf_data.size) 1467 return -EIO; 1468 1469 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1470 return -EBUSY; 1471 1472 range->fifo_hdr.fifo_num = cpu_to_le32(rxf_data.fifo_num); 1473 range->fifo_hdr.num_of_registers = cpu_to_le32(registers_num); 1474 range->range_data_size = cpu_to_le32(rxf_data.size + registers_size); 1475 1476 /* 1477 * read rxf registers. for each register, write to the dump the 1478 * register address and its value 1479 */ 1480 for (i = 0; i < registers_num; i++) { 1481 addr = le32_to_cpu(reg->addrs[i]) + offs; 1482 1483 reg_dump->addr = cpu_to_le32(addr); 1484 reg_dump->data = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, 1485 addr)); 1486 1487 reg_dump++; 1488 } 1489 1490 if (reg->fifos.hdr_only) { 1491 range->range_data_size = cpu_to_le32(registers_size); 1492 goto out; 1493 } 1494 1495 offs = rxf_data.offset; 1496 1497 /* Lock fence */ 1498 iwl_write_prph_no_grab(fwrt->trans, RXF_SET_FENCE_MODE + offs, 0x1); 1499 /* Set fence pointer to the same place like WR pointer */ 1500 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_WR2FENCE + offs, 0x1); 1501 /* Set fence offset */ 1502 iwl_write_prph_no_grab(fwrt->trans, RXF_LD_FENCE_OFFSET_ADDR + offs, 1503 0x0); 1504 1505 /* Read FIFO */ 1506 addr = RXF_FIFO_RD_FENCE_INC + offs; 1507 data = (void *)reg_dump; 1508 for (i = 0; i < rxf_data.size; i += sizeof(*data)) 1509 *data++ = cpu_to_le32(iwl_read_prph_no_grab(fwrt->trans, addr)); 1510 1511out: 1512 iwl_trans_release_nic_access(fwrt->trans); 1513 1514 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1515} 1516 1517static int 1518iwl_dump_ini_err_table_iter(struct iwl_fw_runtime *fwrt, 1519 struct iwl_dump_ini_region_data *reg_data, 1520 void *range_ptr, u32 range_len, int idx) 1521{ 1522 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1523 struct iwl_fw_ini_region_err_table *err_table = ®->err_table; 1524 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1525 u32 addr = le32_to_cpu(err_table->base_addr) + 1526 le32_to_cpu(err_table->offset); 1527 1528 range->internal_base_addr = cpu_to_le32(addr); 1529 range->range_data_size = err_table->size; 1530 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1531 le32_to_cpu(err_table->size)); 1532 1533 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1534} 1535 1536static int 1537iwl_dump_ini_special_mem_iter(struct iwl_fw_runtime *fwrt, 1538 struct iwl_dump_ini_region_data *reg_data, 1539 void *range_ptr, u32 range_len, int idx) 1540{ 1541 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1542 struct iwl_fw_ini_region_special_device_memory *special_mem = 1543 ®->special_mem; 1544 1545 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1546 u32 addr = le32_to_cpu(special_mem->base_addr) + 1547 le32_to_cpu(special_mem->offset); 1548 1549 range->internal_base_addr = cpu_to_le32(addr); 1550 range->range_data_size = special_mem->size; 1551 iwl_trans_read_mem_bytes(fwrt->trans, addr, range->data, 1552 le32_to_cpu(special_mem->size)); 1553 1554 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1555} 1556 1557static int 1558iwl_dump_ini_dbgi_sram_iter(struct iwl_fw_runtime *fwrt, 1559 struct iwl_dump_ini_region_data *reg_data, 1560 void *range_ptr, u32 range_len, int idx) 1561{ 1562 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1563 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1564 __le32 *val = range->data; 1565 u32 prph_data; 1566 int i; 1567 1568 if (!iwl_trans_grab_nic_access(fwrt->trans)) 1569 return -EBUSY; 1570 1571 range->range_data_size = reg->dev_addr.size; 1572 for (i = 0; i < (le32_to_cpu(reg->dev_addr.size) / 4); i++) { 1573 prph_data = iwl_read_prph_no_grab(fwrt->trans, (i % 2) ? 1574 DBGI_SRAM_TARGET_ACCESS_RDATA_MSB : 1575 DBGI_SRAM_TARGET_ACCESS_RDATA_LSB); 1576 if (iwl_trans_is_hw_error_value(prph_data)) { 1577 iwl_trans_release_nic_access(fwrt->trans); 1578 return -EBUSY; 1579 } 1580 *val++ = cpu_to_le32(prph_data); 1581 } 1582 iwl_trans_release_nic_access(fwrt->trans); 1583 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1584} 1585 1586static int iwl_dump_ini_fw_pkt_iter(struct iwl_fw_runtime *fwrt, 1587 struct iwl_dump_ini_region_data *reg_data, 1588 void *range_ptr, u32 range_len, int idx) 1589{ 1590 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1591 struct iwl_rx_packet *pkt = reg_data->dump_data->fw_pkt; 1592 u32 pkt_len; 1593 1594 if (!pkt) 1595 return -EIO; 1596 1597 pkt_len = iwl_rx_packet_payload_len(pkt); 1598 1599 memcpy(&range->fw_pkt_hdr, &pkt->hdr, sizeof(range->fw_pkt_hdr)); 1600 range->range_data_size = cpu_to_le32(pkt_len); 1601 1602 memcpy(range->data, pkt->data, pkt_len); 1603 1604 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1605} 1606 1607static int iwl_dump_ini_imr_iter(struct iwl_fw_runtime *fwrt, 1608 struct iwl_dump_ini_region_data *reg_data, 1609 void *range_ptr, u32 range_len, int idx) 1610{ 1611 /* read the IMR memory and DMA it to SRAM */ 1612 struct iwl_fw_ini_error_dump_range *range = range_ptr; 1613 u64 imr_curr_addr = fwrt->trans->dbg.imr_data.imr_curr_addr; 1614 u32 imr_rem_bytes = fwrt->trans->dbg.imr_data.imr2sram_remainbyte; 1615 u32 sram_addr = fwrt->trans->dbg.imr_data.sram_addr; 1616 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1617 u32 size_to_dump = (imr_rem_bytes > sram_size) ? sram_size : imr_rem_bytes; 1618 1619 range->range_data_size = cpu_to_le32(size_to_dump); 1620 if (iwl_trans_write_imr_mem(fwrt->trans, sram_addr, 1621 imr_curr_addr, size_to_dump)) { 1622 IWL_ERR(fwrt, "WRT_DEBUG: IMR Memory transfer failed\n"); 1623 return -1; 1624 } 1625 1626 fwrt->trans->dbg.imr_data.imr_curr_addr = imr_curr_addr + size_to_dump; 1627 fwrt->trans->dbg.imr_data.imr2sram_remainbyte -= size_to_dump; 1628 1629 iwl_trans_read_mem_bytes(fwrt->trans, sram_addr, range->data, 1630 size_to_dump); 1631 return sizeof(*range) + le32_to_cpu(range->range_data_size); 1632} 1633 1634static void * 1635iwl_dump_ini_mem_fill_header(struct iwl_fw_runtime *fwrt, 1636 struct iwl_dump_ini_region_data *reg_data, 1637 void *data, u32 data_len) 1638{ 1639 struct iwl_fw_ini_error_dump *dump = data; 1640 1641 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1642 1643 return dump->data; 1644} 1645 1646/** 1647 * mask_apply_and_normalize - applies mask on val and normalize the result 1648 * 1649 * The normalization is based on the first set bit in the mask 1650 * 1651 * @val: value 1652 * @mask: mask to apply and to normalize with 1653 */ 1654static u32 mask_apply_and_normalize(u32 val, u32 mask) 1655{ 1656 return (val & mask) >> (ffs(mask) - 1); 1657} 1658 1659static __le32 iwl_get_mon_reg(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1660 const struct iwl_fw_mon_reg *reg_info) 1661{ 1662 u32 val, offs; 1663 1664 /* The header addresses of DBGCi is calculate as follows: 1665 * DBGC1 address + (0x100 * i) 1666 */ 1667 offs = (alloc_id - IWL_FW_INI_ALLOCATION_ID_DBGC1) * 0x100; 1668 1669 if (!reg_info || !reg_info->addr || !reg_info->mask) 1670 return 0; 1671 1672 val = iwl_read_prph_no_grab(fwrt->trans, reg_info->addr + offs); 1673 1674 return cpu_to_le32(mask_apply_and_normalize(val, reg_info->mask)); 1675} 1676 1677static void * 1678iwl_dump_ini_mon_fill_header(struct iwl_fw_runtime *fwrt, u32 alloc_id, 1679 struct iwl_fw_ini_monitor_dump *data, 1680 const struct iwl_fw_mon_regs *addrs) 1681{ 1682 if (!iwl_trans_grab_nic_access(fwrt->trans)) { 1683 IWL_ERR(fwrt, "Failed to get monitor header\n"); 1684 return NULL; 1685 } 1686 1687 data->write_ptr = iwl_get_mon_reg(fwrt, alloc_id, 1688 &addrs->write_ptr); 1689 if (fwrt->trans->trans_cfg->device_family >= IWL_DEVICE_FAMILY_AX210) { 1690 u32 wrt_ptr = le32_to_cpu(data->write_ptr); 1691 1692 data->write_ptr = cpu_to_le32(wrt_ptr >> 2); 1693 } 1694 data->cycle_cnt = iwl_get_mon_reg(fwrt, alloc_id, 1695 &addrs->cycle_cnt); 1696 data->cur_frag = iwl_get_mon_reg(fwrt, alloc_id, 1697 &addrs->cur_frag); 1698 1699 iwl_trans_release_nic_access(fwrt->trans); 1700 1701 data->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1702 1703 return data->data; 1704} 1705 1706static void * 1707iwl_dump_ini_mon_dram_fill_header(struct iwl_fw_runtime *fwrt, 1708 struct iwl_dump_ini_region_data *reg_data, 1709 void *data, u32 data_len) 1710{ 1711 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1712 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1713 u32 alloc_id = le32_to_cpu(reg->dram_alloc_id); 1714 1715 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1716 &fwrt->trans->cfg->mon_dram_regs); 1717} 1718 1719static void * 1720iwl_dump_ini_mon_smem_fill_header(struct iwl_fw_runtime *fwrt, 1721 struct iwl_dump_ini_region_data *reg_data, 1722 void *data, u32 data_len) 1723{ 1724 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1725 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1726 u32 alloc_id = le32_to_cpu(reg->internal_buffer.alloc_id); 1727 1728 return iwl_dump_ini_mon_fill_header(fwrt, alloc_id, mon_dump, 1729 &fwrt->trans->cfg->mon_smem_regs); 1730} 1731 1732static void * 1733iwl_dump_ini_mon_dbgi_fill_header(struct iwl_fw_runtime *fwrt, 1734 struct iwl_dump_ini_region_data *reg_data, 1735 void *data, u32 data_len) 1736{ 1737 struct iwl_fw_ini_monitor_dump *mon_dump = (void *)data; 1738 1739 return iwl_dump_ini_mon_fill_header(fwrt, 1740 /* no offset calculation later */ 1741 IWL_FW_INI_ALLOCATION_ID_DBGC1, 1742 mon_dump, 1743 &fwrt->trans->cfg->mon_dbgi_regs); 1744} 1745 1746static void * 1747iwl_dump_ini_err_table_fill_header(struct iwl_fw_runtime *fwrt, 1748 struct iwl_dump_ini_region_data *reg_data, 1749 void *data, u32 data_len) 1750{ 1751 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1752 struct iwl_fw_ini_err_table_dump *dump = data; 1753 1754 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1755 dump->version = reg->err_table.version; 1756 1757 return dump->data; 1758} 1759 1760static void * 1761iwl_dump_ini_special_mem_fill_header(struct iwl_fw_runtime *fwrt, 1762 struct iwl_dump_ini_region_data *reg_data, 1763 void *data, u32 data_len) 1764{ 1765 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1766 struct iwl_fw_ini_special_device_memory *dump = data; 1767 1768 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1769 dump->type = reg->special_mem.type; 1770 dump->version = reg->special_mem.version; 1771 1772 return dump->data; 1773} 1774 1775static void * 1776iwl_dump_ini_imr_fill_header(struct iwl_fw_runtime *fwrt, 1777 struct iwl_dump_ini_region_data *reg_data, 1778 void *data, u32 data_len) 1779{ 1780 struct iwl_fw_ini_error_dump *dump = data; 1781 1782 dump->header.version = cpu_to_le32(IWL_INI_DUMP_VER); 1783 1784 return dump->data; 1785} 1786 1787static u32 iwl_dump_ini_mem_ranges(struct iwl_fw_runtime *fwrt, 1788 struct iwl_dump_ini_region_data *reg_data) 1789{ 1790 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1791 1792 return iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1793} 1794 1795static u32 iwl_dump_ini_paging_ranges(struct iwl_fw_runtime *fwrt, 1796 struct iwl_dump_ini_region_data *reg_data) 1797{ 1798 if (fwrt->trans->trans_cfg->gen2) { 1799 if (fwrt->trans->init_dram.paging_cnt) 1800 return fwrt->trans->init_dram.paging_cnt - 1; 1801 else 1802 return 0; 1803 } 1804 1805 return fwrt->num_of_paging_blk; 1806} 1807 1808static u32 1809iwl_dump_ini_mon_dram_ranges(struct iwl_fw_runtime *fwrt, 1810 struct iwl_dump_ini_region_data *reg_data) 1811{ 1812 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1813 struct iwl_fw_mon *fw_mon; 1814 u32 ranges = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1815 int i; 1816 1817 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1818 1819 for (i = 0; i < fw_mon->num_frags; i++) { 1820 if (!fw_mon->frags[i].size) 1821 break; 1822 1823 ranges++; 1824 } 1825 1826 return ranges; 1827} 1828 1829static u32 iwl_dump_ini_txf_ranges(struct iwl_fw_runtime *fwrt, 1830 struct iwl_dump_ini_region_data *reg_data) 1831{ 1832 u32 num_of_fifos = 0; 1833 1834 while (iwl_ini_txf_iter(fwrt, reg_data, num_of_fifos)) 1835 num_of_fifos++; 1836 1837 return num_of_fifos; 1838} 1839 1840static u32 iwl_dump_ini_single_range(struct iwl_fw_runtime *fwrt, 1841 struct iwl_dump_ini_region_data *reg_data) 1842{ 1843 return 1; 1844} 1845 1846static u32 iwl_dump_ini_imr_ranges(struct iwl_fw_runtime *fwrt, 1847 struct iwl_dump_ini_region_data *reg_data) 1848{ 1849 /* range is total number of pages need to copied from 1850 *IMR memory to SRAM and later from SRAM to DRAM 1851 */ 1852 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 1853 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 1854 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 1855 1856 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 1857 IWL_DEBUG_INFO(fwrt, 1858 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 1859 imr_enable, imr_size, sram_size); 1860 return 0; 1861 } 1862 1863 return((imr_size % sram_size) ? (imr_size / sram_size + 1) : (imr_size / sram_size)); 1864} 1865 1866static u32 iwl_dump_ini_mem_get_size(struct iwl_fw_runtime *fwrt, 1867 struct iwl_dump_ini_region_data *reg_data) 1868{ 1869 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1870 u32 size = le32_to_cpu(reg->dev_addr.size); 1871 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1872 1873 if (!size || !ranges) 1874 return 0; 1875 1876 return sizeof(struct iwl_fw_ini_error_dump) + ranges * 1877 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1878} 1879 1880static u32 1881iwl_dump_ini_paging_get_size(struct iwl_fw_runtime *fwrt, 1882 struct iwl_dump_ini_region_data *reg_data) 1883{ 1884 int i; 1885 u32 range_header_len = sizeof(struct iwl_fw_ini_error_dump_range); 1886 u32 size = sizeof(struct iwl_fw_ini_error_dump); 1887 1888 /* start from 1 to skip CSS section */ 1889 for (i = 1; i <= iwl_dump_ini_paging_ranges(fwrt, reg_data); i++) { 1890 size += range_header_len; 1891 if (fwrt->trans->trans_cfg->gen2) 1892 size += fwrt->trans->init_dram.paging[i].size; 1893 else 1894 size += fwrt->fw_paging_db[i].fw_paging_size; 1895 } 1896 1897 return size; 1898} 1899 1900static u32 1901iwl_dump_ini_mon_dram_get_size(struct iwl_fw_runtime *fwrt, 1902 struct iwl_dump_ini_region_data *reg_data) 1903{ 1904 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1905 struct iwl_fw_mon *fw_mon; 1906 u32 size = 0, alloc_id = le32_to_cpu(reg->dram_alloc_id); 1907 int i; 1908 1909 fw_mon = &fwrt->trans->dbg.fw_mon_ini[alloc_id]; 1910 1911 for (i = 0; i < fw_mon->num_frags; i++) { 1912 struct iwl_dram_data *frag = &fw_mon->frags[i]; 1913 1914 if (!frag->size) 1915 break; 1916 1917 size += sizeof(struct iwl_fw_ini_error_dump_range) + frag->size; 1918 } 1919 1920 if (size) 1921 size += sizeof(struct iwl_fw_ini_monitor_dump); 1922 1923 return size; 1924} 1925 1926static u32 1927iwl_dump_ini_mon_smem_get_size(struct iwl_fw_runtime *fwrt, 1928 struct iwl_dump_ini_region_data *reg_data) 1929{ 1930 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1931 u32 size; 1932 1933 size = le32_to_cpu(reg->internal_buffer.size); 1934 if (!size) 1935 return 0; 1936 1937 size += sizeof(struct iwl_fw_ini_monitor_dump) + 1938 sizeof(struct iwl_fw_ini_error_dump_range); 1939 1940 return size; 1941} 1942 1943static u32 iwl_dump_ini_mon_dbgi_get_size(struct iwl_fw_runtime *fwrt, 1944 struct iwl_dump_ini_region_data *reg_data) 1945{ 1946 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1947 u32 size = le32_to_cpu(reg->dev_addr.size); 1948 u32 ranges = iwl_dump_ini_mem_ranges(fwrt, reg_data); 1949 1950 if (!size || !ranges) 1951 return 0; 1952 1953 return sizeof(struct iwl_fw_ini_monitor_dump) + ranges * 1954 (size + sizeof(struct iwl_fw_ini_error_dump_range)); 1955} 1956 1957static u32 iwl_dump_ini_txf_get_size(struct iwl_fw_runtime *fwrt, 1958 struct iwl_dump_ini_region_data *reg_data) 1959{ 1960 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1961 struct iwl_txf_iter_data *iter = &fwrt->dump.txf_iter_data; 1962 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1963 u32 size = 0; 1964 u32 fifo_hdr = sizeof(struct iwl_fw_ini_error_dump_range) + 1965 registers_num * 1966 sizeof(struct iwl_fw_ini_error_dump_register); 1967 1968 while (iwl_ini_txf_iter(fwrt, reg_data, size)) { 1969 size += fifo_hdr; 1970 if (!reg->fifos.hdr_only) 1971 size += iter->fifo_size; 1972 } 1973 1974 if (!size) 1975 return 0; 1976 1977 return size + sizeof(struct iwl_fw_ini_error_dump); 1978} 1979 1980static u32 iwl_dump_ini_rxf_get_size(struct iwl_fw_runtime *fwrt, 1981 struct iwl_dump_ini_region_data *reg_data) 1982{ 1983 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 1984 struct iwl_ini_rxf_data rx_data; 1985 u32 registers_num = iwl_tlv_array_len(reg_data->reg_tlv, reg, addrs); 1986 u32 size = sizeof(struct iwl_fw_ini_error_dump) + 1987 sizeof(struct iwl_fw_ini_error_dump_range) + 1988 registers_num * sizeof(struct iwl_fw_ini_error_dump_register); 1989 1990 if (reg->fifos.hdr_only) 1991 return size; 1992 1993#if defined(__FreeBSD__) 1994 rx_data.size = 0; 1995#endif 1996 iwl_ini_get_rxf_data(fwrt, reg_data, &rx_data); 1997 size += rx_data.size; 1998 1999 return size; 2000} 2001 2002static u32 2003iwl_dump_ini_err_table_get_size(struct iwl_fw_runtime *fwrt, 2004 struct iwl_dump_ini_region_data *reg_data) 2005{ 2006 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2007 u32 size = le32_to_cpu(reg->err_table.size); 2008 2009 if (size) 2010 size += sizeof(struct iwl_fw_ini_err_table_dump) + 2011 sizeof(struct iwl_fw_ini_error_dump_range); 2012 2013 return size; 2014} 2015 2016static u32 2017iwl_dump_ini_special_mem_get_size(struct iwl_fw_runtime *fwrt, 2018 struct iwl_dump_ini_region_data *reg_data) 2019{ 2020 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2021 u32 size = le32_to_cpu(reg->special_mem.size); 2022 2023 if (size) 2024 size += sizeof(struct iwl_fw_ini_special_device_memory) + 2025 sizeof(struct iwl_fw_ini_error_dump_range); 2026 2027 return size; 2028} 2029 2030static u32 2031iwl_dump_ini_fw_pkt_get_size(struct iwl_fw_runtime *fwrt, 2032 struct iwl_dump_ini_region_data *reg_data) 2033{ 2034 u32 size = 0; 2035 2036 if (!reg_data->dump_data->fw_pkt) 2037 return 0; 2038 2039 size += iwl_rx_packet_payload_len(reg_data->dump_data->fw_pkt); 2040 if (size) 2041 size += sizeof(struct iwl_fw_ini_error_dump) + 2042 sizeof(struct iwl_fw_ini_error_dump_range); 2043 2044 return size; 2045} 2046 2047static u32 2048iwl_dump_ini_imr_get_size(struct iwl_fw_runtime *fwrt, 2049 struct iwl_dump_ini_region_data *reg_data) 2050{ 2051 u32 ranges = 0; 2052 u32 imr_enable = fwrt->trans->dbg.imr_data.imr_enable; 2053 u32 imr_size = fwrt->trans->dbg.imr_data.imr_size; 2054 u32 sram_size = fwrt->trans->dbg.imr_data.sram_size; 2055 2056 if (imr_enable == 0 || imr_size == 0 || sram_size == 0) { 2057 IWL_DEBUG_INFO(fwrt, 2058 "WRT: Invalid imr data enable: %d, imr_size: %d, sram_size: %d\n", 2059 imr_enable, imr_size, sram_size); 2060 return 0; 2061 } 2062 ranges = iwl_dump_ini_imr_ranges(fwrt, reg_data); 2063 if (!ranges) { 2064 IWL_ERR(fwrt, "WRT: ranges :=%d\n", ranges); 2065 return 0; 2066 } 2067 imr_size += sizeof(struct iwl_fw_ini_error_dump) + 2068 ranges * sizeof(struct iwl_fw_ini_error_dump_range); 2069 return imr_size; 2070} 2071 2072/** 2073 * struct iwl_dump_ini_mem_ops - ini memory dump operations 2074 * @get_num_of_ranges: returns the number of memory ranges in the region. 2075 * @get_size: returns the total size of the region. 2076 * @fill_mem_hdr: fills region type specific headers and returns pointer to 2077 * the first range or NULL if failed to fill headers. 2078 * @fill_range: copies a given memory range into the dump. 2079 * Returns the size of the range or negative error value otherwise. 2080 */ 2081struct iwl_dump_ini_mem_ops { 2082 u32 (*get_num_of_ranges)(struct iwl_fw_runtime *fwrt, 2083 struct iwl_dump_ini_region_data *reg_data); 2084 u32 (*get_size)(struct iwl_fw_runtime *fwrt, 2085 struct iwl_dump_ini_region_data *reg_data); 2086 void *(*fill_mem_hdr)(struct iwl_fw_runtime *fwrt, 2087 struct iwl_dump_ini_region_data *reg_data, 2088 void *data, u32 data_len); 2089 int (*fill_range)(struct iwl_fw_runtime *fwrt, 2090 struct iwl_dump_ini_region_data *reg_data, 2091 void *range, u32 range_len, int idx); 2092}; 2093 2094/** 2095 * iwl_dump_ini_mem 2096 * 2097 * Creates a dump tlv and copy a memory region into it. 2098 * Returns the size of the current dump tlv or 0 if failed 2099 * 2100 * @fwrt: fw runtime struct 2101 * @list: list to add the dump tlv to 2102 * @reg_data: memory region 2103 * @ops: memory dump operations 2104 */ 2105static u32 iwl_dump_ini_mem(struct iwl_fw_runtime *fwrt, struct list_head *list, 2106 struct iwl_dump_ini_region_data *reg_data, 2107 const struct iwl_dump_ini_mem_ops *ops) 2108{ 2109 struct iwl_fw_ini_region_tlv *reg = (void *)reg_data->reg_tlv->data; 2110 struct iwl_fw_ini_dump_entry *entry; 2111 struct iwl_fw_ini_error_dump_data *tlv; 2112 struct iwl_fw_ini_error_dump_header *header; 2113 u32 type = reg->type; 2114 u32 id = le32_get_bits(reg->id, IWL_FW_INI_REGION_ID_MASK); 2115 u32 num_of_ranges, i, size; 2116 u8 *range; 2117 u32 free_size; 2118 u64 header_size; 2119 u32 dump_policy = IWL_FW_INI_DUMP_VERBOSE; 2120 2121 IWL_DEBUG_FW(fwrt, "WRT: Collecting region: dump type=%d, id=%d, type=%d\n", 2122 dump_policy, id, type); 2123 2124 if (le32_to_cpu(reg->hdr.version) >= 2) { 2125 u32 dp = le32_get_bits(reg->id, 2126 IWL_FW_INI_REGION_DUMP_POLICY_MASK); 2127 2128 if (dump_policy == IWL_FW_INI_DUMP_VERBOSE && 2129 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_NO_LIMIT)) { 2130 IWL_DEBUG_FW(fwrt, 2131 "WRT: no dump - type %d and policy mismatch=%d\n", 2132 dump_policy, dp); 2133 return 0; 2134 } else if (dump_policy == IWL_FW_INI_DUMP_MEDIUM && 2135 !(dp & IWL_FW_IWL_DEBUG_DUMP_POLICY_MAX_LIMIT_5MB)) { 2136 IWL_DEBUG_FW(fwrt, 2137 "WRT: no dump - type %d and policy mismatch=%d\n", 2138 dump_policy, dp); 2139 return 0; 2140 } else if (dump_policy == IWL_FW_INI_DUMP_BRIEF && 2141 !(dp & IWL_FW_INI_DEBUG_DUMP_POLICY_MAX_LIMIT_600KB)) { 2142 IWL_DEBUG_FW(fwrt, 2143 "WRT: no dump - type %d and policy mismatch=%d\n", 2144 dump_policy, dp); 2145 return 0; 2146 } 2147 } 2148 2149 if (!ops->get_num_of_ranges || !ops->get_size || !ops->fill_mem_hdr || 2150 !ops->fill_range) { 2151 IWL_DEBUG_FW(fwrt, "WRT: no ops for collecting data\n"); 2152 return 0; 2153 } 2154 2155 size = ops->get_size(fwrt, reg_data); 2156 2157 if (size < sizeof(*header)) { 2158 IWL_DEBUG_FW(fwrt, "WRT: size didn't include space for header\n"); 2159 return 0; 2160 } 2161 2162 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + size); 2163 if (!entry) 2164 return 0; 2165 2166 entry->size = sizeof(*tlv) + size; 2167 2168 tlv = (void *)entry->data; 2169 tlv->type = reg->type; 2170 tlv->sub_type = reg->sub_type; 2171 tlv->sub_type_ver = reg->sub_type_ver; 2172 tlv->reserved = reg->reserved; 2173 tlv->len = cpu_to_le32(size); 2174 2175 num_of_ranges = ops->get_num_of_ranges(fwrt, reg_data); 2176 2177 header = (void *)tlv->data; 2178 header->region_id = cpu_to_le32(id); 2179 header->num_of_ranges = cpu_to_le32(num_of_ranges); 2180 header->name_len = cpu_to_le32(IWL_FW_INI_MAX_NAME); 2181 memcpy(header->name, reg->name, IWL_FW_INI_MAX_NAME); 2182 2183 free_size = size; 2184 range = ops->fill_mem_hdr(fwrt, reg_data, header, free_size); 2185 if (!range) { 2186 IWL_ERR(fwrt, 2187 "WRT: Failed to fill region header: id=%d, type=%d\n", 2188 id, type); 2189 goto out_err; 2190 } 2191 2192 header_size = range - (u8 *)header; 2193 2194 if (WARN(header_size > free_size, 2195#if defined(__linux__) 2196 "header size %llu > free_size %d", 2197 header_size, free_size)) { 2198#elif defined(__FreeBSD__) 2199 "header size %ju > free_size %d", 2200 (uintmax_t)header_size, free_size)) { 2201#endif 2202 IWL_ERR(fwrt, 2203 "WRT: fill_mem_hdr used more than given free_size\n"); 2204 goto out_err; 2205 } 2206 2207 free_size -= header_size; 2208 2209 for (i = 0; i < num_of_ranges; i++) { 2210 int range_size = ops->fill_range(fwrt, reg_data, range, 2211 free_size, i); 2212 2213 if (range_size < 0) { 2214 IWL_ERR(fwrt, 2215 "WRT: Failed to dump region: id=%d, type=%d\n", 2216 id, type); 2217 goto out_err; 2218 } 2219 2220 if (WARN(range_size > free_size, "range_size %d > free_size %d", 2221 range_size, free_size)) { 2222 IWL_ERR(fwrt, 2223 "WRT: fill_raged used more than given free_size\n"); 2224 goto out_err; 2225 } 2226 2227 free_size -= range_size; 2228 range = range + range_size; 2229 } 2230 2231 list_add_tail(&entry->list, list); 2232 2233 return entry->size; 2234 2235out_err: 2236 vfree(entry); 2237 2238 return 0; 2239} 2240 2241static u32 iwl_dump_ini_info(struct iwl_fw_runtime *fwrt, 2242 struct iwl_fw_ini_trigger_tlv *trigger, 2243 struct list_head *list) 2244{ 2245 struct iwl_fw_ini_dump_entry *entry; 2246 struct iwl_fw_error_dump_data *tlv; 2247 struct iwl_fw_ini_dump_info *dump; 2248 struct iwl_dbg_tlv_node *node; 2249 struct iwl_fw_ini_dump_cfg_name *cfg_name; 2250 u32 size = sizeof(*tlv) + sizeof(*dump); 2251 u32 num_of_cfg_names = 0; 2252 u32 hw_type; 2253 2254 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2255 size += sizeof(*cfg_name); 2256 num_of_cfg_names++; 2257 } 2258 2259 entry = vzalloc(sizeof(*entry) + size); 2260 if (!entry) 2261 return 0; 2262 2263 entry->size = size; 2264 2265 tlv = (void *)entry->data; 2266 tlv->type = cpu_to_le32(IWL_INI_DUMP_INFO_TYPE); 2267 tlv->len = cpu_to_le32(size - sizeof(*tlv)); 2268 2269 dump = (void *)tlv->data; 2270 2271 dump->version = cpu_to_le32(IWL_INI_DUMP_VER); 2272 dump->time_point = trigger->time_point; 2273 dump->trigger_reason = trigger->trigger_reason; 2274 dump->external_cfg_state = 2275 cpu_to_le32(fwrt->trans->dbg.external_ini_cfg); 2276 2277 dump->ver_type = cpu_to_le32(fwrt->dump.fw_ver.type); 2278 dump->ver_subtype = cpu_to_le32(fwrt->dump.fw_ver.subtype); 2279 2280 dump->hw_step = cpu_to_le32(fwrt->trans->hw_rev_step); 2281 2282 /* 2283 * Several HWs all have type == 0x42, so we'll override this value 2284 * according to the detected HW 2285 */ 2286 hw_type = CSR_HW_REV_TYPE(fwrt->trans->hw_rev); 2287 if (hw_type == IWL_AX210_HW_TYPE) { 2288 u32 prph_val = iwl_read_umac_prph(fwrt->trans, WFPM_OTP_CFG1_ADDR); 2289 u32 is_jacket = !!(prph_val & WFPM_OTP_CFG1_IS_JACKET_BIT); 2290 u32 is_cdb = !!(prph_val & WFPM_OTP_CFG1_IS_CDB_BIT); 2291 u32 masked_bits = is_jacket | (is_cdb << 1); 2292 2293 /* 2294 * The HW type depends on certain bits in this case, so add 2295 * these bits to the HW type. We won't have collisions since we 2296 * add these bits after the highest possible bit in the mask. 2297 */ 2298 hw_type |= masked_bits << IWL_AX210_HW_TYPE_ADDITION_SHIFT; 2299 } 2300 dump->hw_type = cpu_to_le32(hw_type); 2301 2302 dump->rf_id_flavor = 2303 cpu_to_le32(CSR_HW_RFID_FLAVOR(fwrt->trans->hw_rf_id)); 2304 dump->rf_id_dash = cpu_to_le32(CSR_HW_RFID_DASH(fwrt->trans->hw_rf_id)); 2305 dump->rf_id_step = cpu_to_le32(CSR_HW_RFID_STEP(fwrt->trans->hw_rf_id)); 2306 dump->rf_id_type = cpu_to_le32(CSR_HW_RFID_TYPE(fwrt->trans->hw_rf_id)); 2307 2308 dump->lmac_major = cpu_to_le32(fwrt->dump.fw_ver.lmac_major); 2309 dump->lmac_minor = cpu_to_le32(fwrt->dump.fw_ver.lmac_minor); 2310 dump->umac_major = cpu_to_le32(fwrt->dump.fw_ver.umac_major); 2311 dump->umac_minor = cpu_to_le32(fwrt->dump.fw_ver.umac_minor); 2312 2313 dump->fw_mon_mode = cpu_to_le32(fwrt->trans->dbg.ini_dest); 2314 dump->regions_mask = trigger->regions_mask & 2315 ~cpu_to_le64(fwrt->trans->dbg.unsupported_region_msk); 2316 2317 dump->build_tag_len = cpu_to_le32(sizeof(dump->build_tag)); 2318 memcpy(dump->build_tag, fwrt->fw->human_readable, 2319 sizeof(dump->build_tag)); 2320 2321 cfg_name = dump->cfg_names; 2322 dump->num_of_cfg_names = cpu_to_le32(num_of_cfg_names); 2323 list_for_each_entry(node, &fwrt->trans->dbg.debug_info_tlv_list, list) { 2324 struct iwl_fw_ini_debug_info_tlv *debug_info = 2325 (void *)node->tlv.data; 2326 2327 cfg_name->image_type = debug_info->image_type; 2328 cfg_name->cfg_name_len = 2329 cpu_to_le32(IWL_FW_INI_MAX_CFG_NAME); 2330 memcpy(cfg_name->cfg_name, debug_info->debug_cfg_name, 2331 sizeof(cfg_name->cfg_name)); 2332 cfg_name++; 2333 } 2334 2335 /* add dump info TLV to the beginning of the list since it needs to be 2336 * the first TLV in the dump 2337 */ 2338 list_add(&entry->list, list); 2339 2340 return entry->size; 2341} 2342 2343static u32 iwl_dump_ini_file_name_info(struct iwl_fw_runtime *fwrt, 2344 struct list_head *list) 2345{ 2346 struct iwl_fw_ini_dump_entry *entry; 2347 struct iwl_dump_file_name_info *tlv; 2348 u32 len = strnlen(fwrt->trans->dbg.dump_file_name_ext, 2349 IWL_FW_INI_MAX_NAME); 2350 2351 if (!fwrt->trans->dbg.dump_file_name_ext_valid) 2352 return 0; 2353 2354 entry = vzalloc(sizeof(*entry) + sizeof(*tlv) + len); 2355 if (!entry) 2356 return 0; 2357 2358 entry->size = sizeof(*tlv) + len; 2359 2360 tlv = (void *)entry->data; 2361 tlv->type = cpu_to_le32(IWL_INI_DUMP_NAME_TYPE); 2362 tlv->len = cpu_to_le32(len); 2363 memcpy(tlv->data, fwrt->trans->dbg.dump_file_name_ext, len); 2364 2365 /* add the dump file name extension tlv to the list */ 2366 list_add_tail(&entry->list, list); 2367 2368 fwrt->trans->dbg.dump_file_name_ext_valid = false; 2369 2370 return entry->size; 2371} 2372 2373static const struct iwl_dump_ini_mem_ops iwl_dump_ini_region_ops[] = { 2374 [IWL_FW_INI_REGION_INVALID] = {}, 2375 [IWL_FW_INI_REGION_INTERNAL_BUFFER] = { 2376 .get_num_of_ranges = iwl_dump_ini_single_range, 2377 .get_size = iwl_dump_ini_mon_smem_get_size, 2378 .fill_mem_hdr = iwl_dump_ini_mon_smem_fill_header, 2379 .fill_range = iwl_dump_ini_mon_smem_iter, 2380 }, 2381 [IWL_FW_INI_REGION_DRAM_BUFFER] = { 2382 .get_num_of_ranges = iwl_dump_ini_mon_dram_ranges, 2383 .get_size = iwl_dump_ini_mon_dram_get_size, 2384 .fill_mem_hdr = iwl_dump_ini_mon_dram_fill_header, 2385 .fill_range = iwl_dump_ini_mon_dram_iter, 2386 }, 2387 [IWL_FW_INI_REGION_TXF] = { 2388 .get_num_of_ranges = iwl_dump_ini_txf_ranges, 2389 .get_size = iwl_dump_ini_txf_get_size, 2390 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2391 .fill_range = iwl_dump_ini_txf_iter, 2392 }, 2393 [IWL_FW_INI_REGION_RXF] = { 2394 .get_num_of_ranges = iwl_dump_ini_single_range, 2395 .get_size = iwl_dump_ini_rxf_get_size, 2396 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2397 .fill_range = iwl_dump_ini_rxf_iter, 2398 }, 2399 [IWL_FW_INI_REGION_LMAC_ERROR_TABLE] = { 2400 .get_num_of_ranges = iwl_dump_ini_single_range, 2401 .get_size = iwl_dump_ini_err_table_get_size, 2402 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2403 .fill_range = iwl_dump_ini_err_table_iter, 2404 }, 2405 [IWL_FW_INI_REGION_UMAC_ERROR_TABLE] = { 2406 .get_num_of_ranges = iwl_dump_ini_single_range, 2407 .get_size = iwl_dump_ini_err_table_get_size, 2408 .fill_mem_hdr = iwl_dump_ini_err_table_fill_header, 2409 .fill_range = iwl_dump_ini_err_table_iter, 2410 }, 2411 [IWL_FW_INI_REGION_RSP_OR_NOTIF] = { 2412 .get_num_of_ranges = iwl_dump_ini_single_range, 2413 .get_size = iwl_dump_ini_fw_pkt_get_size, 2414 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2415 .fill_range = iwl_dump_ini_fw_pkt_iter, 2416 }, 2417 [IWL_FW_INI_REGION_DEVICE_MEMORY] = { 2418 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2419 .get_size = iwl_dump_ini_mem_get_size, 2420 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2421 .fill_range = iwl_dump_ini_dev_mem_iter, 2422 }, 2423 [IWL_FW_INI_REGION_PERIPHERY_MAC] = { 2424 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2425 .get_size = iwl_dump_ini_mem_get_size, 2426 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2427 .fill_range = iwl_dump_ini_prph_mac_iter, 2428 }, 2429 [IWL_FW_INI_REGION_PERIPHERY_PHY] = { 2430 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2431 .get_size = iwl_dump_ini_mem_get_size, 2432 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2433 .fill_range = iwl_dump_ini_prph_phy_iter, 2434 }, 2435 [IWL_FW_INI_REGION_PERIPHERY_AUX] = {}, 2436 [IWL_FW_INI_REGION_PAGING] = { 2437 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2438 .get_num_of_ranges = iwl_dump_ini_paging_ranges, 2439 .get_size = iwl_dump_ini_paging_get_size, 2440 .fill_range = iwl_dump_ini_paging_iter, 2441 }, 2442 [IWL_FW_INI_REGION_CSR] = { 2443 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2444 .get_size = iwl_dump_ini_mem_get_size, 2445 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2446 .fill_range = iwl_dump_ini_csr_iter, 2447 }, 2448 [IWL_FW_INI_REGION_DRAM_IMR] = { 2449 .get_num_of_ranges = iwl_dump_ini_imr_ranges, 2450 .get_size = iwl_dump_ini_imr_get_size, 2451 .fill_mem_hdr = iwl_dump_ini_imr_fill_header, 2452 .fill_range = iwl_dump_ini_imr_iter, 2453 }, 2454 [IWL_FW_INI_REGION_PCI_IOSF_CONFIG] = { 2455 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2456 .get_size = iwl_dump_ini_mem_get_size, 2457 .fill_mem_hdr = iwl_dump_ini_mem_fill_header, 2458 .fill_range = iwl_dump_ini_config_iter, 2459 }, 2460 [IWL_FW_INI_REGION_SPECIAL_DEVICE_MEMORY] = { 2461 .get_num_of_ranges = iwl_dump_ini_single_range, 2462 .get_size = iwl_dump_ini_special_mem_get_size, 2463 .fill_mem_hdr = iwl_dump_ini_special_mem_fill_header, 2464 .fill_range = iwl_dump_ini_special_mem_iter, 2465 }, 2466 [IWL_FW_INI_REGION_DBGI_SRAM] = { 2467 .get_num_of_ranges = iwl_dump_ini_mem_ranges, 2468 .get_size = iwl_dump_ini_mon_dbgi_get_size, 2469 .fill_mem_hdr = iwl_dump_ini_mon_dbgi_fill_header, 2470 .fill_range = iwl_dump_ini_dbgi_sram_iter, 2471 }, 2472}; 2473 2474static u32 iwl_dump_ini_trigger(struct iwl_fw_runtime *fwrt, 2475 struct iwl_fwrt_dump_data *dump_data, 2476 struct list_head *list) 2477{ 2478 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2479 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trigger->time_point); 2480 struct iwl_dump_ini_region_data reg_data = { 2481 .dump_data = dump_data, 2482 }; 2483 struct iwl_dump_ini_region_data imr_reg_data = { 2484 .dump_data = dump_data, 2485 }; 2486 int i; 2487 u32 size = 0; 2488 u64 regions_mask = le64_to_cpu(trigger->regions_mask) & 2489 ~(fwrt->trans->dbg.unsupported_region_msk); 2490 2491 BUILD_BUG_ON(sizeof(trigger->regions_mask) != sizeof(regions_mask)); 2492 BUILD_BUG_ON((sizeof(trigger->regions_mask) * BITS_PER_BYTE) < 2493 ARRAY_SIZE(fwrt->trans->dbg.active_regions)); 2494 2495 for (i = 0; i < ARRAY_SIZE(fwrt->trans->dbg.active_regions); i++) { 2496 u32 reg_type; 2497 struct iwl_fw_ini_region_tlv *reg; 2498 2499 if (!(BIT_ULL(i) & regions_mask)) 2500 continue; 2501 2502 reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2503 if (!reg_data.reg_tlv) { 2504 IWL_WARN(fwrt, 2505 "WRT: Unassigned region id %d, skipping\n", i); 2506 continue; 2507 } 2508 2509 reg = (void *)reg_data.reg_tlv->data; 2510 reg_type = reg->type; 2511 if (reg_type >= ARRAY_SIZE(iwl_dump_ini_region_ops)) 2512 continue; 2513 2514 if (reg_type == IWL_FW_INI_REGION_PERIPHERY_PHY && 2515 tp_id != IWL_FW_INI_TIME_POINT_FW_ASSERT) { 2516 IWL_WARN(fwrt, 2517 "WRT: trying to collect phy prph at time point: %d, skipping\n", 2518 tp_id); 2519 continue; 2520 } 2521 /* 2522 * DRAM_IMR can be collected only for FW/HW error timepoint 2523 * when fw is not alive. In addition, it must be collected 2524 * lastly as it overwrites SRAM that can possibly contain 2525 * debug data which also need to be collected. 2526 */ 2527 if (reg_type == IWL_FW_INI_REGION_DRAM_IMR) { 2528 if (tp_id == IWL_FW_INI_TIME_POINT_FW_ASSERT || 2529 tp_id == IWL_FW_INI_TIME_POINT_FW_HW_ERROR) 2530 imr_reg_data.reg_tlv = fwrt->trans->dbg.active_regions[i]; 2531 else 2532 IWL_INFO(fwrt, 2533 "WRT: trying to collect DRAM_IMR at time point: %d, skipping\n", 2534 tp_id); 2535 /* continue to next region */ 2536 continue; 2537 } 2538 2539 2540 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2541 &iwl_dump_ini_region_ops[reg_type]); 2542 } 2543 /* collect DRAM_IMR region in the last */ 2544 if (imr_reg_data.reg_tlv) 2545 size += iwl_dump_ini_mem(fwrt, list, ®_data, 2546 &iwl_dump_ini_region_ops[IWL_FW_INI_REGION_DRAM_IMR]); 2547 2548 if (size) { 2549 size += iwl_dump_ini_file_name_info(fwrt, list); 2550 size += iwl_dump_ini_info(fwrt, trigger, list); 2551 } 2552 2553 return size; 2554} 2555 2556static bool iwl_fw_ini_trigger_on(struct iwl_fw_runtime *fwrt, 2557 struct iwl_fw_ini_trigger_tlv *trig) 2558{ 2559 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 2560 u32 usec = le32_to_cpu(trig->ignore_consec); 2561 2562 if (!iwl_trans_dbg_ini_valid(fwrt->trans) || 2563 tp_id == IWL_FW_INI_TIME_POINT_INVALID || 2564 tp_id >= IWL_FW_INI_TIME_POINT_NUM || 2565 iwl_fw_dbg_no_trig_window(fwrt, tp_id, usec)) 2566 return false; 2567 2568 return true; 2569} 2570 2571static u32 iwl_dump_ini_file_gen(struct iwl_fw_runtime *fwrt, 2572 struct iwl_fwrt_dump_data *dump_data, 2573 struct list_head *list) 2574{ 2575 struct iwl_fw_ini_trigger_tlv *trigger = dump_data->trig; 2576 struct iwl_fw_ini_dump_entry *entry; 2577 struct iwl_fw_ini_dump_file_hdr *hdr; 2578 u32 size; 2579 2580 if (!trigger || !iwl_fw_ini_trigger_on(fwrt, trigger) || 2581 !le64_to_cpu(trigger->regions_mask)) 2582 return 0; 2583 2584 entry = vzalloc(sizeof(*entry) + sizeof(*hdr)); 2585 if (!entry) 2586 return 0; 2587 2588 entry->size = sizeof(*hdr); 2589 2590 size = iwl_dump_ini_trigger(fwrt, dump_data, list); 2591 if (!size) { 2592 vfree(entry); 2593 return 0; 2594 } 2595 2596 hdr = (void *)entry->data; 2597 hdr->barker = cpu_to_le32(IWL_FW_INI_ERROR_DUMP_BARKER); 2598 hdr->file_len = cpu_to_le32(size + entry->size); 2599 2600 list_add(&entry->list, list); 2601 2602 return le32_to_cpu(hdr->file_len); 2603} 2604 2605static inline void iwl_fw_free_dump_desc(struct iwl_fw_runtime *fwrt, 2606 const struct iwl_fw_dump_desc *desc) 2607{ 2608 if (desc && desc != &iwl_dump_desc_assert) 2609 kfree(desc); 2610 2611 fwrt->dump.lmac_err_id[0] = 0; 2612 if (fwrt->smem_cfg.num_lmacs > 1) 2613 fwrt->dump.lmac_err_id[1] = 0; 2614 fwrt->dump.umac_err_id = 0; 2615} 2616 2617static void iwl_fw_error_dump(struct iwl_fw_runtime *fwrt, 2618 struct iwl_fwrt_dump_data *dump_data) 2619{ 2620 struct iwl_fw_dump_ptrs fw_error_dump = {}; 2621 struct iwl_fw_error_dump_file *dump_file; 2622 struct scatterlist *sg_dump_data; 2623 u32 file_len; 2624 u32 dump_mask = fwrt->fw->dbg.dump_mask; 2625 2626 dump_file = iwl_fw_error_dump_file(fwrt, &fw_error_dump, dump_data); 2627 if (!dump_file) 2628 return; 2629 2630 if (dump_data->monitor_only) 2631 dump_mask &= BIT(IWL_FW_ERROR_DUMP_FW_MONITOR); 2632 2633 fw_error_dump.trans_ptr = iwl_trans_dump_data(fwrt->trans, dump_mask, 2634 fwrt->sanitize_ops, 2635 fwrt->sanitize_ctx); 2636 file_len = le32_to_cpu(dump_file->file_len); 2637 fw_error_dump.fwrt_len = file_len; 2638 2639 if (fw_error_dump.trans_ptr) { 2640 file_len += fw_error_dump.trans_ptr->len; 2641 dump_file->file_len = cpu_to_le32(file_len); 2642 } 2643 2644 sg_dump_data = alloc_sgtable(file_len); 2645 if (sg_dump_data) { 2646 sg_pcopy_from_buffer(sg_dump_data, 2647 sg_nents(sg_dump_data), 2648 fw_error_dump.fwrt_ptr, 2649 fw_error_dump.fwrt_len, 0); 2650 if (fw_error_dump.trans_ptr) 2651 sg_pcopy_from_buffer(sg_dump_data, 2652 sg_nents(sg_dump_data), 2653 fw_error_dump.trans_ptr->data, 2654 fw_error_dump.trans_ptr->len, 2655 fw_error_dump.fwrt_len); 2656 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2657 GFP_KERNEL); 2658 } 2659 vfree(fw_error_dump.fwrt_ptr); 2660 vfree(fw_error_dump.trans_ptr); 2661} 2662 2663static void iwl_dump_ini_list_free(struct list_head *list) 2664{ 2665 while (!list_empty(list)) { 2666 struct iwl_fw_ini_dump_entry *entry = 2667 list_entry(list->next, typeof(*entry), list); 2668 2669 list_del(&entry->list); 2670 vfree(entry); 2671 } 2672} 2673 2674static void iwl_fw_error_dump_data_free(struct iwl_fwrt_dump_data *dump_data) 2675{ 2676 dump_data->trig = NULL; 2677 kfree(dump_data->fw_pkt); 2678 dump_data->fw_pkt = NULL; 2679} 2680 2681static void iwl_fw_error_ini_dump(struct iwl_fw_runtime *fwrt, 2682 struct iwl_fwrt_dump_data *dump_data) 2683{ 2684#if defined(__linux__) 2685 LIST_HEAD(dump_list); 2686#elif defined(__FreeBSD__) 2687 LINUX_LIST_HEAD(dump_list); 2688#endif 2689 struct scatterlist *sg_dump_data; 2690 u32 file_len = iwl_dump_ini_file_gen(fwrt, dump_data, &dump_list); 2691 2692 if (!file_len) 2693 return; 2694 2695 sg_dump_data = alloc_sgtable(file_len); 2696 if (sg_dump_data) { 2697 struct iwl_fw_ini_dump_entry *entry; 2698 int sg_entries = sg_nents(sg_dump_data); 2699 u32 offs = 0; 2700 2701 list_for_each_entry(entry, &dump_list, list) { 2702 sg_pcopy_from_buffer(sg_dump_data, sg_entries, 2703 entry->data, entry->size, offs); 2704 offs += entry->size; 2705 } 2706 dev_coredumpsg(fwrt->trans->dev, sg_dump_data, file_len, 2707 GFP_KERNEL); 2708 } 2709 iwl_dump_ini_list_free(&dump_list); 2710} 2711 2712const struct iwl_fw_dump_desc iwl_dump_desc_assert = { 2713 .trig_desc = { 2714 .type = cpu_to_le32(FW_DBG_TRIGGER_FW_ASSERT), 2715 }, 2716}; 2717IWL_EXPORT_SYMBOL(iwl_dump_desc_assert); 2718 2719int iwl_fw_dbg_collect_desc(struct iwl_fw_runtime *fwrt, 2720 const struct iwl_fw_dump_desc *desc, 2721 bool monitor_only, 2722 unsigned int delay) 2723{ 2724 struct iwl_fwrt_wk_data *wk_data; 2725 unsigned long idx; 2726 2727 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2728 iwl_fw_free_dump_desc(fwrt, desc); 2729 return 0; 2730 } 2731 2732 /* 2733 * Check there is an available worker. 2734 * ffz return value is undefined if no zero exists, 2735 * so check against ~0UL first. 2736 */ 2737 if (fwrt->dump.active_wks == ~0UL) 2738 return -EBUSY; 2739 2740 idx = ffz(fwrt->dump.active_wks); 2741 2742 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 2743 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 2744 return -EBUSY; 2745 2746 wk_data = &fwrt->dump.wks[idx]; 2747 2748 if (WARN_ON(wk_data->dump_data.desc)) 2749 iwl_fw_free_dump_desc(fwrt, wk_data->dump_data.desc); 2750 2751 wk_data->dump_data.desc = desc; 2752 wk_data->dump_data.monitor_only = monitor_only; 2753 2754 IWL_WARN(fwrt, "Collecting data: trigger %d fired.\n", 2755 le32_to_cpu(desc->trig_desc.type)); 2756 2757 schedule_delayed_work(&wk_data->wk, usecs_to_jiffies(delay)); 2758 2759 return 0; 2760} 2761IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_desc); 2762 2763int iwl_fw_dbg_error_collect(struct iwl_fw_runtime *fwrt, 2764 enum iwl_fw_dbg_trigger trig_type) 2765{ 2766 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) 2767 return -EIO; 2768 2769 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 2770 if (trig_type != FW_DBG_TRIGGER_ALIVE_TIMEOUT && 2771 trig_type != FW_DBG_TRIGGER_DRIVER) 2772 return -EIO; 2773 2774 iwl_dbg_tlv_time_point(fwrt, 2775 IWL_FW_INI_TIME_POINT_HOST_ALIVE_TIMEOUT, 2776 NULL); 2777 } else { 2778 struct iwl_fw_dump_desc *iwl_dump_error_desc; 2779 int ret; 2780 2781 iwl_dump_error_desc = 2782 kmalloc(sizeof(*iwl_dump_error_desc), GFP_KERNEL); 2783 2784 if (!iwl_dump_error_desc) 2785 return -ENOMEM; 2786 2787 iwl_dump_error_desc->trig_desc.type = cpu_to_le32(trig_type); 2788 iwl_dump_error_desc->len = 0; 2789 2790 ret = iwl_fw_dbg_collect_desc(fwrt, iwl_dump_error_desc, 2791 false, 0); 2792 if (ret) { 2793 kfree(iwl_dump_error_desc); 2794 return ret; 2795 } 2796 } 2797 2798 iwl_trans_sync_nmi(fwrt->trans); 2799 2800 return 0; 2801} 2802IWL_EXPORT_SYMBOL(iwl_fw_dbg_error_collect); 2803 2804int iwl_fw_dbg_collect(struct iwl_fw_runtime *fwrt, 2805 enum iwl_fw_dbg_trigger trig, 2806 const char *str, size_t len, 2807 struct iwl_fw_dbg_trigger_tlv *trigger) 2808{ 2809 struct iwl_fw_dump_desc *desc; 2810 unsigned int delay = 0; 2811 bool monitor_only = false; 2812 2813 if (trigger) { 2814 u16 occurrences = le16_to_cpu(trigger->occurrences) - 1; 2815 2816 if (!le16_to_cpu(trigger->occurrences)) 2817 return 0; 2818 2819 if (trigger->flags & IWL_FW_DBG_FORCE_RESTART) { 2820 IWL_WARN(fwrt, "Force restart: trigger %d fired.\n", 2821 trig); 2822 iwl_force_nmi(fwrt->trans); 2823 return 0; 2824 } 2825 2826 trigger->occurrences = cpu_to_le16(occurrences); 2827 monitor_only = trigger->mode & IWL_FW_DBG_TRIGGER_MONITOR_ONLY; 2828 2829 /* convert msec to usec */ 2830 delay = le32_to_cpu(trigger->stop_delay) * USEC_PER_MSEC; 2831 } 2832 2833 desc = kzalloc(struct_size(desc, trig_desc.data, len), GFP_ATOMIC); 2834 if (!desc) 2835 return -ENOMEM; 2836 2837 2838 desc->len = len; 2839 desc->trig_desc.type = cpu_to_le32(trig); 2840 memcpy(desc->trig_desc.data, str, len); 2841 2842 return iwl_fw_dbg_collect_desc(fwrt, desc, monitor_only, delay); 2843} 2844IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect); 2845 2846int iwl_fw_dbg_collect_trig(struct iwl_fw_runtime *fwrt, 2847 struct iwl_fw_dbg_trigger_tlv *trigger, 2848 const char *fmt, ...) 2849{ 2850 int ret, len = 0; 2851 char buf[64]; 2852 2853 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2854 return 0; 2855 2856 if (fmt) { 2857 va_list ap; 2858 2859 buf[sizeof(buf) - 1] = '\0'; 2860 2861 va_start(ap, fmt); 2862 vsnprintf(buf, sizeof(buf), fmt, ap); 2863 va_end(ap); 2864 2865 /* check for truncation */ 2866 if (WARN_ON_ONCE(buf[sizeof(buf) - 1])) 2867 buf[sizeof(buf) - 1] = '\0'; 2868 2869 len = strlen(buf) + 1; 2870 } 2871 2872 ret = iwl_fw_dbg_collect(fwrt, le32_to_cpu(trigger->id), buf, len, 2873 trigger); 2874 2875 if (ret) 2876 return ret; 2877 2878 return 0; 2879} 2880IWL_EXPORT_SYMBOL(iwl_fw_dbg_collect_trig); 2881 2882int iwl_fw_start_dbg_conf(struct iwl_fw_runtime *fwrt, u8 conf_id) 2883{ 2884 u8 *ptr; 2885 int ret; 2886 int i; 2887 2888 if (WARN_ONCE(conf_id >= ARRAY_SIZE(fwrt->fw->dbg.conf_tlv), 2889 "Invalid configuration %d\n", conf_id)) 2890 return -EINVAL; 2891 2892 /* EARLY START - firmware's configuration is hard coded */ 2893 if ((!fwrt->fw->dbg.conf_tlv[conf_id] || 2894 !fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds) && 2895 conf_id == FW_DBG_START_FROM_ALIVE) 2896 return 0; 2897 2898 if (!fwrt->fw->dbg.conf_tlv[conf_id]) 2899 return -EINVAL; 2900 2901 if (fwrt->dump.conf != FW_DBG_INVALID) 2902 IWL_INFO(fwrt, "FW already configured (%d) - re-configuring\n", 2903 fwrt->dump.conf); 2904 2905 /* Send all HCMDs for configuring the FW debug */ 2906 ptr = (void *)&fwrt->fw->dbg.conf_tlv[conf_id]->hcmd; 2907 for (i = 0; i < fwrt->fw->dbg.conf_tlv[conf_id]->num_of_hcmds; i++) { 2908 struct iwl_fw_dbg_conf_hcmd *cmd = (void *)ptr; 2909 struct iwl_host_cmd hcmd = { 2910 .id = cmd->id, 2911 .len = { le16_to_cpu(cmd->len), }, 2912 .data = { cmd->data, }, 2913 }; 2914 2915 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 2916 if (ret) 2917 return ret; 2918 2919 ptr += sizeof(*cmd); 2920 ptr += le16_to_cpu(cmd->len); 2921 } 2922 2923 fwrt->dump.conf = conf_id; 2924 2925 return 0; 2926} 2927IWL_EXPORT_SYMBOL(iwl_fw_start_dbg_conf); 2928 2929void iwl_send_dbg_dump_complete_cmd(struct iwl_fw_runtime *fwrt, 2930 u32 timepoint, 2931 u32 timepoint_data) 2932{ 2933 struct iwl_dbg_dump_complete_cmd hcmd_data; 2934 struct iwl_host_cmd hcmd = { 2935 .id = WIDE_ID(DEBUG_GROUP, FW_DUMP_COMPLETE_CMD), 2936 .data[0] = &hcmd_data, 2937 .len[0] = sizeof(hcmd_data), 2938 }; 2939 2940 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 2941 return; 2942 2943 if (fw_has_capa(&fwrt->fw->ucode_capa, 2944 IWL_UCODE_TLV_CAPA_DUMP_COMPLETE_SUPPORT)) { 2945 hcmd_data.tp = cpu_to_le32(timepoint); 2946 hcmd_data.tp_data = cpu_to_le32(timepoint_data); 2947 iwl_trans_send_cmd(fwrt->trans, &hcmd); 2948 } 2949} 2950 2951/* this function assumes dump_start was called beforehand and dump_end will be 2952 * called afterwards 2953 */ 2954static void iwl_fw_dbg_collect_sync(struct iwl_fw_runtime *fwrt, u8 wk_idx) 2955{ 2956 struct iwl_fw_dbg_params params = {0}; 2957 struct iwl_fwrt_dump_data *dump_data = 2958 &fwrt->dump.wks[wk_idx].dump_data; 2959 u32 policy; 2960 u32 time_point; 2961 if (!test_bit(wk_idx, &fwrt->dump.active_wks)) 2962 return; 2963 2964 if (!dump_data->trig) { 2965 IWL_ERR(fwrt, "dump trigger data is not set\n"); 2966 goto out; 2967 } 2968 2969 if (!test_bit(STATUS_DEVICE_ENABLED, &fwrt->trans->status)) { 2970 IWL_ERR(fwrt, "Device is not enabled - cannot dump error\n"); 2971 goto out; 2972 } 2973 2974 /* there's no point in fw dump if the bus is dead */ 2975 if (test_bit(STATUS_TRANS_DEAD, &fwrt->trans->status)) { 2976 IWL_ERR(fwrt, "Skip fw error dump since bus is dead\n"); 2977 goto out; 2978 } 2979 2980 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, true); 2981 2982 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection start\n"); 2983 if (iwl_trans_dbg_ini_valid(fwrt->trans)) 2984 iwl_fw_error_ini_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2985 else 2986 iwl_fw_error_dump(fwrt, &fwrt->dump.wks[wk_idx].dump_data); 2987 IWL_DEBUG_FW_INFO(fwrt, "WRT: Data collection done\n"); 2988 2989 iwl_fw_dbg_stop_restart_recording(fwrt, ¶ms, false); 2990 2991 policy = le32_to_cpu(dump_data->trig->apply_policy); 2992 time_point = le32_to_cpu(dump_data->trig->time_point); 2993 2994 if (policy & IWL_FW_INI_APPLY_POLICY_DUMP_COMPLETE_CMD) { 2995 IWL_DEBUG_FW_INFO(fwrt, "WRT: sending dump complete\n"); 2996 iwl_send_dbg_dump_complete_cmd(fwrt, time_point, 0); 2997 } 2998 if (fwrt->trans->dbg.last_tp_resetfw == IWL_FW_INI_RESET_FW_MODE_STOP_FW_ONLY) 2999 iwl_force_nmi(fwrt->trans); 3000 3001out: 3002 if (iwl_trans_dbg_ini_valid(fwrt->trans)) { 3003 iwl_fw_error_dump_data_free(dump_data); 3004 } else { 3005 iwl_fw_free_dump_desc(fwrt, dump_data->desc); 3006 dump_data->desc = NULL; 3007 } 3008 3009 clear_bit(wk_idx, &fwrt->dump.active_wks); 3010} 3011 3012int iwl_fw_dbg_ini_collect(struct iwl_fw_runtime *fwrt, 3013 struct iwl_fwrt_dump_data *dump_data, 3014 bool sync) 3015{ 3016 struct iwl_fw_ini_trigger_tlv *trig = dump_data->trig; 3017 enum iwl_fw_ini_time_point tp_id = le32_to_cpu(trig->time_point); 3018 u32 occur, delay; 3019 unsigned long idx; 3020 3021 if (!iwl_fw_ini_trigger_on(fwrt, trig)) { 3022 IWL_WARN(fwrt, "WRT: Trigger %d is not active, aborting dump\n", 3023 tp_id); 3024 return -EINVAL; 3025 } 3026 3027 delay = le32_to_cpu(trig->dump_delay); 3028 occur = le32_to_cpu(trig->occurrences); 3029 if (!occur) 3030 return 0; 3031 3032 trig->occurrences = cpu_to_le32(--occur); 3033 3034 /* Check there is an available worker. 3035 * ffz return value is undefined if no zero exists, 3036 * so check against ~0UL first. 3037 */ 3038 if (fwrt->dump.active_wks == ~0UL) 3039 return -EBUSY; 3040 3041 idx = ffz(fwrt->dump.active_wks); 3042 3043 if (idx >= IWL_FW_RUNTIME_DUMP_WK_NUM || 3044 test_and_set_bit(fwrt->dump.wks[idx].idx, &fwrt->dump.active_wks)) 3045 return -EBUSY; 3046 3047 fwrt->dump.wks[idx].dump_data = *dump_data; 3048 3049 if (sync) 3050 delay = 0; 3051 3052 IWL_WARN(fwrt, 3053 "WRT: Collecting data: ini trigger %d fired (delay=%dms).\n", 3054 tp_id, (u32)(delay / USEC_PER_MSEC)); 3055 3056 if (sync) 3057 iwl_fw_dbg_collect_sync(fwrt, idx); 3058 else 3059 schedule_delayed_work(&fwrt->dump.wks[idx].wk, usecs_to_jiffies(delay)); 3060 3061 return 0; 3062} 3063 3064void iwl_fw_error_dump_wk(struct work_struct *work) 3065{ 3066 struct iwl_fwrt_wk_data *wks = 3067 container_of(work, typeof(*wks), wk.work); 3068 struct iwl_fw_runtime *fwrt = 3069 container_of(wks, typeof(*fwrt), dump.wks[wks->idx]); 3070 3071 /* assumes the op mode mutex is locked in dump_start since 3072 * iwl_fw_dbg_collect_sync can't run in parallel 3073 */ 3074 if (fwrt->ops && fwrt->ops->dump_start) 3075 fwrt->ops->dump_start(fwrt->ops_ctx); 3076 3077 iwl_fw_dbg_collect_sync(fwrt, wks->idx); 3078 3079 if (fwrt->ops && fwrt->ops->dump_end) 3080 fwrt->ops->dump_end(fwrt->ops_ctx); 3081} 3082 3083void iwl_fw_dbg_read_d3_debug_data(struct iwl_fw_runtime *fwrt) 3084{ 3085 const struct iwl_cfg *cfg = fwrt->trans->cfg; 3086 3087 if (!iwl_fw_dbg_is_d3_debug_enabled(fwrt)) 3088 return; 3089 3090 if (!fwrt->dump.d3_debug_data) { 3091 fwrt->dump.d3_debug_data = kmalloc(cfg->d3_debug_data_length, 3092 GFP_KERNEL); 3093 if (!fwrt->dump.d3_debug_data) { 3094 IWL_ERR(fwrt, 3095 "failed to allocate memory for D3 debug data\n"); 3096 return; 3097 } 3098 } 3099 3100 /* if the buffer holds previous debug data it is overwritten */ 3101 iwl_trans_read_mem_bytes(fwrt->trans, cfg->d3_debug_data_base_addr, 3102 fwrt->dump.d3_debug_data, 3103 cfg->d3_debug_data_length); 3104 3105 if (fwrt->sanitize_ops && fwrt->sanitize_ops->frob_mem) 3106 fwrt->sanitize_ops->frob_mem(fwrt->sanitize_ctx, 3107 cfg->d3_debug_data_base_addr, 3108 fwrt->dump.d3_debug_data, 3109 cfg->d3_debug_data_length); 3110} 3111IWL_EXPORT_SYMBOL(iwl_fw_dbg_read_d3_debug_data); 3112 3113void iwl_fw_dbg_stop_sync(struct iwl_fw_runtime *fwrt) 3114{ 3115 int i; 3116 3117 iwl_dbg_tlv_del_timers(fwrt->trans); 3118 for (i = 0; i < IWL_FW_RUNTIME_DUMP_WK_NUM; i++) 3119 iwl_fw_dbg_collect_sync(fwrt, i); 3120 3121 iwl_fw_dbg_stop_restart_recording(fwrt, NULL, true); 3122} 3123IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_sync); 3124 3125static int iwl_fw_dbg_suspend_resume_hcmd(struct iwl_trans *trans, bool suspend) 3126{ 3127 struct iwl_dbg_suspend_resume_cmd cmd = { 3128 .operation = suspend ? 3129 cpu_to_le32(DBGC_SUSPEND_CMD) : 3130 cpu_to_le32(DBGC_RESUME_CMD), 3131 }; 3132 struct iwl_host_cmd hcmd = { 3133 .id = WIDE_ID(DEBUG_GROUP, DBGC_SUSPEND_RESUME), 3134 .data[0] = &cmd, 3135 .len[0] = sizeof(cmd), 3136 }; 3137 3138 return iwl_trans_send_cmd(trans, &hcmd); 3139} 3140 3141static void iwl_fw_dbg_stop_recording(struct iwl_trans *trans, 3142 struct iwl_fw_dbg_params *params) 3143{ 3144 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3145 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3146 return; 3147 } 3148 3149 if (params) { 3150 params->in_sample = iwl_read_umac_prph(trans, DBGC_IN_SAMPLE); 3151 params->out_ctrl = iwl_read_umac_prph(trans, DBGC_OUT_CTRL); 3152 } 3153 3154 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, 0); 3155 /* wait for the DBGC to finish writing the internal buffer to DRAM to 3156 * avoid halting the HW while writing 3157 */ 3158 usleep_range(700, 1000); 3159 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, 0); 3160} 3161 3162static int iwl_fw_dbg_restart_recording(struct iwl_trans *trans, 3163 struct iwl_fw_dbg_params *params) 3164{ 3165 if (!params) 3166 return -EIO; 3167 3168 if (trans->trans_cfg->device_family == IWL_DEVICE_FAMILY_7000) { 3169 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x100); 3170 iwl_clear_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3171 iwl_set_bits_prph(trans, MON_BUFF_SAMPLE_CTL, 0x1); 3172 } else { 3173 iwl_write_umac_prph(trans, DBGC_IN_SAMPLE, params->in_sample); 3174 iwl_write_umac_prph(trans, DBGC_OUT_CTRL, params->out_ctrl); 3175 } 3176 3177 return 0; 3178} 3179 3180int iwl_fw_send_timestamp_marker_cmd(struct iwl_fw_runtime *fwrt) 3181{ 3182 struct iwl_mvm_marker marker = { 3183 .dw_len = sizeof(struct iwl_mvm_marker) / 4, 3184 .marker_id = MARKER_ID_SYNC_CLOCK, 3185 }; 3186 struct iwl_host_cmd hcmd = { 3187 .flags = CMD_ASYNC, 3188 .id = WIDE_ID(LONG_GROUP, MARKER_CMD), 3189 .dataflags = {}, 3190 }; 3191 struct iwl_mvm_marker_rsp *resp; 3192 int cmd_ver = iwl_fw_lookup_cmd_ver(fwrt->fw, 3193 WIDE_ID(LONG_GROUP, MARKER_CMD), 3194 IWL_FW_CMD_VER_UNKNOWN); 3195 int ret; 3196 3197 if (cmd_ver == 1) { 3198 /* the real timestamp is taken from the ftrace clock 3199 * this is for finding the match between fw and kernel logs 3200 */ 3201 marker.timestamp = cpu_to_le64(fwrt->timestamp.seq++); 3202 } else if (cmd_ver == 2) { 3203 marker.timestamp = cpu_to_le64(ktime_get_boottime_ns()); 3204 } else { 3205 IWL_DEBUG_INFO(fwrt, 3206 "Invalid version of Marker CMD. Ver = %d\n", 3207 cmd_ver); 3208 return -EINVAL; 3209 } 3210 3211 hcmd.data[0] = ▮ 3212 hcmd.len[0] = sizeof(marker); 3213 3214 ret = iwl_trans_send_cmd(fwrt->trans, &hcmd); 3215 3216 if (cmd_ver > 1 && hcmd.resp_pkt) { 3217 resp = (void *)hcmd.resp_pkt->data; 3218 IWL_DEBUG_INFO(fwrt, "FW GP2 time: %u\n", 3219 le32_to_cpu(resp->gp2)); 3220 } 3221 3222 return ret; 3223} 3224 3225void iwl_fw_dbg_stop_restart_recording(struct iwl_fw_runtime *fwrt, 3226 struct iwl_fw_dbg_params *params, 3227 bool stop) 3228{ 3229 int ret __maybe_unused = 0; 3230 3231 if (test_bit(STATUS_FW_ERROR, &fwrt->trans->status)) 3232 return; 3233 3234 if (fw_has_capa(&fwrt->fw->ucode_capa, 3235 IWL_UCODE_TLV_CAPA_DBG_SUSPEND_RESUME_CMD_SUPP)) { 3236 if (stop) 3237 iwl_fw_send_timestamp_marker_cmd(fwrt); 3238 ret = iwl_fw_dbg_suspend_resume_hcmd(fwrt->trans, stop); 3239 } else if (stop) { 3240 iwl_fw_dbg_stop_recording(fwrt->trans, params); 3241 } else { 3242 ret = iwl_fw_dbg_restart_recording(fwrt->trans, params); 3243 } 3244#ifdef CONFIG_IWLWIFI_DEBUGFS 3245 if (!ret) { 3246 if (stop) 3247 fwrt->trans->dbg.rec_on = false; 3248 else 3249 iwl_fw_set_dbg_rec_on(fwrt); 3250 } 3251#endif 3252} 3253IWL_EXPORT_SYMBOL(iwl_fw_dbg_stop_restart_recording); 3254