10SN/A// SPDX-License-Identifier: BSD-3-Clause-Clear 29595SN/A/* 30SN/A * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved. 40SN/A * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved. 50SN/A */ 60SN/A 72362SN/A#include "hal_desc.h" 80SN/A#include "hal.h" 92362SN/A#include "hal_tx.h" 100SN/A#include "hif.h" 110SN/A 120SN/A#define DSCP_TID_MAP_TBL_ENTRY_SIZE 64 130SN/A 140SN/A/* dscp_tid_map - Default DSCP-TID mapping 150SN/A *================= 160SN/A * DSCP TID 170SN/A *================= 180SN/A * 000xxx 0 190SN/A * 001xxx 1 200SN/A * 010xxx 2 212362SN/A * 011xxx 3 222362SN/A * 100xxx 4 232362SN/A * 101xxx 5 240SN/A * 110xxx 6 250SN/A * 111xxx 7 260SN/A */ 270SN/Astatic inline u8 dscp2tid(u8 dscp) 280SN/A{ 290SN/A return dscp >> 3; 300SN/A} 310SN/A 320SN/Avoid ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab, 330SN/A struct hal_tcl_data_cmd *tcl_cmd, 340SN/A struct hal_tx_info *ti) 350SN/A{ 360SN/A tcl_cmd->buf_addr_info.info0 = 370SN/A le32_encode_bits(ti->paddr, BUFFER_ADDR_INFO0_ADDR); 380SN/A tcl_cmd->buf_addr_info.info1 = 3915786Salexsch le32_encode_bits(((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT), 400SN/A BUFFER_ADDR_INFO1_ADDR); 410SN/A tcl_cmd->buf_addr_info.info1 |= 4212195Savstepan le32_encode_bits((ti->rbm_id), BUFFER_ADDR_INFO1_RET_BUF_MGR) | 430SN/A le32_encode_bits(ti->desc_id, BUFFER_ADDR_INFO1_SW_COOKIE); 440SN/A 450SN/A tcl_cmd->info0 = 460SN/A le32_encode_bits(ti->type, HAL_TCL_DATA_CMD_INFO0_DESC_TYPE) | 470SN/A le32_encode_bits(ti->bank_id, HAL_TCL_DATA_CMD_INFO0_BANK_ID); 480SN/A 490SN/A tcl_cmd->info1 = 500SN/A le32_encode_bits(ti->meta_data_flags, 510SN/A HAL_TCL_DATA_CMD_INFO1_CMD_NUM); 520SN/A 530SN/A tcl_cmd->info2 = cpu_to_le32(ti->flags0) | 540SN/A le32_encode_bits(ti->data_len, HAL_TCL_DATA_CMD_INFO2_DATA_LEN) | 559595SN/A le32_encode_bits(ti->pkt_offset, HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET); 560SN/A 570SN/A tcl_cmd->info3 = cpu_to_le32(ti->flags1) | 580SN/A le32_encode_bits(ti->tid, HAL_TCL_DATA_CMD_INFO3_TID) | 590SN/A le32_encode_bits(ti->lmac_id, HAL_TCL_DATA_CMD_INFO3_PMAC_ID) | 600SN/A le32_encode_bits(ti->vdev_id, HAL_TCL_DATA_CMD_INFO3_VDEV_ID); 610SN/A 620SN/A tcl_cmd->info4 = le32_encode_bits(ti->bss_ast_idx, 630SN/A HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX) | 640SN/A le32_encode_bits(ti->bss_ast_hash, 650SN/A HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM); 660SN/A tcl_cmd->info5 = 0; 670SN/A} 680SN/A 690SN/Avoid ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id) 700SN/A{ 710SN/A u32 ctrl_reg_val; 720SN/A u32 addr; 730SN/A u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE], dscp, tid; 740SN/A int i; 750SN/A u32 value; 760SN/A 770SN/A ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 780SN/A HAL_TCL1_RING_CMN_CTRL_REG); 790SN/A /* Enable read/write access */ 800SN/A ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 810SN/A ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 820SN/A HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val); 830SN/A 840SN/A addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP + 850SN/A (4 * id * (HAL_DSCP_TID_TBL_SIZE / 4)); 860SN/A 870SN/A /* Configure each DSCP-TID mapping in three bits there by configure 880SN/A * three bytes in an iteration. 890SN/A */ 900SN/A for (i = 0, dscp = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 3) { 910SN/A tid = dscp2tid(dscp); 920SN/A value = u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP0); 930SN/A dscp++; 940SN/A 950SN/A tid = dscp2tid(dscp); 960SN/A value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP1); 970SN/A dscp++; 980SN/A 990SN/A tid = dscp2tid(dscp); 1000SN/A value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP2); 1010SN/A dscp++; 1020SN/A 1030SN/A tid = dscp2tid(dscp); 1040SN/A value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP3); 1050SN/A dscp++; 1060SN/A 1070SN/A tid = dscp2tid(dscp); 1080SN/A value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP4); 1090SN/A dscp++; 1100SN/A 1110SN/A tid = dscp2tid(dscp); 1120SN/A value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP5); 1130SN/A dscp++; 1140SN/A 1150SN/A tid = dscp2tid(dscp); 1160SN/A value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP6); 1170SN/A dscp++; 1180SN/A 1190SN/A tid = dscp2tid(dscp); 1200SN/A value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP7); 1210SN/A dscp++; 1220SN/A 1230SN/A memcpy(&hw_map_val[i], &value, 3); 1240SN/A } 1250SN/A 1260SN/A for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) { 1270SN/A ath12k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]); 1280SN/A addr += 4; 1290SN/A } 1300SN/A 1310SN/A /* Disable read/write access */ 1320SN/A ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 1330SN/A HAL_TCL1_RING_CMN_CTRL_REG); 1340SN/A ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN; 1350SN/A ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG + 1360SN/A HAL_TCL1_RING_CMN_CTRL_REG, 1370SN/A ctrl_reg_val); 1380SN/A} 1390SN/A 1400SN/Avoid ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config, 1410SN/A u8 bank_id) 1420SN/A{ 1430SN/A ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id, 1440SN/A bank_config); 1450SN/A} 1460SN/A