1// SPDX-License-Identifier: BSD-3-Clause-Clear
2/*
3 * Copyright (c) 2018-2021 The Linux Foundation. All rights reserved.
4 * Copyright (c) 2021-2022 Qualcomm Innovation Center, Inc. All rights reserved.
5 */
6
7#include "hal_desc.h"
8#include "hal.h"
9#include "hal_tx.h"
10#include "hif.h"
11
12#define DSCP_TID_MAP_TBL_ENTRY_SIZE 64
13
14/* dscp_tid_map - Default DSCP-TID mapping
15 *=================
16 * DSCP        TID
17 *=================
18 * 000xxx      0
19 * 001xxx      1
20 * 010xxx      2
21 * 011xxx      3
22 * 100xxx      4
23 * 101xxx      5
24 * 110xxx      6
25 * 111xxx      7
26 */
27static inline u8 dscp2tid(u8 dscp)
28{
29	return dscp >> 3;
30}
31
32void ath12k_hal_tx_cmd_desc_setup(struct ath12k_base *ab,
33				  struct hal_tcl_data_cmd *tcl_cmd,
34				  struct hal_tx_info *ti)
35{
36	tcl_cmd->buf_addr_info.info0 =
37		le32_encode_bits(ti->paddr, BUFFER_ADDR_INFO0_ADDR);
38	tcl_cmd->buf_addr_info.info1 =
39		le32_encode_bits(((uint64_t)ti->paddr >> HAL_ADDR_MSB_REG_SHIFT),
40				 BUFFER_ADDR_INFO1_ADDR);
41	tcl_cmd->buf_addr_info.info1 |=
42		le32_encode_bits((ti->rbm_id), BUFFER_ADDR_INFO1_RET_BUF_MGR) |
43		le32_encode_bits(ti->desc_id, BUFFER_ADDR_INFO1_SW_COOKIE);
44
45	tcl_cmd->info0 =
46		le32_encode_bits(ti->type, HAL_TCL_DATA_CMD_INFO0_DESC_TYPE) |
47		le32_encode_bits(ti->bank_id, HAL_TCL_DATA_CMD_INFO0_BANK_ID);
48
49	tcl_cmd->info1 =
50		le32_encode_bits(ti->meta_data_flags,
51				 HAL_TCL_DATA_CMD_INFO1_CMD_NUM);
52
53	tcl_cmd->info2 = cpu_to_le32(ti->flags0) |
54		le32_encode_bits(ti->data_len, HAL_TCL_DATA_CMD_INFO2_DATA_LEN) |
55		le32_encode_bits(ti->pkt_offset, HAL_TCL_DATA_CMD_INFO2_PKT_OFFSET);
56
57	tcl_cmd->info3 = cpu_to_le32(ti->flags1) |
58		le32_encode_bits(ti->tid, HAL_TCL_DATA_CMD_INFO3_TID) |
59		le32_encode_bits(ti->lmac_id, HAL_TCL_DATA_CMD_INFO3_PMAC_ID) |
60		le32_encode_bits(ti->vdev_id, HAL_TCL_DATA_CMD_INFO3_VDEV_ID);
61
62	tcl_cmd->info4 = le32_encode_bits(ti->bss_ast_idx,
63					  HAL_TCL_DATA_CMD_INFO4_SEARCH_INDEX) |
64			 le32_encode_bits(ti->bss_ast_hash,
65					  HAL_TCL_DATA_CMD_INFO4_CACHE_SET_NUM);
66	tcl_cmd->info5 = 0;
67}
68
69void ath12k_hal_tx_set_dscp_tid_map(struct ath12k_base *ab, int id)
70{
71	u32 ctrl_reg_val;
72	u32 addr;
73	u8 hw_map_val[HAL_DSCP_TID_TBL_SIZE], dscp, tid;
74	int i;
75	u32 value;
76
77	ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
78					 HAL_TCL1_RING_CMN_CTRL_REG);
79	/* Enable read/write access */
80	ctrl_reg_val |= HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
81	ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
82			   HAL_TCL1_RING_CMN_CTRL_REG, ctrl_reg_val);
83
84	addr = HAL_SEQ_WCSS_UMAC_TCL_REG + HAL_TCL1_RING_DSCP_TID_MAP +
85	       (4 * id * (HAL_DSCP_TID_TBL_SIZE / 4));
86
87	/* Configure each DSCP-TID mapping in three bits there by configure
88	 * three bytes in an iteration.
89	 */
90	for (i = 0, dscp = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 3) {
91		tid = dscp2tid(dscp);
92		value = u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP0);
93		dscp++;
94
95		tid = dscp2tid(dscp);
96		value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP1);
97		dscp++;
98
99		tid = dscp2tid(dscp);
100		value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP2);
101		dscp++;
102
103		tid = dscp2tid(dscp);
104		value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP3);
105		dscp++;
106
107		tid = dscp2tid(dscp);
108		value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP4);
109		dscp++;
110
111		tid = dscp2tid(dscp);
112		value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP5);
113		dscp++;
114
115		tid = dscp2tid(dscp);
116		value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP6);
117		dscp++;
118
119		tid = dscp2tid(dscp);
120		value |= u32_encode_bits(tid, HAL_TCL1_RING_FIELD_DSCP_TID_MAP7);
121		dscp++;
122
123		memcpy(&hw_map_val[i], &value, 3);
124	}
125
126	for (i = 0; i < HAL_DSCP_TID_TBL_SIZE; i += 4) {
127		ath12k_hif_write32(ab, addr, *(u32 *)&hw_map_val[i]);
128		addr += 4;
129	}
130
131	/* Disable read/write access */
132	ctrl_reg_val = ath12k_hif_read32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
133					 HAL_TCL1_RING_CMN_CTRL_REG);
134	ctrl_reg_val &= ~HAL_TCL1_RING_CMN_CTRL_DSCP_TID_MAP_PROG_EN;
135	ath12k_hif_write32(ab, HAL_SEQ_WCSS_UMAC_TCL_REG +
136			   HAL_TCL1_RING_CMN_CTRL_REG,
137			   ctrl_reg_val);
138}
139
140void ath12k_hal_tx_configure_bank_register(struct ath12k_base *ab, u32 bank_config,
141					   u8 bank_id)
142{
143	ath12k_hif_write32(ab, HAL_TCL_SW_CONFIG_BANK_ADDR + 4 * bank_id,
144			   bank_config);
145}
146