1/*- 2******************************************************************************** 3Copyright (C) 2015 Annapurna Labs Ltd. 4 5This file may be licensed under the terms of the Annapurna Labs Commercial 6License Agreement. 7 8Alternatively, this file can be distributed under the terms of the GNU General 9Public License V2 as published by the Free Software Foundation and can be 10found at http://www.gnu.org/licenses/gpl-2.0.html 11 12Alternatively, redistribution and use in source and binary forms, with or 13without modification, are permitted provided that the following conditions are 14met: 15 16 * Redistributions of source code must retain the above copyright notice, 17this list of conditions and the following disclaimer. 18 19 * Redistributions in binary form must reproduce the above copyright 20notice, this list of conditions and the following disclaimer in 21the documentation and/or other materials provided with the 22distribution. 23 24THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND 25ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED 26WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 27DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR 28ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 29(INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 30LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON 31ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 32(INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS 33SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 34 35*******************************************************************************/ 36 37#ifndef __AL_HAL_PCIE_REGS_H__ 38#define __AL_HAL_PCIE_REGS_H__ 39 40/* Note: Definitions before the includes so axi/wrapper regs sees them */ 41 42/** Maximum physical functions supported */ 43#define REV1_2_MAX_NUM_OF_PFS 1 44#define REV3_MAX_NUM_OF_PFS 4 45#define AL_MAX_NUM_OF_PFS 4 /* the maximum between all Revisions */ 46 47#include "al_hal_pcie_axi_reg.h" 48#ifndef AL_PCIE_EX 49#include "al_hal_pcie_w_reg.h" 50#else 51#include "al_hal_pcie_w_reg_ex.h" 52#endif 53 54#define AL_PCIE_AXI_REGS_OFFSET 0x0 55#define AL_PCIE_REV_1_2_APP_REGS_OFFSET 0x1000 56#define AL_PCIE_REV_3_APP_REGS_OFFSET 0x2000 57#define AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET 0x2000 58#define AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET 0x10000 59 60/** Maximum number of lanes supported */ 61#define REV1_2_MAX_NUM_LANES 4 62#define REV3_MAX_NUM_LANES 8 63#define AL_MAX_NUM_OF_LANES 8 /* the maximum between all Revisions */ 64 65/** Number of outbound atu regions - rev 1/2 */ 66#define AL_PCIE_REV_1_2_ATU_NUM_OUTBOUND_REGIONS 12 67/** Number of outbound atu regions - rev 3 */ 68#define AL_PCIE_REV_3_ATU_NUM_OUTBOUND_REGIONS 16 69 70struct al_pcie_core_iatu_regs { 71 uint32_t index; 72 uint32_t cr1; 73 uint32_t cr2; 74 uint32_t lower_base_addr; 75 uint32_t upper_base_addr; 76 uint32_t limit_addr; 77 uint32_t lower_target_addr; 78 uint32_t upper_target_addr; 79 uint32_t cr3; 80 uint32_t rsrvd[(0x270 - 0x224) >> 2]; 81}; 82 83struct al_pcie_core_port_regs { 84 uint32_t ack_lat_rply_timer; 85 uint32_t reserved1[(0x10 - 0x4) >> 2]; 86 uint32_t port_link_ctrl; 87 uint32_t reserved2[(0x18 - 0x14) >> 2]; 88 uint32_t timer_ctrl_max_func_num; 89 uint32_t filter_mask_reg_1; 90 uint32_t reserved3[(0x48 - 0x20) >> 2]; 91 uint32_t vc0_posted_rcv_q_ctrl; 92 uint32_t vc0_non_posted_rcv_q_ctrl; 93 uint32_t vc0_comp_rcv_q_ctrl; 94 uint32_t reserved4[(0x10C - 0x54) >> 2]; 95 uint32_t gen2_ctrl; 96 uint32_t reserved5[(0x190 - 0x110) >> 2]; 97 uint32_t gen3_ctrl; 98 uint32_t gen3_eq_fs_lf; 99 uint32_t gen3_eq_preset_to_coef_map; 100 uint32_t gen3_eq_preset_idx; 101 uint32_t reserved6; 102 uint32_t gen3_eq_status; 103 uint32_t gen3_eq_ctrl; 104 uint32_t reserved7[(0x1B8 - 0x1AC) >> 2]; 105 uint32_t pipe_loopback_ctrl; 106 uint32_t rd_only_wr_en; 107 uint32_t reserved8[(0x1D0 - 0x1C0) >> 2]; 108 uint32_t axi_slave_err_resp; 109 uint32_t reserved9[(0x200 - 0x1D4) >> 2]; 110 struct al_pcie_core_iatu_regs iatu; 111 uint32_t reserved10[(0x448 - 0x270) >> 2]; 112}; 113 114struct al_pcie_core_aer_regs { 115 /* 0x0 - PCI Express Extended Capability Header */ 116 uint32_t header; 117 /* 0x4 - Uncorrectable Error Status Register */ 118 uint32_t uncorr_err_stat; 119 /* 0x8 - Uncorrectable Error Mask Register */ 120 uint32_t uncorr_err_mask; 121 /* 0xc - Uncorrectable Error Severity Register */ 122 uint32_t uncorr_err_severity; 123 /* 0x10 - Correctable Error Status Register */ 124 uint32_t corr_err_stat; 125 /* 0x14 - Correctable Error Mask Register */ 126 uint32_t corr_err_mask; 127 /* 0x18 - Advanced Error Capabilities and Control Register */ 128 uint32_t cap_and_ctrl; 129 /* 0x1c - Header Log Registers */ 130 uint32_t header_log[4]; 131 /* 0x2c - Root Error Command Register */ 132 uint32_t root_err_cmd; 133 /* 0x30 - Root Error Status Register */ 134 uint32_t root_err_stat; 135 /* 0x34 - Error Source Identification Register */ 136 uint32_t err_src_id; 137}; 138 139struct al_pcie_core_reg_space_rev_1_2 { 140 uint32_t config_header[0x40 >> 2]; 141 uint32_t pcie_pm_cap_base; 142 uint32_t reserved1[(0x70 - 0x44) >> 2]; 143 uint32_t pcie_cap_base; 144 uint32_t pcie_dev_cap_base; 145 uint32_t pcie_dev_ctrl_status; 146 uint32_t pcie_link_cap_base; 147 uint32_t reserved2[(0xB0 - 0x80) >> 2]; 148 uint32_t msix_cap_base; 149 uint32_t reserved3[(0x100 - 0xB4) >> 2]; 150 struct al_pcie_core_aer_regs aer; 151 uint32_t reserved4[(0x150 - 152 (0x100 + 153 sizeof(struct al_pcie_core_aer_regs))) >> 2]; 154 uint32_t pcie_sec_ext_cap_base; 155 uint32_t reserved5[(0x700 - 0x154) >> 2]; 156 struct al_pcie_core_port_regs port_regs; 157 uint32_t reserved6[(0x1000 - 158 (0x700 + 159 sizeof(struct al_pcie_core_port_regs))) >> 2]; 160}; 161 162struct al_pcie_core_reg_space_rev_3 { 163 uint32_t config_header[0x40 >> 2]; 164 uint32_t pcie_pm_cap_base; 165 uint32_t reserved1[(0x70 - 0x44) >> 2]; 166 uint32_t pcie_cap_base; 167 uint32_t pcie_dev_cap_base; 168 uint32_t pcie_dev_ctrl_status; 169 uint32_t pcie_link_cap_base; 170 uint32_t reserved2[(0xB0 - 0x80) >> 2]; 171 uint32_t msix_cap_base; 172 uint32_t reserved3[(0x100 - 0xB4) >> 2]; 173 struct al_pcie_core_aer_regs aer; 174 uint32_t reserved4[(0x158 - 175 (0x100 + 176 sizeof(struct al_pcie_core_aer_regs))) >> 2]; 177 /* pcie_sec_cap is only applicable for function 0 */ 178 uint32_t pcie_sec_ext_cap_base; 179 uint32_t reserved5[(0x178 - 0x15C) >> 2]; 180 /* tph capability is only applicable for rev3 */ 181 uint32_t tph_cap_base; 182 uint32_t reserved6[(0x700 - 0x17C) >> 2]; 183 /* port_regs is only applicable for function 0 */ 184 struct al_pcie_core_port_regs port_regs; 185 uint32_t reserved7[(0x1000 - 186 (0x700 + 187 sizeof(struct al_pcie_core_port_regs))) >> 2]; 188}; 189 190struct al_pcie_rev3_core_reg_space { 191 struct al_pcie_core_reg_space_rev_3 func[REV3_MAX_NUM_OF_PFS]; 192}; 193 194struct al_pcie_core_reg_space { 195 uint32_t *config_header; 196 uint32_t *pcie_pm_cap_base; 197 uint32_t *pcie_cap_base; 198 uint32_t *pcie_dev_cap_base; 199 uint32_t *pcie_dev_ctrl_status; 200 uint32_t *pcie_link_cap_base; 201 uint32_t *msix_cap_base; 202 struct al_pcie_core_aer_regs *aer; 203 uint32_t *pcie_sec_ext_cap_base; 204 uint32_t *tph_cap_base; 205}; 206 207struct al_pcie_revx_regs { 208 struct al_pcie_revx_axi_regs __iomem axi; 209}; 210 211struct al_pcie_rev1_regs { 212 struct al_pcie_rev1_axi_regs __iomem axi; 213 uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET - 214 (AL_PCIE_AXI_REGS_OFFSET + 215 sizeof(struct al_pcie_rev1_axi_regs))) >> 2]; 216 struct al_pcie_rev1_w_regs __iomem app; 217 uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET - 218 (AL_PCIE_REV_1_2_APP_REGS_OFFSET + 219 sizeof(struct al_pcie_rev1_w_regs))) >> 2]; 220 struct al_pcie_core_reg_space_rev_1_2 core_space; 221}; 222 223struct al_pcie_rev2_regs { 224 struct al_pcie_rev2_axi_regs __iomem axi; 225 uint32_t reserved1[(AL_PCIE_REV_1_2_APP_REGS_OFFSET - 226 (AL_PCIE_AXI_REGS_OFFSET + 227 sizeof(struct al_pcie_rev2_axi_regs))) >> 2]; 228 struct al_pcie_rev2_w_regs __iomem app; 229 uint32_t reserved2[(AL_PCIE_REV_1_2_CORE_CONF_BASE_OFFSET - 230 (AL_PCIE_REV_1_2_APP_REGS_OFFSET + 231 sizeof(struct al_pcie_rev2_w_regs))) >> 2]; 232 struct al_pcie_core_reg_space_rev_1_2 core_space; 233}; 234 235struct al_pcie_rev3_regs { 236 struct al_pcie_rev3_axi_regs __iomem axi; 237 uint32_t reserved1[(AL_PCIE_REV_3_APP_REGS_OFFSET - 238 (AL_PCIE_AXI_REGS_OFFSET + 239 sizeof(struct al_pcie_rev3_axi_regs))) >> 2]; 240 struct al_pcie_rev3_w_regs __iomem app; 241 uint32_t reserved2[(AL_PCIE_REV_3_CORE_CONF_BASE_OFFSET - 242 (AL_PCIE_REV_3_APP_REGS_OFFSET + 243 sizeof(struct al_pcie_rev3_w_regs))) >> 2]; 244 struct al_pcie_rev3_core_reg_space core_space; 245}; 246 247struct al_pcie_axi_ctrl { 248 uint32_t *global; 249 uint32_t *master_rctl; 250 uint32_t *master_arctl; 251 uint32_t *master_awctl; 252 uint32_t *master_ctl; 253 uint32_t *slv_ctl; 254}; 255 256struct al_pcie_axi_ob_ctrl { 257 uint32_t *cfg_target_bus; 258 uint32_t *cfg_control; 259 uint32_t *io_start_l; 260 uint32_t *io_start_h; 261 uint32_t *io_limit_l; 262 uint32_t *io_limit_h; 263 uint32_t *io_addr_mask_h; /* Rev 3 only */ 264 uint32_t *ar_msg_addr_mask_h; /* Rev 3 only */ 265 uint32_t *aw_msg_addr_mask_h; /* Rev 3 only */ 266 uint32_t *tgtid_reg_ovrd; /* Rev 2/3 only */ 267 uint32_t *addr_high_reg_ovrd_value; /* Rev 2/3 only */ 268 uint32_t *addr_high_reg_ovrd_sel; /* Rev 2/3 only */ 269 uint32_t *addr_size_replace; /* Rev 2/3 only */ 270}; 271 272struct al_pcie_axi_pcie_global { 273 uint32_t *conf; 274}; 275 276struct al_pcie_axi_conf { 277 uint32_t *zero_lane0; 278 uint32_t *zero_lane1; 279 uint32_t *zero_lane2; 280 uint32_t *zero_lane3; 281 uint32_t *zero_lane4; 282 uint32_t *zero_lane5; 283 uint32_t *zero_lane6; 284 uint32_t *zero_lane7; 285}; 286 287struct al_pcie_axi_status { 288 uint32_t *lane[AL_MAX_NUM_OF_LANES]; 289}; 290 291struct al_pcie_axi_parity { 292 uint32_t *en_axi; 293}; 294 295struct al_pcie_axi_ordering { 296 uint32_t *pos_cntl; 297}; 298 299struct al_pcie_axi_pre_configuration { 300 uint32_t *pcie_core_setup; 301}; 302 303struct al_pcie_axi_init_fc { 304 uint32_t *cfg; 305}; 306 307struct al_pcie_axi_attr_ovrd { 308 uint32_t *write_msg_ctrl_0; 309 uint32_t *write_msg_ctrl_1; 310 uint32_t *pf_sel; 311}; 312 313struct al_pcie_axi_pf_axi_attr_ovrd { 314 uint32_t *func_ctrl_0; 315 uint32_t *func_ctrl_1; 316 uint32_t *func_ctrl_2; 317 uint32_t *func_ctrl_3; 318 uint32_t *func_ctrl_4; 319 uint32_t *func_ctrl_5; 320 uint32_t *func_ctrl_6; 321 uint32_t *func_ctrl_7; 322 uint32_t *func_ctrl_8; 323 uint32_t *func_ctrl_9; 324}; 325 326struct al_pcie_axi_msg_attr_axuser_table { 327 uint32_t *entry_vec; 328}; 329 330struct al_pcie_axi_regs { 331 struct al_pcie_axi_ctrl ctrl; 332 struct al_pcie_axi_ob_ctrl ob_ctrl; 333 struct al_pcie_axi_pcie_global pcie_global; 334 struct al_pcie_axi_conf conf; 335 struct al_pcie_axi_status status; 336 struct al_pcie_axi_parity parity; 337 struct al_pcie_axi_ordering ordering; 338 struct al_pcie_axi_pre_configuration pre_configuration; 339 struct al_pcie_axi_init_fc init_fc; 340 struct al_pcie_revx_axi_int_grp_a_axi *int_grp_a; 341 /* Rev3 only */ 342 struct al_pcie_axi_attr_ovrd axi_attr_ovrd; 343 struct al_pcie_axi_pf_axi_attr_ovrd pf_axi_attr_ovrd[REV3_MAX_NUM_OF_PFS]; 344 struct al_pcie_axi_msg_attr_axuser_table msg_attr_axuser_table; 345}; 346 347struct al_pcie_w_global_ctrl { 348 uint32_t *port_init; 349 uint32_t *pm_control; 350 uint32_t *events_gen[REV3_MAX_NUM_OF_PFS]; 351 uint32_t *corr_err_sts_int; 352 uint32_t *uncorr_err_sts_int; 353 uint32_t *sris_kp_counter; 354}; 355 356struct al_pcie_w_soc_int { 357 uint32_t *status_0; 358 uint32_t *status_1; 359 uint32_t *status_2; 360 uint32_t *status_3; /* Rev 2/3 only */ 361 uint32_t *mask_inta_leg_0; 362 uint32_t *mask_inta_leg_1; 363 uint32_t *mask_inta_leg_2; 364 uint32_t *mask_inta_leg_3; /* Rev 2/3 only */ 365 uint32_t *mask_msi_leg_0; 366 uint32_t *mask_msi_leg_1; 367 uint32_t *mask_msi_leg_2; 368 uint32_t *mask_msi_leg_3; /* Rev 2/3 only */ 369}; 370struct al_pcie_w_atu { 371 uint32_t *in_mask_pair; 372 uint32_t *out_mask_pair; 373 uint32_t *reg_out_mask; /* Rev 3 only */ 374}; 375 376struct al_pcie_w_regs { 377 struct al_pcie_w_global_ctrl global_ctrl; 378 struct al_pcie_revx_w_debug *debug; 379 struct al_pcie_revx_w_ap_user_send_msg *ap_user_send_msg; 380 struct al_pcie_w_soc_int soc_int[REV3_MAX_NUM_OF_PFS]; 381 struct al_pcie_revx_w_cntl_gen *ctrl_gen; 382 struct al_pcie_revx_w_parity *parity; 383 struct al_pcie_w_atu atu; 384 struct al_pcie_revx_w_status_per_func *status_per_func[REV3_MAX_NUM_OF_PFS]; 385 struct al_pcie_revx_w_int_grp *int_grp_a; 386 struct al_pcie_revx_w_int_grp *int_grp_b; 387 struct al_pcie_revx_w_int_grp *int_grp_c; 388 struct al_pcie_revx_w_int_grp *int_grp_d; 389 struct al_pcie_rev3_w_cfg_func_ext *cfg_func_ext; /* Rev 3 only */ 390}; 391 392struct al_pcie_regs { 393 struct al_pcie_axi_regs axi; 394 struct al_pcie_w_regs app; 395 struct al_pcie_core_port_regs *port_regs; 396 struct al_pcie_core_reg_space core_space[REV3_MAX_NUM_OF_PFS]; 397}; 398 399#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_EP 0 400#define PCIE_AXI_MISC_PCIE_GLOBAL_CONF_DEV_TYPE_RC 4 401 402#define PCIE_PORT_GEN2_CTRL_DIRECT_SPEED_CHANGE AL_BIT(17) 403#define PCIE_PORT_GEN2_CTRL_TX_SWING_LOW_SHIFT 18 404#define PCIE_PORT_GEN2_CTRL_TX_COMPLIANCE_RCV_SHIFT 19 405#define PCIE_PORT_GEN2_CTRL_DEEMPHASIS_SET_SHIFT 20 406#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_MASK AL_FIELD_MASK(12, 8) 407#define PCIE_PORT_GEN2_CTRL_NUM_OF_LANES_SHIFT 8 408 409#define PCIE_PORT_GEN3_CTRL_EQ_PHASE_2_3_DISABLE_SHIFT 9 410#define PCIE_PORT_GEN3_CTRL_EQ_DISABLE_SHIFT 16 411 412#define PCIE_PORT_GEN3_EQ_LF_SHIFT 0 413#define PCIE_PORT_GEN3_EQ_LF_MASK 0x3f 414#define PCIE_PORT_GEN3_EQ_FS_SHIFT 6 415#define PCIE_PORT_GEN3_EQ_FS_MASK (0x3f << PCIE_PORT_GEN3_EQ_FS_SHIFT) 416 417#define PCIE_PORT_LINK_CTRL_LB_EN_SHIFT 2 418#define PCIE_PORT_LINK_CTRL_FAST_LINK_EN_SHIFT 7 419#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_MASK AL_FIELD_MASK(21, 16) 420#define PCIE_PORT_LINK_CTRL_LINK_CAPABLE_SHIFT 16 421 422#define PCIE_PORT_PIPE_LOOPBACK_CTRL_PIPE_LB_EN_SHIFT 31 423 424#define PCIE_PORT_AXI_SLAVE_ERR_RESP_ALL_MAPPING_SHIFT 0 425 426/** timer_ctrl_max_func_num register 427 * Max physical function number (for example: 0 for 1PF, 3 for 4PFs) 428 */ 429#define PCIE_PORT_GEN3_MAX_FUNC_NUM AL_FIELD_MASK(7, 0) 430 431/* filter_mask_reg_1 register */ 432/** 433 * SKP Interval Value. 434 * The number of symbol times to wait between transmitting SKP ordered sets 435 */ 436#define PCIE_FLT_MASK_SKP_INT_VAL_MASK AL_FIELD_MASK(10, 0) 437 438/* 439 * 0: Treat Function MisMatched TLPs as UR 440 * 1: Treat Function MisMatched TLPs as Supported 441 */ 442#define CX_FLT_MASK_UR_FUNC_MISMATCH AL_BIT(16) 443 444/* 445 * 0: Treat CFG type1 TLPs as UR for EP; Supported for RC 446 * 1: Treat CFG type1 TLPs as Supported for EP; UR for RC 447 */ 448#define CX_FLT_MASK_CFG_TYPE1_RE_AS_UR AL_BIT(19) 449 450/* 451 * 0: Enforce requester id match for received CPL TLPs. 452 * A violation results in cpl_abort, and possibly AER of unexp_cpl_err, 453 * cpl_rcvd_ur, cpl_rcvd_ca 454 * 1: Mask requester id match for received CPL TLPs 455 */ 456#define CX_FLT_MASK_CPL_REQID_MATCH AL_BIT(22) 457 458/* 459 * 0: Enforce function match for received CPL TLPs. 460 * A violation results in cpl_abort, and possibly AER of unexp_cpl_err, 461 * cpl_rcvd_ur, cpl_rcvd_ca 462 * 1: Mask function match for received CPL TLPs 463 */ 464#define CX_FLT_MASK_CPL_FUNC_MATCH AL_BIT(23) 465 466/* vc0_posted_rcv_q_ctrl register */ 467#define RADM_PQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12) 468#define RADM_PQ_HCRD_VC0_SHIFT 12 469 470/* vc0_non_posted_rcv_q_ctrl register */ 471#define RADM_NPQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12) 472#define RADM_NPQ_HCRD_VC0_SHIFT 12 473 474/* vc0_comp_rcv_q_ctrl register */ 475#define RADM_CPLQ_HCRD_VC0_MASK AL_FIELD_MASK(19, 12) 476#define RADM_CPLQ_HCRD_VC0_SHIFT 12 477 478/**** iATU, Control Register 1 ****/ 479 480/** 481 * When the Address and BAR matching logic in the core indicate that a MEM-I/O 482 * transaction matches a BAR in the function corresponding to this value, then 483 * address translation proceeds. This check is only performed if the "Function 484 * Number Match Enable" bit of the "iATU Control 2 Register" is set 485 */ 486#define PCIE_IATU_CR1_FUNC_NUM_MASK AL_FIELD_MASK(24, 20) 487#define PCIE_IATU_CR1_FUNC_NUM_SHIFT 20 488 489/**** iATU, Control Register 2 ****/ 490/** For outbound regions, the Function Number Translation Bypass mode enables 491 * taking the function number of the translated TLP from the PCIe core 492 * interface and not from the "Function Number" field of CR1. 493 * For inbound regions, this bit should be asserted when physical function 494 * match mode needs to be enabled 495 */ 496#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_MASK AL_BIT(19) 497#define PCIE_IATU_CR2_FUNC_NUM_TRANS_BYPASS_FUNC_MATCH_ENABLE_SHIFT 19 498 499/* pcie_dev_ctrl_status register */ 500#define PCIE_PORT_DEV_CTRL_STATUS_CORR_ERR_REPORT_EN AL_BIT(0) 501#define PCIE_PORT_DEV_CTRL_STATUS_NON_FTL_ERR_REPORT_EN AL_BIT(1) 502#define PCIE_PORT_DEV_CTRL_STATUS_FTL_ERR_REPORT_EN AL_BIT(2) 503#define PCIE_PORT_DEV_CTRL_STATUS_UNSUP_REQ_REPORT_EN AL_BIT(3) 504 505#define PCIE_PORT_DEV_CTRL_STATUS_MPS_MASK AL_FIELD_MASK(7, 5) 506#define PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT 5 507#define PCIE_PORT_DEV_CTRL_STATUS_MPS_VAL_256 (1 << PCIE_PORT_DEV_CTRL_STATUS_MPS_SHIFT) 508 509#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_MASK AL_FIELD_MASK(14, 12) 510#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT 12 511#define PCIE_PORT_DEV_CTRL_STATUS_MRRS_VAL_256 (1 << PCIE_PORT_DEV_CTRL_STATUS_MRRS_SHIFT) 512 513/****************************************************************************** 514 * AER registers 515 ******************************************************************************/ 516/* PCI Express Extended Capability ID */ 517#define PCIE_AER_CAP_ID_MASK AL_FIELD_MASK(15, 0) 518#define PCIE_AER_CAP_ID_SHIFT 0 519#define PCIE_AER_CAP_ID_VAL 1 520/* Capability Version */ 521#define PCIE_AER_CAP_VER_MASK AL_FIELD_MASK(19, 16) 522#define PCIE_AER_CAP_VER_SHIFT 16 523#define PCIE_AER_CAP_VER_VAL 2 524 525/* First Error Pointer */ 526#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_MASK AL_FIELD_MASK(4, 0) 527#define PCIE_AER_CTRL_STAT_FIRST_ERR_PTR_SHIFT 0 528/* ECRC Generation Capability */ 529#define PCIE_AER_CTRL_STAT_ECRC_GEN_SUPPORTED AL_BIT(5) 530/* ECRC Generation Enable */ 531#define PCIE_AER_CTRL_STAT_ECRC_GEN_EN AL_BIT(6) 532/* ECRC Check Capable */ 533#define PCIE_AER_CTRL_STAT_ECRC_CHK_SUPPORTED AL_BIT(7) 534/* ECRC Check Enable */ 535#define PCIE_AER_CTRL_STAT_ECRC_CHK_EN AL_BIT(8) 536 537/* Correctable Error Reporting Enable */ 538#define PCIE_AER_ROOT_ERR_CMD_CORR_ERR_RPRT_EN AL_BIT(0) 539/* Non-Fatal Error Reporting Enable */ 540#define PCIE_AER_ROOT_ERR_CMD_NON_FTL_ERR_RPRT_EN AL_BIT(1) 541/* Fatal Error Reporting Enable */ 542#define PCIE_AER_ROOT_ERR_CMD_FTL_ERR_RPRT_EN AL_BIT(2) 543 544/* ERR_COR Received */ 545#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR AL_BIT(0) 546/* Multiple ERR_COR Received */ 547#define PCIE_AER_ROOT_ERR_STAT_CORR_ERR_MULTI AL_BIT(1) 548/* ERR_FATAL/NONFATAL Received */ 549#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR AL_BIT(2) 550/* Multiple ERR_FATAL/NONFATAL Received */ 551#define PCIE_AER_ROOT_ERR_STAT_FTL_NON_FTL_ERR_MULTI AL_BIT(3) 552/* First Uncorrectable Fatal */ 553#define PCIE_AER_ROOT_ERR_STAT_FIRST_UNCORR_FTL AL_BIT(4) 554/* Non-Fatal Error Messages Received */ 555#define PCIE_AER_ROOT_ERR_STAT_NON_FTL_RCVD AL_BIT(5) 556/* Fatal Error Messages Received */ 557#define PCIE_AER_ROOT_ERR_STAT_FTL_RCVD AL_BIT(6) 558/* Advanced Error Interrupt Message Number */ 559#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_MASK AL_FIELD_MASK(31, 27) 560#define PCIE_AER_ROOT_ERR_STAT_ERR_INT_MSG_NUM_SHIFT 27 561 562/* ERR_COR Source Identification */ 563#define PCIE_AER_SRC_ID_CORR_ERR_MASK AL_FIELD_MASK(15, 0) 564#define PCIE_AER_SRC_ID_CORR_ERR_SHIFT 0 565/* ERR_FATAL/NONFATAL Source Identification */ 566#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_MASK AL_FIELD_MASK(31, 16) 567#define PCIE_AER_SRC_ID_CORR_ERR_FTL_NON_FTL_SHIFT 16 568 569/* AER message */ 570#define PCIE_AER_MSG_REQID_MASK AL_FIELD_MASK(31, 16) 571#define PCIE_AER_MSG_REQID_SHIFT 16 572#define PCIE_AER_MSG_TYPE_MASK AL_FIELD_MASK(15, 8) 573#define PCIE_AER_MSG_TYPE_SHIFT 8 574#define PCIE_AER_MSG_RESERVED AL_FIELD_MASK(7, 1) 575#define PCIE_AER_MSG_VALID AL_BIT(0) 576/* AER message ack */ 577#define PCIE_AER_MSG_ACK AL_BIT(0) 578/* AER errors definitions */ 579#define AL_PCIE_AER_TYPE_CORR (0x30) 580#define AL_PCIE_AER_TYPE_NON_FATAL (0x31) 581#define AL_PCIE_AER_TYPE_FATAL (0x33) 582/* Requester ID Bus */ 583#define AL_PCIE_REQID_BUS_NUM_SHIFT (8) 584 585/****************************************************************************** 586 * TPH registers 587 ******************************************************************************/ 588#define PCIE_TPH_NEXT_POINTER AL_FIELD_MASK(31, 20) 589 590/****************************************************************************** 591 * Config Header registers 592 ******************************************************************************/ 593/** 594 * see BIST_HEADER_TYPE_LATENCY_CACHE_LINE_SIZE_REG in core spec 595 * Note: valid only for EP mode 596 */ 597#define PCIE_BIST_HEADER_TYPE_BASE 0xc 598#define PCIE_BIST_HEADER_TYPE_MULTI_FUNC_MASK AL_BIT(23) 599 600/****************************************************************************** 601 * SRIS KP counters default values 602 ******************************************************************************/ 603#define PCIE_SRIS_KP_COUNTER_GEN3_DEFAULT_VAL (0x24) 604#define PCIE_SRIS_KP_COUNTER_GEN21_DEFAULT_VAL (0x4B) 605 606#endif 607