1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2022 Soren Schmidt <sos@deepcore.dk>
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/param.h>
29#include <sys/bus.h>
30#include <sys/kernel.h>
31#include <sys/module.h>
32#include <sys/mutex.h>
33#include <sys/rman.h>
34#include <machine/bus.h>
35
36#include <dev/ofw/openfirm.h>
37#include <dev/ofw/ofw_bus.h>
38#include <dev/ofw/ofw_bus_subr.h>
39
40#include <dev/syscon/syscon.h>
41#include <dev/fdt/simple_mfd.h>
42
43#include "rk_otp.h"
44#include "rk_otp_if.h"
45
46#define	OTPC_SBPI_CTRL			0x0020
47#define	 SBPI_ENABLE_MASK		0x00010000
48#define	 SBPI_ENABLE			1
49#define	 SBPI_DAP_ADDR_MASK		0xff000000
50#define	 SBPI_DAP_ADDR			0x02
51#define	 SBPI_DAP_ADDR_SHIFT		8
52#define	OTPC_SBPI_CMD_VALID_PRE		0x0024
53#define	 SBPI_CMD_VALID_MASK		0xffff0000
54#define	OTPC_SBPI_INT_STATUS		0x0304
55#define	 OTPC_SBPI_DONE			2
56#define	 OTPC_USER_DONE			4
57#define	OTPC_USER_CTRL			0x0100
58#define	 OTPC_USER_MASK			0xffff0000
59#define	 OTPC_USER			1
60#define	OTPC_USER_ADDR			0x0104
61#define	 OTPC_USER_ADDR_MASK 		0xffff0000
62#define	OTPC_USER_ENABLE		0x0108
63#define	 OTPC_USER_FSM_ENABLE_MASK	0xffff0000
64#define	 OTPC_USER_FSM_ENABLE		1
65#define	OTPC_USER_Q			0x0124
66#define	OTPC_SBPI_CMD0_OFFSET		0x1000
67#define	 SBPI_DAP_CMD_WRF		0xc0
68#define	 SBPI_DAP_REG_ECC		0x3a
69#define	OTPC_SBPI_CMD1_OFFSET		0x1004
70#define	 SBPI_ECC_ENABLE		0x00
71#define	 SBPI_ECC_DISABLE		0x09
72
73
74static struct ofw_compat_data compat_data[] = {
75	{"rockchip,rk3568-otp",	1},
76	{NULL,			0}
77};
78
79static struct rk_otp_softc {
80	struct resource *mem;
81} rk_otp_sc;
82
83
84static int
85rk_otp_wait(struct rk_otp_softc *sc, uint32_t status)
86{
87	int retry = 10000;
88
89	while (!(bus_read_4(sc->mem, OTPC_SBPI_INT_STATUS) & status)) {
90		DELAY(10);
91		if (--retry == 0)
92			return (ETIMEDOUT);
93	}
94
95	/* clear status */
96	bus_write_4(sc->mem, OTPC_SBPI_INT_STATUS, status);
97
98	return (0);
99}
100
101static int
102rk_otp_ecc(struct rk_otp_softc *sc, int enable)
103{
104	bus_write_4(sc->mem, OTPC_SBPI_CTRL,
105	    SBPI_DAP_ADDR_MASK | (SBPI_DAP_ADDR << SBPI_DAP_ADDR_SHIFT));
106	bus_write_4(sc->mem, OTPC_SBPI_CMD_VALID_PRE,
107	    SBPI_CMD_VALID_MASK | 0x1);
108	bus_write_4(sc->mem, OTPC_SBPI_CMD0_OFFSET,
109	    SBPI_DAP_CMD_WRF | SBPI_DAP_REG_ECC);
110	if (enable)
111		bus_write_4(sc->mem, OTPC_SBPI_CMD1_OFFSET, SBPI_ECC_ENABLE);
112	else
113		bus_write_4(sc->mem, OTPC_SBPI_CMD1_OFFSET, SBPI_ECC_DISABLE);
114	bus_write_4(sc->mem, OTPC_SBPI_CTRL, SBPI_ENABLE_MASK | SBPI_ENABLE);
115
116	return (rk_otp_wait(sc, OTPC_SBPI_DONE));
117}
118
119int
120rk_otp_read(device_t dev, uint8_t *buffer, int offset, int size)
121{
122	struct rk_otp_softc *sc = &rk_otp_sc;
123	int error;
124
125	/* if not initialized just error out */
126	if (!sc->mem)
127		return (ENXIO);
128
129	if ((error = rk_otp_ecc(sc, 1))) {
130		device_printf(dev, "timeout waiting for OTP ECC status\n");
131		return (error);
132	}
133
134	bus_write_4(sc->mem, OTPC_USER_CTRL, OTPC_USER | OTPC_USER_MASK);
135	DELAY(5);
136	while (size--) {
137		bus_write_4(sc->mem, OTPC_USER_ADDR,
138		    offset++ | OTPC_USER_ADDR_MASK);
139		bus_write_4(sc->mem, OTPC_USER_ENABLE,
140		    OTPC_USER_FSM_ENABLE | OTPC_USER_FSM_ENABLE_MASK);
141
142		if ((error = rk_otp_wait(sc, OTPC_USER_DONE))) {
143			device_printf(dev, "timeout waiting for OTP data\n");
144			break;
145		}
146		*buffer++ = bus_read_4(sc->mem, OTPC_USER_Q);
147	}
148	bus_write_4(sc->mem, OTPC_USER_CTRL, OTPC_USER_MASK);
149
150	return (error);
151}
152
153static int
154rk_otp_probe(device_t dev)
155{
156
157	if (!ofw_bus_status_okay(dev))
158		return (ENXIO);
159	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
160		return (ENXIO);
161	device_set_desc(dev, "RockChip OTP");
162	return (BUS_PROBE_DEFAULT);
163}
164
165static int
166rk_otp_attach(device_t dev)
167{
168	struct rk_otp_softc *sc = &rk_otp_sc;
169	int rid = 0;
170
171	sc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, RF_ACTIVE);
172	if (!sc->mem) {
173		device_printf(dev, "Cannot allocate memory resources\n");
174		return (ENXIO);
175	}
176	return (0);
177}
178
179
180static device_method_t rk_otp_methods[] = {
181	/* Device interface */
182	DEVMETHOD(device_probe,		rk_otp_probe),
183	DEVMETHOD(device_attach,	rk_otp_attach),
184
185	DEVMETHOD_END
186};
187
188DEFINE_CLASS_1(rk_otp, rk_otp_driver, rk_otp_methods,
189    sizeof(struct simple_mfd_softc), simple_mfd_driver);
190EARLY_DRIVER_MODULE(rk_otp, simplebus, rk_otp_driver, 0, 0,
191    BUS_PASS_BUS + BUS_PASS_ORDER_MIDDLE);
192