1/*- 2 * SPDX-License-Identifier: BSD-2-Clause 3 * 4 * Copyright (c) 2018 Emmanuel Vadot <manu@FreeBSD.org> 5 * Copyright (c) 2021 Soren Schmidt <sos@deepcore.dk> 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 * 28 */ 29 30#include <sys/param.h> 31#include <sys/systm.h> 32#include <sys/bus.h> 33 34#include <sys/kernel.h> 35#include <sys/module.h> 36#include <sys/proc.h> 37#include <sys/rman.h> 38#include <sys/lock.h> 39#include <sys/mutex.h> 40#include <sys/gpio.h> 41 42#include <machine/bus.h> 43#include <machine/resource.h> 44#include <machine/intr.h> 45 46#include <dev/gpio/gpiobusvar.h> 47#include <dev/ofw/ofw_bus.h> 48#include <dev/ofw/ofw_bus_subr.h> 49#include <dev/clk/clk.h> 50 51#include "gpio_if.h" 52#include "pic_if.h" 53 54#include "fdt_pinctrl_if.h" 55 56enum gpio_regs { 57 RK_GPIO_SWPORTA_DR = 1, /* Data register */ 58 RK_GPIO_SWPORTA_DDR, /* Data direction register */ 59 RK_GPIO_INTEN, /* Interrupt enable register */ 60 RK_GPIO_INTMASK, /* Interrupt mask register */ 61 RK_GPIO_INTTYPE_LEVEL, /* Interrupt level register */ 62 RK_GPIO_INTTYPE_BOTH, /* Both rise and falling edge */ 63 RK_GPIO_INT_POLARITY, /* Interrupt polarity register */ 64 RK_GPIO_INT_STATUS, /* Interrupt status register */ 65 RK_GPIO_INT_RAWSTATUS, /* Raw Interrupt status register */ 66 RK_GPIO_DEBOUNCE, /* Debounce enable register */ 67 RK_GPIO_PORTA_EOI, /* Clear interrupt register */ 68 RK_GPIO_EXT_PORTA, /* External port register */ 69 RK_GPIO_REGNUM 70}; 71 72#define RK_GPIO_LS_SYNC 0x60 /* Level sensitive syncronization enable register */ 73 74#define RK_GPIO_DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 75 GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN | GPIO_INTR_EDGE_BOTH | \ 76 GPIO_INTR_EDGE_RISING | GPIO_INTR_EDGE_FALLING | \ 77 GPIO_INTR_LEVEL_HIGH | GPIO_INTR_LEVEL_LOW) 78 79#define GPIO_FLAGS_PINCTRL GPIO_PIN_PULLUP | GPIO_PIN_PULLDOWN 80#define RK_GPIO_MAX_PINS 32 81 82struct pin_cached { 83 uint8_t is_gpio; 84 uint32_t flags; 85}; 86 87struct rk_pin_irqsrc { 88 struct intr_irqsrc isrc; 89 uint32_t irq; 90 uint32_t mode; 91}; 92 93struct rk_gpio_softc { 94 device_t sc_dev; 95 device_t sc_busdev; 96 struct mtx sc_mtx; 97 struct resource *sc_res[2]; 98 bus_space_tag_t sc_bst; 99 bus_space_handle_t sc_bsh; 100 clk_t clk; 101 device_t pinctrl; 102 uint32_t swporta; 103 uint32_t swporta_ddr; 104 uint32_t version; 105 struct pin_cached pin_cached[RK_GPIO_MAX_PINS]; 106 uint8_t regs[RK_GPIO_REGNUM]; 107 void *ihandle; 108 struct rk_pin_irqsrc isrcs[RK_GPIO_MAX_PINS]; 109}; 110 111static struct ofw_compat_data compat_data[] = { 112 {"rockchip,gpio-bank", 1}, 113 {NULL, 0} 114}; 115 116static struct resource_spec rk_gpio_spec[] = { 117 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 118 { SYS_RES_IRQ, 0, RF_ACTIVE }, 119 { -1, 0 } 120}; 121 122#define RK_GPIO_VERSION 0x78 123#define RK_GPIO_TYPE_V1 0x00000000 124#define RK_GPIO_TYPE_V2 0x01000c2b 125#define RK_GPIO_ISRC(sc, irq) (&(sc->isrcs[irq].isrc)) 126 127static int rk_gpio_detach(device_t dev); 128 129#define RK_GPIO_LOCK(_sc) mtx_lock_spin(&(_sc)->sc_mtx) 130#define RK_GPIO_UNLOCK(_sc) mtx_unlock_spin(&(_sc)->sc_mtx) 131#define RK_GPIO_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->sc_mtx, MA_OWNED) 132 133#define RK_GPIO_WRITE(_sc, _off, _val) \ 134 bus_space_write_4(_sc->sc_bst, _sc->sc_bsh, _off, _val) 135#define RK_GPIO_READ(_sc, _off) \ 136 bus_space_read_4(_sc->sc_bst, _sc->sc_bsh, _off) 137 138static int 139rk_gpio_read_bit(struct rk_gpio_softc *sc, int reg, int bit) 140{ 141 int offset = sc->regs[reg]; 142 uint32_t value; 143 144 if (sc->version == RK_GPIO_TYPE_V1) { 145 value = RK_GPIO_READ(sc, offset); 146 value >>= bit; 147 } else { 148 value = RK_GPIO_READ(sc, bit > 15 ? offset + 4 : offset); 149 value >>= (bit % 16); 150 } 151 return (value & 1); 152} 153 154static void 155rk_gpio_write_bit(struct rk_gpio_softc *sc, int reg, int bit, int data) 156{ 157 int offset = sc->regs[reg]; 158 uint32_t value; 159 160 if (sc->version == RK_GPIO_TYPE_V1) { 161 value = RK_GPIO_READ(sc, offset); 162 if (data) 163 value |= (1 << bit); 164 else 165 value &= ~(1 << bit); 166 RK_GPIO_WRITE(sc, offset, value); 167 } else { 168 if (data) 169 value = (1 << (bit % 16)); 170 else 171 value = 0; 172 value |= (1 << ((bit % 16) + 16)); 173 RK_GPIO_WRITE(sc, bit > 15 ? offset + 4 : offset, value); 174 } 175} 176 177static uint32_t 178rk_gpio_read_4(struct rk_gpio_softc *sc, int reg) 179{ 180 int offset = sc->regs[reg]; 181 uint32_t value; 182 183 if (sc->version == RK_GPIO_TYPE_V1) 184 value = RK_GPIO_READ(sc, offset); 185 else 186 value = (RK_GPIO_READ(sc, offset) & 0xffff) | 187 (RK_GPIO_READ(sc, offset + 4) << 16); 188 return (value); 189} 190 191static void 192rk_gpio_write_4(struct rk_gpio_softc *sc, int reg, uint32_t value) 193{ 194 int offset = sc->regs[reg]; 195 196 if (sc->version == RK_GPIO_TYPE_V1) 197 RK_GPIO_WRITE(sc, offset, value); 198 else { 199 RK_GPIO_WRITE(sc, offset, (value & 0xffff) | 0xffff0000); 200 RK_GPIO_WRITE(sc, offset + 4, (value >> 16) | 0xffff0000); 201 } 202} 203 204static int 205rk_gpio_intr(void *arg) 206{ 207 struct rk_gpio_softc *sc = (struct rk_gpio_softc *)arg; 208 struct trapframe *tf = curthread->td_intr_frame; 209 uint32_t status; 210 211 RK_GPIO_LOCK(sc); 212 status = rk_gpio_read_4(sc, RK_GPIO_INT_STATUS); 213 rk_gpio_write_4(sc, RK_GPIO_PORTA_EOI, status); 214 RK_GPIO_UNLOCK(sc); 215 216 while (status) { 217 int pin = ffs(status) - 1; 218 219 status &= ~(1 << pin); 220 if (intr_isrc_dispatch(RK_GPIO_ISRC(sc, pin), tf)) { 221 device_printf(sc->sc_dev, "Interrupt pin=%d unhandled\n", 222 pin); 223 continue; 224 } 225 226 if ((sc->version == RK_GPIO_TYPE_V1) && 227 (sc->isrcs[pin].mode & GPIO_INTR_EDGE_BOTH)) { 228 RK_GPIO_LOCK(sc); 229 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 230 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 231 (1 << pin), 0); 232 else 233 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 234 (1 << pin), 1); 235 RK_GPIO_UNLOCK(sc); 236 } 237 } 238 return (FILTER_HANDLED); 239} 240 241static int 242rk_gpio_probe(device_t dev) 243{ 244 245 if (!ofw_bus_status_okay(dev)) 246 return (ENXIO); 247 248 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0) 249 return (ENXIO); 250 251 device_set_desc(dev, "RockChip GPIO Bank controller"); 252 return (BUS_PROBE_DEFAULT); 253} 254 255static int 256rk_gpio_attach(device_t dev) 257{ 258 struct rk_gpio_softc *sc; 259 phandle_t parent_node, node; 260 int err, i; 261 262 sc = device_get_softc(dev); 263 sc->sc_dev = dev; 264 sc->pinctrl = device_get_parent(dev); 265 parent_node = ofw_bus_get_node(sc->pinctrl); 266 267 node = ofw_bus_get_node(sc->sc_dev); 268 if (!OF_hasprop(node, "gpio-controller")) 269 return (ENXIO); 270 271 mtx_init(&sc->sc_mtx, "rk gpio", "gpio", MTX_SPIN); 272 273 if (bus_alloc_resources(dev, rk_gpio_spec, sc->sc_res)) { 274 device_printf(dev, "could not allocate resources\n"); 275 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 276 mtx_destroy(&sc->sc_mtx); 277 return (ENXIO); 278 } 279 280 sc->sc_bst = rman_get_bustag(sc->sc_res[0]); 281 sc->sc_bsh = rman_get_bushandle(sc->sc_res[0]); 282 283 if (clk_get_by_ofw_index(dev, 0, 0, &sc->clk) != 0) { 284 device_printf(dev, "Cannot get clock\n"); 285 rk_gpio_detach(dev); 286 return (ENXIO); 287 } 288 err = clk_enable(sc->clk); 289 if (err != 0) { 290 device_printf(dev, "Could not enable clock %s\n", 291 clk_get_name(sc->clk)); 292 rk_gpio_detach(dev); 293 return (ENXIO); 294 } 295 296 if ((err = bus_setup_intr(dev, sc->sc_res[1], 297 INTR_TYPE_MISC | INTR_MPSAFE, rk_gpio_intr, NULL, 298 sc, &sc->ihandle))) { 299 device_printf(dev, "Can not setup IRQ\n"); 300 rk_gpio_detach(dev); 301 return (ENXIO); 302 } 303 304 /* 305 * RK3568 has GPIO_VER_ID register, however both 306 * RK3328 and RK3399 doesn't have. So choose the 307 * version based on parent's compat string. 308 */ 309 if (ofw_bus_node_is_compatible(parent_node, "rockchip,rk3568-pinctrl")) 310 sc->version = RK_GPIO_TYPE_V2; 311 else 312 sc->version = RK_GPIO_TYPE_V1; 313 314 switch (sc->version) { 315 case RK_GPIO_TYPE_V1: 316 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 317 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x04; 318 sc->regs[RK_GPIO_INTEN] = 0x30; 319 sc->regs[RK_GPIO_INTMASK] = 0x34; 320 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x38; 321 sc->regs[RK_GPIO_INT_POLARITY] = 0x3c; 322 sc->regs[RK_GPIO_INT_STATUS] = 0x40; 323 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x44; 324 sc->regs[RK_GPIO_DEBOUNCE] = 0x48; 325 sc->regs[RK_GPIO_PORTA_EOI] = 0x4c; 326 sc->regs[RK_GPIO_EXT_PORTA] = 0x50; 327 break; 328 case RK_GPIO_TYPE_V2: 329 sc->regs[RK_GPIO_SWPORTA_DR] = 0x00; 330 sc->regs[RK_GPIO_SWPORTA_DDR] = 0x08; 331 sc->regs[RK_GPIO_INTEN] = 0x10; 332 sc->regs[RK_GPIO_INTMASK] = 0x18; 333 sc->regs[RK_GPIO_INTTYPE_LEVEL] = 0x20; 334 sc->regs[RK_GPIO_INTTYPE_BOTH] = 0x30; 335 sc->regs[RK_GPIO_INT_POLARITY] = 0x28; 336 sc->regs[RK_GPIO_INT_STATUS] = 0x50; 337 sc->regs[RK_GPIO_INT_RAWSTATUS] = 0x58; 338 sc->regs[RK_GPIO_DEBOUNCE] = 0x38; 339 sc->regs[RK_GPIO_PORTA_EOI] = 0x60; 340 sc->regs[RK_GPIO_EXT_PORTA] = 0x70; 341 break; 342 default: 343 device_printf(dev, "Unknown gpio version %08x\n", sc->version); 344 rk_gpio_detach(dev); 345 return (ENXIO); 346 } 347 348 for (i = 0; i < RK_GPIO_MAX_PINS; i++) { 349 sc->isrcs[i].irq = i; 350 sc->isrcs[i].mode = GPIO_INTR_CONFORM; 351 if ((err = intr_isrc_register(RK_GPIO_ISRC(sc, i), 352 dev, 0, "%s", device_get_nameunit(dev)))) { 353 device_printf(dev, "Can not register isrc %d\n", err); 354 rk_gpio_detach(dev); 355 return (ENXIO); 356 } 357 } 358 359 if (intr_pic_register(dev, OF_xref_from_node(node)) == NULL) { 360 device_printf(dev, "Can not register pic\n"); 361 rk_gpio_detach(dev); 362 return (ENXIO); 363 } 364 365 sc->sc_busdev = gpiobus_attach_bus(dev); 366 if (sc->sc_busdev == NULL) { 367 rk_gpio_detach(dev); 368 return (ENXIO); 369 } 370 371 /* Set the cached value to unknown */ 372 for (i = 0; i < RK_GPIO_MAX_PINS; i++) 373 sc->pin_cached[i].is_gpio = 2; 374 375 RK_GPIO_LOCK(sc); 376 sc->swporta = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 377 sc->swporta_ddr = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 378 RK_GPIO_UNLOCK(sc); 379 380 return (0); 381} 382 383static int 384rk_gpio_detach(device_t dev) 385{ 386 struct rk_gpio_softc *sc; 387 388 sc = device_get_softc(dev); 389 390 if (sc->sc_busdev) 391 gpiobus_detach_bus(dev); 392 bus_release_resources(dev, rk_gpio_spec, sc->sc_res); 393 mtx_destroy(&sc->sc_mtx); 394 clk_disable(sc->clk); 395 396 return(0); 397} 398 399static device_t 400rk_gpio_get_bus(device_t dev) 401{ 402 struct rk_gpio_softc *sc; 403 404 sc = device_get_softc(dev); 405 406 return (sc->sc_busdev); 407} 408 409static int 410rk_gpio_pin_max(device_t dev, int *maxpin) 411{ 412 413 /* Each bank have always 32 pins */ 414 /* XXX not true*/ 415 *maxpin = 31; 416 return (0); 417} 418 419static int 420rk_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 421{ 422 struct rk_gpio_softc *sc; 423 uint32_t bank; 424 425 sc = device_get_softc(dev); 426 427 if (pin >= 32) 428 return (EINVAL); 429 430 bank = pin / 8; 431 pin = pin - (bank * 8); 432 RK_GPIO_LOCK(sc); 433 snprintf(name, GPIOMAXNAME, "P%c%d", bank + 'A', pin); 434 RK_GPIO_UNLOCK(sc); 435 436 return (0); 437} 438 439static int 440rk_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 441{ 442 struct rk_gpio_softc *sc; 443 int rv; 444 445 sc = device_get_softc(dev); 446 447 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 448 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 449 if (rv != 0) 450 return (rv); 451 if (sc->pin_cached[pin].is_gpio == 0) 452 return (EINVAL); 453 } 454 *flags = 0; 455 rv = FDT_PINCTRL_GET_FLAGS(sc->pinctrl, dev, pin, flags); 456 if (rv != 0) 457 return (rv); 458 sc->pin_cached[pin].flags = *flags; 459 460 if (sc->swporta_ddr & (1 << pin)) 461 *flags |= GPIO_PIN_OUTPUT; 462 else 463 *flags |= GPIO_PIN_INPUT; 464 465 return (0); 466} 467 468static int 469rk_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 470{ 471 472 if (pin >= RK_GPIO_MAX_PINS) 473 return EINVAL; 474 475 *caps = RK_GPIO_DEFAULT_CAPS; 476 return (0); 477} 478 479static int 480rk_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 481{ 482 struct rk_gpio_softc *sc; 483 int rv; 484 485 sc = device_get_softc(dev); 486 487 if (pin >= RK_GPIO_MAX_PINS) 488 return (EINVAL); 489 490 if (__predict_false(sc->pin_cached[pin].is_gpio != 1)) { 491 rv = FDT_PINCTRL_IS_GPIO(sc->pinctrl, dev, pin, (bool *)&sc->pin_cached[pin].is_gpio); 492 if (rv != 0) 493 return (rv); 494 if (sc->pin_cached[pin].is_gpio == 0) 495 return (EINVAL); 496 } 497 498 if (__predict_false((flags & GPIO_PIN_INPUT) && ((flags & GPIO_FLAGS_PINCTRL) != sc->pin_cached[pin].flags))) { 499 rv = FDT_PINCTRL_SET_FLAGS(sc->pinctrl, dev, pin, flags); 500 sc->pin_cached[pin].flags = flags & GPIO_FLAGS_PINCTRL; 501 if (rv != 0) 502 return (rv); 503 } 504 505 RK_GPIO_LOCK(sc); 506 if (flags & GPIO_PIN_INPUT) 507 sc->swporta_ddr &= ~(1 << pin); 508 else if (flags & GPIO_PIN_OUTPUT) 509 sc->swporta_ddr |= (1 << pin); 510 511 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, sc->swporta_ddr); 512 RK_GPIO_UNLOCK(sc); 513 514 return (0); 515} 516 517static int 518rk_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 519{ 520 struct rk_gpio_softc *sc; 521 522 sc = device_get_softc(dev); 523 524 if (pin >= RK_GPIO_MAX_PINS) 525 return (EINVAL); 526 527 RK_GPIO_LOCK(sc); 528 *val = rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin); 529 RK_GPIO_UNLOCK(sc); 530 531 return (0); 532} 533 534static int 535rk_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 536{ 537 struct rk_gpio_softc *sc; 538 539 sc = device_get_softc(dev); 540 541 if (pin >= RK_GPIO_MAX_PINS) 542 return (EINVAL); 543 544 RK_GPIO_LOCK(sc); 545 if (value) 546 sc->swporta |= (1 << pin); 547 else 548 sc->swporta &= ~(1 << pin); 549 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 550 RK_GPIO_UNLOCK(sc); 551 552 return (0); 553} 554 555static int 556rk_gpio_pin_toggle(device_t dev, uint32_t pin) 557{ 558 struct rk_gpio_softc *sc; 559 560 sc = device_get_softc(dev); 561 562 if (pin >= RK_GPIO_MAX_PINS) 563 return (EINVAL); 564 565 RK_GPIO_LOCK(sc); 566 if (sc->swporta & (1 << pin)) 567 sc->swporta &= ~(1 << pin); 568 else 569 sc->swporta |= (1 << pin); 570 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, sc->swporta); 571 RK_GPIO_UNLOCK(sc); 572 573 return (0); 574} 575 576static int 577rk_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 578 uint32_t change_pins, uint32_t *orig_pins) 579{ 580 struct rk_gpio_softc *sc; 581 uint32_t reg; 582 583 sc = device_get_softc(dev); 584 585 RK_GPIO_LOCK(sc); 586 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DR); 587 if (orig_pins) 588 *orig_pins = reg; 589 sc->swporta = reg; 590 591 if ((clear_pins | change_pins) != 0) { 592 reg = (reg & ~clear_pins) ^ change_pins; 593 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DR, reg); 594 } 595 RK_GPIO_UNLOCK(sc); 596 597 return (0); 598} 599 600static int 601rk_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 602 uint32_t *pin_flags) 603{ 604 struct rk_gpio_softc *sc; 605 uint32_t reg, set, mask, flags; 606 int i; 607 608 sc = device_get_softc(dev); 609 610 if (first_pin != 0 || num_pins > 32) 611 return (EINVAL); 612 613 set = 0; 614 mask = 0; 615 for (i = 0; i < num_pins; i++) { 616 mask = (mask << 1) | 1; 617 flags = pin_flags[i]; 618 if (flags & GPIO_PIN_INPUT) { 619 set &= ~(1 << i); 620 } else if (flags & GPIO_PIN_OUTPUT) { 621 set |= (1 << i); 622 } 623 } 624 625 RK_GPIO_LOCK(sc); 626 reg = rk_gpio_read_4(sc, RK_GPIO_SWPORTA_DDR); 627 reg &= ~mask; 628 reg |= set; 629 rk_gpio_write_4(sc, RK_GPIO_SWPORTA_DDR, reg); 630 sc->swporta_ddr = reg; 631 RK_GPIO_UNLOCK(sc); 632 633 return (0); 634} 635 636static int 637rk_gpio_map_gpios(device_t bus, phandle_t dev, phandle_t gparent, int gcells, 638 pcell_t *gpios, uint32_t *pin, uint32_t *flags) 639{ 640 641 /* The gpios are mapped as <pin flags> */ 642 *pin = gpios[0]; 643 *flags = gpios[1]; 644 return (0); 645} 646 647static phandle_t 648rk_gpio_get_node(device_t bus, device_t dev) 649{ 650 651 /* We only have one child, the GPIO bus, which needs our own node. */ 652 return (ofw_bus_get_node(bus)); 653} 654 655static int 656rk_pic_map_intr(device_t dev, struct intr_map_data *data, 657 struct intr_irqsrc **isrcp) 658{ 659 struct rk_gpio_softc *sc = device_get_softc(dev); 660 struct intr_map_data_gpio *gdata; 661 uint32_t irq; 662 663 if (data->type != INTR_MAP_DATA_GPIO) { 664 device_printf(dev, "Wrong type\n"); 665 return (ENOTSUP); 666 } 667 gdata = (struct intr_map_data_gpio *)data; 668 irq = gdata->gpio_pin_num; 669 if (irq >= RK_GPIO_MAX_PINS) { 670 device_printf(dev, "Invalid interrupt %u\n", irq); 671 return (EINVAL); 672 } 673 *isrcp = RK_GPIO_ISRC(sc, irq); 674 return (0); 675} 676 677static int 678rk_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 679 struct resource *res, struct intr_map_data *data) 680{ 681 struct rk_gpio_softc *sc = device_get_softc(dev); 682 struct rk_pin_irqsrc *rkisrc = (struct rk_pin_irqsrc *)isrc; 683 struct intr_map_data_gpio *gdata; 684 uint32_t mode; 685 uint8_t pin; 686 687 if (!data) { 688 device_printf(dev, "No map data\n"); 689 return (ENOTSUP); 690 } 691 gdata = (struct intr_map_data_gpio *)data; 692 mode = gdata->gpio_intr_mode; 693 pin = gdata->gpio_pin_num; 694 695 if (rkisrc->irq != gdata->gpio_pin_num) { 696 device_printf(dev, "Interrupts don't match\n"); 697 return (EINVAL); 698 } 699 700 if (isrc->isrc_handlers != 0) { 701 device_printf(dev, "Handler already attached\n"); 702 return (rkisrc->mode == mode ? 0 : EINVAL); 703 } 704 rkisrc->mode = mode; 705 706 RK_GPIO_LOCK(sc); 707 708 switch (mode & GPIO_INTR_MASK) { 709 case GPIO_INTR_EDGE_RISING: 710 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 711 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 712 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 713 break; 714 case GPIO_INTR_EDGE_FALLING: 715 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 716 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 717 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 718 break; 719 case GPIO_INTR_EDGE_BOTH: 720 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 721 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 1); 722 if (sc->version == RK_GPIO_TYPE_V1) { 723 if (rk_gpio_read_bit(sc, RK_GPIO_EXT_PORTA, pin)) 724 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 725 pin, 0); 726 else 727 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, 728 pin, 1); 729 } else 730 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_BOTH, pin, 1); 731 break; 732 case GPIO_INTR_LEVEL_HIGH: 733 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 734 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 735 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 1); 736 break; 737 case GPIO_INTR_LEVEL_LOW: 738 rk_gpio_write_bit(sc, RK_GPIO_SWPORTA_DDR, pin, 0); 739 rk_gpio_write_bit(sc, RK_GPIO_INTTYPE_LEVEL, pin, 0); 740 rk_gpio_write_bit(sc, RK_GPIO_INT_POLARITY, pin, 0); 741 break; 742 default: 743 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 1); 744 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 0); 745 RK_GPIO_UNLOCK(sc); 746 return (EINVAL); 747 } 748 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, pin, 1); 749 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, pin, 0); 750 rk_gpio_write_bit(sc, RK_GPIO_INTEN, pin, 1); 751 RK_GPIO_UNLOCK(sc); 752 753 return (0); 754} 755 756static int 757rk_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 758 struct resource *res, struct intr_map_data *data) 759{ 760 struct rk_gpio_softc *sc = device_get_softc(dev); 761 struct rk_pin_irqsrc *irqsrc; 762 763 irqsrc = (struct rk_pin_irqsrc *)isrc; 764 765 if (isrc->isrc_handlers == 0) { 766 irqsrc->mode = GPIO_INTR_CONFORM; 767 RK_GPIO_LOCK(sc); 768 rk_gpio_write_bit(sc, RK_GPIO_INTEN, irqsrc->irq, 0); 769 rk_gpio_write_bit(sc, RK_GPIO_INTMASK, irqsrc->irq, 0); 770 rk_gpio_write_bit(sc, RK_GPIO_DEBOUNCE, irqsrc->irq, 0); 771 RK_GPIO_UNLOCK(sc); 772 } 773 return (0); 774} 775 776static device_method_t rk_gpio_methods[] = { 777 /* Device interface */ 778 DEVMETHOD(device_probe, rk_gpio_probe), 779 DEVMETHOD(device_attach, rk_gpio_attach), 780 DEVMETHOD(device_detach, rk_gpio_detach), 781 782 /* GPIO protocol */ 783 DEVMETHOD(gpio_get_bus, rk_gpio_get_bus), 784 DEVMETHOD(gpio_pin_max, rk_gpio_pin_max), 785 DEVMETHOD(gpio_pin_getname, rk_gpio_pin_getname), 786 DEVMETHOD(gpio_pin_getflags, rk_gpio_pin_getflags), 787 DEVMETHOD(gpio_pin_getcaps, rk_gpio_pin_getcaps), 788 DEVMETHOD(gpio_pin_setflags, rk_gpio_pin_setflags), 789 DEVMETHOD(gpio_pin_get, rk_gpio_pin_get), 790 DEVMETHOD(gpio_pin_set, rk_gpio_pin_set), 791 DEVMETHOD(gpio_pin_toggle, rk_gpio_pin_toggle), 792 DEVMETHOD(gpio_pin_access_32, rk_gpio_pin_access_32), 793 DEVMETHOD(gpio_pin_config_32, rk_gpio_pin_config_32), 794 DEVMETHOD(gpio_map_gpios, rk_gpio_map_gpios), 795 796 /* Interrupt controller interface */ 797 DEVMETHOD(pic_map_intr, rk_pic_map_intr), 798 DEVMETHOD(pic_setup_intr, rk_pic_setup_intr), 799 DEVMETHOD(pic_teardown_intr, rk_pic_teardown_intr), 800 801 /* ofw_bus interface */ 802 DEVMETHOD(ofw_bus_get_node, rk_gpio_get_node), 803 804 DEVMETHOD_END 805}; 806 807static driver_t rk_gpio_driver = { 808 "gpio", 809 rk_gpio_methods, 810 sizeof(struct rk_gpio_softc), 811}; 812 813/* 814 * GPIO driver is always a child of rk_pinctrl driver and should be probed 815 * and attached within rk_pinctrl_attach function. Due to this, bus pass order 816 * must be same as bus pass order of rk_pinctrl driver. 817 */ 818EARLY_DRIVER_MODULE(rk_gpio, simplebus, rk_gpio_driver, 0, 0, 819 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_MIDDLE); 820