1/*- 2 * Copyright (c) 2018-2020 Ruslan Bukin <br@bsdpad.com> 3 * All rights reserved. 4 * 5 * This software was developed by SRI International and the University of 6 * Cambridge Computer Laboratory under DARPA/AFRL contract FA8750-10-C-0237 7 * ("CTSRD"), as part of the DARPA CRASH research programme. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 19 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 20 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 21 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 22 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 23 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 24 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 25 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 26 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 27 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 28 * SUCH DAMAGE. 29 */ 30 31#ifndef _ARM64_CORESIGHT_CORESIGHT_H_ 32#define _ARM64_CORESIGHT_CORESIGHT_H_ 33 34#include "opt_acpi.h" 35#include "opt_platform.h" 36 37#include <sys/bus.h> 38#include <sys/malloc.h> 39 40#ifdef FDT 41#include <dev/ofw/openfirm.h> 42#endif 43 44#ifdef DEV_ACPI 45#include <contrib/dev/acpica/include/acpi.h> 46#include <dev/acpica/acpivar.h> 47#endif 48 49#define CORESIGHT_ITCTRL 0xf00 50#define CORESIGHT_CLAIMSET 0xfa0 51#define CORESIGHT_CLAIMCLR 0xfa4 52#define CORESIGHT_LAR 0xfb0 53#define CORESIGHT_UNLOCK 0xc5acce55 54#define CORESIGHT_LSR 0xfb4 55#define CORESIGHT_AUTHSTATUS 0xfb8 56#define CORESIGHT_DEVID 0xfc8 57#define CORESIGHT_DEVTYPE 0xfcc 58 59enum cs_dev_type { 60 CORESIGHT_ETMV4, 61 CORESIGHT_TMC, 62 CORESIGHT_DYNAMIC_REPLICATOR, 63 CORESIGHT_FUNNEL, 64 CORESIGHT_CPU_DEBUG, 65}; 66 67enum cs_bus_type { 68 CORESIGHT_BUS_ACPI, 69 CORESIGHT_BUS_FDT, 70}; 71 72struct coresight_device { 73 TAILQ_ENTRY(coresight_device) link; 74 device_t dev; 75 enum cs_dev_type dev_type; 76 struct coresight_platform_data *pdata; 77}; 78 79struct endpoint { 80 TAILQ_ENTRY(endpoint) link; 81#ifdef FDT 82 phandle_t my_node; 83 phandle_t their_node; 84 phandle_t dev_node; 85#endif 86#ifdef DEV_ACPI 87 ACPI_HANDLE their_handle; 88 ACPI_HANDLE my_handle; 89#endif 90 boolean_t input; 91 int reg; 92 struct coresight_device *cs_dev; 93 LIST_ENTRY(endpoint) endplink; 94}; 95 96struct coresight_platform_data { 97 int cpu; 98 int in_ports; 99 int out_ports; 100 struct mtx mtx_lock; 101 TAILQ_HEAD(endpoint_list, endpoint) endpoints; 102 enum cs_bus_type bus_type; 103}; 104 105struct coresight_desc { 106 struct coresight_platform_data *pdata; 107 device_t dev; 108 enum cs_dev_type dev_type; 109}; 110 111TAILQ_HEAD(coresight_device_list, coresight_device); 112 113#define ETM_N_COMPRATOR 16 114 115struct etm_state { 116 uint32_t trace_id; 117}; 118 119struct etr_state { 120 boolean_t started; 121 uint32_t cycle; 122 uint32_t offset; 123 uint32_t low; 124 uint32_t high; 125 uint32_t bufsize; 126 uint32_t flags; 127#define ETR_FLAG_ALLOCATE (1 << 0) 128#define ETR_FLAG_RELEASE (1 << 1) 129}; 130 131struct coresight_event { 132 LIST_HEAD(, endpoint) endplist; 133 134 uint64_t addr[ETM_N_COMPRATOR]; 135 uint32_t naddr; 136 uint8_t excp_level; 137 enum cs_dev_type src; 138 enum cs_dev_type sink; 139 140 struct etr_state etr; 141 struct etm_state etm; 142}; 143 144struct etm_config { 145 uint64_t addr[ETM_N_COMPRATOR]; 146 uint32_t naddr; 147 uint8_t excp_level; 148}; 149 150static MALLOC_DEFINE(M_CORESIGHT, "coresight", "ARM Coresight"); 151 152struct coresight_platform_data *coresight_fdt_get_platform_data(device_t dev); 153struct coresight_platform_data *coresight_acpi_get_platform_data(device_t dev); 154struct endpoint * coresight_get_output_endpoint(struct coresight_platform_data *pdata); 155struct coresight_device * coresight_get_output_device(struct endpoint *endp, struct endpoint **); 156int coresight_register(struct coresight_desc *desc); 157int coresight_init_event(int cpu, struct coresight_event *event); 158void coresight_enable(int cpu, struct coresight_event *event); 159void coresight_disable(int cpu, struct coresight_event *event); 160void coresight_read(int cpu, struct coresight_event *event); 161 162#endif /* !_ARM64_CORESIGHT_CORESIGHT_H_ */ 163