1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28/* 29 * UART driver for Tegra SoCs. 30 */ 31#include "opt_platform.h" 32 33#include <sys/param.h> 34#include <sys/systm.h> 35#include <sys/bus.h> 36#include <sys/conf.h> 37#include <sys/kernel.h> 38#include <sys/module.h> 39#include <sys/sysctl.h> 40#include <machine/bus.h> 41 42#include <dev/clk/clk.h> 43#include <dev/hwreset/hwreset.h> 44#include <dev/ofw/ofw_bus.h> 45#include <dev/ofw/ofw_bus_subr.h> 46#include <dev/uart/uart.h> 47#include <dev/uart/uart_cpu.h> 48#include <dev/uart/uart_cpu_fdt.h> 49#include <dev/uart/uart_bus.h> 50#include <dev/uart/uart_dev_ns8250.h> 51#include <dev/ic/ns16550.h> 52 53#include "uart_if.h" 54 55/* 56 * High-level UART interface. 57 */ 58struct tegra_softc { 59 struct ns8250_softc ns8250_base; 60 clk_t clk; 61 hwreset_t reset; 62}; 63 64/* 65 * UART class interface. 66 */ 67static int 68tegra_uart_attach(struct uart_softc *sc) 69{ 70 int rv; 71 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 72 struct uart_bas *bas = &sc->sc_bas; 73 74 rv = ns8250_bus_attach(sc); 75 if (rv != 0) 76 return (rv); 77 78 ns8250->ier_rxbits = 0x1d; 79 ns8250->ier_mask = 0xc0; 80 ns8250->ier = uart_getreg(bas, REG_IER) & ns8250->ier_mask; 81 ns8250->ier |= ns8250->ier_rxbits; 82 uart_setreg(bas, REG_IER, ns8250->ier); 83 uart_barrier(bas); 84 return (0); 85} 86 87static void 88tegra_uart_grab(struct uart_softc *sc) 89{ 90 struct uart_bas *bas = &sc->sc_bas; 91 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 92 u_char ier; 93 94 /* 95 * turn off all interrupts to enter polling mode. Leave the 96 * saved mask alone. We'll restore whatever it was in ungrab. 97 * All pending interrupt signals are reset when IER is set to 0. 98 */ 99 uart_lock(sc->sc_hwmtx); 100 ier = uart_getreg(bas, REG_IER); 101 uart_setreg(bas, REG_IER, ier & ns8250->ier_mask); 102 103 while ((uart_getreg(bas, REG_LSR) & LSR_TEMT) == 0) 104 ; 105 106 uart_setreg(bas, REG_FCR, 0); 107 uart_barrier(bas); 108 uart_unlock(sc->sc_hwmtx); 109} 110 111static void 112tegra_uart_ungrab(struct uart_softc *sc) 113{ 114 struct ns8250_softc *ns8250 = (struct ns8250_softc*)sc; 115 struct uart_bas *bas = &sc->sc_bas; 116 117 /* 118 * Restore previous interrupt mask 119 */ 120 uart_lock(sc->sc_hwmtx); 121 uart_setreg(bas, REG_FCR, ns8250->fcr); 122 uart_setreg(bas, REG_IER, ns8250->ier); 123 uart_barrier(bas); 124 uart_unlock(sc->sc_hwmtx); 125} 126 127static kobj_method_t tegra_methods[] = { 128 KOBJMETHOD(uart_probe, ns8250_bus_probe), 129 KOBJMETHOD(uart_attach, tegra_uart_attach), 130 KOBJMETHOD(uart_detach, ns8250_bus_detach), 131 KOBJMETHOD(uart_flush, ns8250_bus_flush), 132 KOBJMETHOD(uart_getsig, ns8250_bus_getsig), 133 KOBJMETHOD(uart_ioctl, ns8250_bus_ioctl), 134 KOBJMETHOD(uart_ipend, ns8250_bus_ipend), 135 KOBJMETHOD(uart_param, ns8250_bus_param), 136 KOBJMETHOD(uart_receive, ns8250_bus_receive), 137 KOBJMETHOD(uart_setsig, ns8250_bus_setsig), 138 KOBJMETHOD(uart_transmit, ns8250_bus_transmit), 139 KOBJMETHOD(uart_txbusy, ns8250_bus_txbusy), 140 KOBJMETHOD(uart_grab, tegra_uart_grab), 141 KOBJMETHOD(uart_ungrab, tegra_uart_ungrab), 142 KOBJMETHOD_END 143}; 144 145static struct uart_class tegra_uart_class = { 146 "tegra class", 147 tegra_methods, 148 sizeof(struct tegra_softc), 149 .uc_ops = &uart_ns8250_ops, 150 .uc_range = 8, 151 .uc_rclk = 0, 152}; 153 154/* Compatible devices. */ 155static struct ofw_compat_data compat_data[] = { 156 {"nvidia,tegra124-uart", (uintptr_t)&tegra_uart_class}, 157 {"nvidia,tegra210-uart", (uintptr_t)&tegra_uart_class}, 158 {NULL, (uintptr_t)NULL}, 159}; 160 161UART_FDT_CLASS(compat_data); 162 163/* 164 * UART Driver interface. 165 */ 166static int 167uart_fdt_get_shift1(phandle_t node) 168{ 169 pcell_t shift; 170 171 if ((OF_getencprop(node, "reg-shift", &shift, sizeof(shift))) <= 0) 172 shift = 2; 173 return ((int)shift); 174} 175 176static int 177tegra_uart_probe(device_t dev) 178{ 179 struct tegra_softc *sc; 180 phandle_t node; 181 uint64_t freq; 182 int shift; 183 int rv; 184 const struct ofw_compat_data *cd; 185 186 sc = device_get_softc(dev); 187 if (!ofw_bus_status_okay(dev)) 188 return (ENXIO); 189 cd = ofw_bus_search_compatible(dev, compat_data); 190 if (cd->ocd_data == 0) 191 return (ENXIO); 192 sc->ns8250_base.base.sc_class = (struct uart_class *)cd->ocd_data; 193 rv = hwreset_get_by_ofw_name(dev, 0, "serial", &sc->reset); 194 if (rv != 0) { 195 device_printf(dev, "Cannot get 'serial' reset\n"); 196 return (ENXIO); 197 } 198 rv = hwreset_deassert(sc->reset); 199 if (rv != 0) { 200 device_printf(dev, "Cannot unreset 'serial' reset\n"); 201 return (ENXIO); 202 } 203 node = ofw_bus_get_node(dev); 204 shift = uart_fdt_get_shift1(node); 205 rv = clk_get_by_ofw_index(dev, 0, 0, &sc->clk); 206 if (rv != 0) { 207 device_printf(dev, "Cannot get UART clock: %d\n", rv); 208 return (ENXIO); 209 } 210 rv = clk_enable(sc->clk); 211 if (rv != 0) { 212 device_printf(dev, "Cannot enable UART clock: %d\n", rv); 213 return (ENXIO); 214 } 215 rv = clk_get_freq(sc->clk, &freq); 216 if (rv != 0) { 217 device_printf(dev, "Cannot enable UART clock: %d\n", rv); 218 return (ENXIO); 219 } 220 return (uart_bus_probe(dev, shift, 0, (int)freq, 0, 0, 0)); 221} 222 223static int 224tegra_uart_detach(device_t dev) 225{ 226 struct tegra_softc *sc; 227 228 sc = device_get_softc(dev); 229 if (sc->clk != NULL) { 230 clk_release(sc->clk); 231 } 232 233 return (uart_bus_detach(dev)); 234} 235 236static device_method_t tegra_uart_bus_methods[] = { 237 /* Device interface */ 238 DEVMETHOD(device_probe, tegra_uart_probe), 239 DEVMETHOD(device_attach, uart_bus_attach), 240 DEVMETHOD(device_detach, tegra_uart_detach), 241 DEVMETHOD_END 242}; 243 244static driver_t tegra_uart_driver = { 245 uart_driver_name, 246 tegra_uart_bus_methods, 247 sizeof(struct tegra_softc), 248}; 249 250DRIVER_MODULE(tegra_uart, simplebus, tegra_uart_driver, 0, 0); 251