166129Swpaul/*- 266129Swpaul * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 366129Swpaul * All rights reserved. 466129Swpaul * 566129Swpaul * Redistribution and use in source and binary forms, with or without 666129Swpaul * modification, are permitted provided that the following conditions 766129Swpaul * are met: 866129Swpaul * 1. Redistributions of source code must retain the above copyright 966129Swpaul * notice, this list of conditions and the following disclaimer. 1066129Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1166129Swpaul * notice, this list of conditions and the following disclaimer in the 1266129Swpaul * documentation and/or other materials provided with the distribution. 1366129Swpaul * 1466129Swpaul * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1566129Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1666129Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1766129Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 1866129Swpaul * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1966129Swpaul * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2066129Swpaul * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2166129Swpaul * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2266129Swpaul * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2366129Swpaul * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2466129Swpaul * SUCH DAMAGE. 2566129Swpaul */ 2666129Swpaul 2766129Swpaul#ifndef _TEGRA_PMC_H_ 2866129Swpaul#define _TEGRA_PMC_H_ 2966129Swpaul 3066129Swpaulenum tegra_suspend_mode { 3166129Swpaul TEGRA_SUSPEND_NONE = 0, 3266129Swpaul TEGRA_SUSPEND_LP2, /* CPU voltage off */ 3366129Swpaul TEGRA_SUSPEND_LP1, /* CPU voltage off, DRAM self-refresh */ 34119418Sobrien TEGRA_SUSPEND_LP0, /* CPU + core voltage off, DRAM self-refresh */ 35119418Sobrien}; 36119418Sobrien 3766129Swpaul/* PARTIDs for powergate */ 3866129Swpaulenum tegra_powergate_id { 3966129Swpaul TEGRA_POWERGATE_CRAIL = 0, 4066129Swpaul TEGRA_POWERGATE_TD = 1, /* Tegra124 only */ 4166129Swpaul TEGRA_POWERGATE_VE = 2, 4266129Swpaul TEGRA_POWERGATE_PCX = 3, 4366129Swpaul TEGRA_POWERGATE_VDE = 4, /* Tegra124 only */ 4466129Swpaul TEGRA_POWERGATE_L2C = 5, /* Tegra124 only */ 4566129Swpaul TEGRA_POWERGATE_MPE = 6, 46113038Sobrien TEGRA_POWERGATE_HEG = 7, /* Tegra124 only */ 47113038Sobrien TEGRA_POWERGATE_SAX = 8, 48113038Sobrien TEGRA_POWERGATE_CE1 = 9, 4966129Swpaul TEGRA_POWERGATE_CE2 = 10, 5066129Swpaul TEGRA_POWERGATE_CE3 = 11, 5166129Swpaul TEGRA_POWERGATE_CELP = 12, /* Tegra124 only */ 5266129Swpaul /* */ 5366129Swpaul TEGRA_POWERGATE_CE0 = 14, 5466129Swpaul TEGRA_POWERGATE_C0NC = 15, 5566129Swpaul TEGRA_POWERGATE_C1NC = 16, 5666129Swpaul TEGRA_POWERGATE_SOR = 17, 5766129Swpaul TEGRA_POWERGATE_DIS = 18, 5866129Swpaul TEGRA_POWERGATE_DISB = 19, 5966129Swpaul TEGRA_POWERGATE_XUSBA = 20, 6066129Swpaul TEGRA_POWERGATE_XUSBB = 21, 6166129Swpaul TEGRA_POWERGATE_XUSBC = 22, 6266129Swpaul TEGRA_POWERGATE_VIC = 23, 63109514Sobrien TEGRA_POWERGATE_IRAM = 24, 6466129Swpaul TEGRA_POWERGATE_NVDEC = 25, /* Tegra210 only */ 6566129Swpaul TEGRA_POWERGATE_NVJPG = 26, /* Tegra210 only */ 6666129Swpaul TEGRA_POWERGATE_AUD = 27, /* Tegra210 only */ 67105135Salfred TEGRA_POWERGATE_DFD = 28, /* Tegra210 only */ 68105135Salfred TEGRA_POWERGATE_VE2 = 29, /* Tegra210 only */ 6966129Swpaul /* */ 7066129Swpaul TEGRA_POWERGATE_3D = 32 7166129Swpaul}; 7266129Swpaul 7366129Swpaul/* PARTIDs for power rails */ 7495722Sphkenum tegra_powerrail_id { 7566129Swpaul TEGRA_IO_RAIL_CSIA = 0, 7666129Swpaul TEGRA_IO_RAIL_CSIB = 1, 7766129Swpaul TEGRA_IO_RAIL_DSI = 2, 7866129Swpaul TEGRA_IO_RAIL_MIPI_BIAS = 3, 7966129Swpaul TEGRA_IO_RAIL_PEX_BIAS = 4, 8066129Swpaul TEGRA_IO_RAIL_PEX_CLK1 = 5, 8166129Swpaul TEGRA_IO_RAIL_PEX_CLK2 = 6, 8266129Swpaul TEGRA_IO_RAIL_USB0 = 9, 8366129Swpaul TEGRA_IO_RAIL_USB1 = 10, 8466129Swpaul TEGRA_IO_RAIL_USB2 = 11, 8566129Swpaul TEGRA_IO_RAIL_USB_BIAS = 12, 8666129Swpaul TEGRA_IO_RAIL_NAND = 13, 8766129Swpaul TEGRA_IO_RAIL_UART = 14, 8866129Swpaul TEGRA_IO_RAIL_BB = 15, 8992739Salfred TEGRA_IO_RAIL_AUDIO = 17, 9066129Swpaul TEGRA_IO_RAIL_HSIC = 19, 9166129Swpaul TEGRA_IO_RAIL_COMP = 22, 9266129Swpaul TEGRA_IO_RAIL_HDMI = 28, 9366129Swpaul TEGRA_IO_RAIL_PEX_CNTRL = 32, 9466129Swpaul TEGRA_IO_RAIL_SDMMC1 = 33, 9566129Swpaul TEGRA_IO_RAIL_SDMMC3 = 34, 9666129Swpaul TEGRA_IO_RAIL_SDMMC4 = 35, 9766129Swpaul TEGRA_IO_RAIL_CAM = 36, 9866129Swpaul TEGRA_IO_RAIL_RES = 37, 9966129Swpaul TEGRA_IO_RAIL_HV = 38, 10066129Swpaul TEGRA_IO_RAIL_DSIB = 39, 10166129Swpaul TEGRA_IO_RAIL_DSIC = 40, 10266129Swpaul TEGRA_IO_RAIL_DSID = 41, 10366129Swpaul TEGRA_IO_RAIL_CSIE = 44, 10466129Swpaul TEGRA_IO_RAIL_LVDS = 57, 10566129Swpaul TEGRA_IO_RAIL_SYS_DDC = 58, 10666129Swpaul}; 10766129Swpaul 10866129Swpaulint tegra_powergate_is_powered(enum tegra_powergate_id id); 10966129Swpaulint tegra_powergate_power_on(enum tegra_powergate_id id); 11066129Swpaulint tegra_powergate_power_off(enum tegra_powergate_id id); 11166129Swpaulint tegra_powergate_remove_clamping(enum tegra_powergate_id id); 11266129Swpaulint tegra_powergate_sequence_power_up(enum tegra_powergate_id id, 11366129Swpaul clk_t clk, hwreset_t rst); 11466129Swpaulint tegra_io_rail_power_on(int tegra_powerrail_id); 11566129Swpaulint tegra_io_rail_power_off(int tegra_powerrail_id); 11666129Swpaul 11766129Swpaul#endif /*_TEGRA_PMC_H_*/