1/*-
2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 */
26
27#ifndef _TEGRA_PMC_H_
28#define	_TEGRA_PMC_H_
29
30enum tegra_suspend_mode {
31      TEGRA_SUSPEND_NONE = 0,
32      TEGRA_SUSPEND_LP2, 	/* CPU voltage off */
33      TEGRA_SUSPEND_LP1, 	/* CPU voltage off, DRAM self-refresh */
34      TEGRA_SUSPEND_LP0, 	/* CPU + core voltage off, DRAM self-refresh */
35};
36
37/* PARTIDs for powergate */
38enum tegra_powergate_id {
39	TEGRA_POWERGATE_CRAIL	= 0,
40	TEGRA_POWERGATE_TD	= 1, /* Tegra124 only */
41	TEGRA_POWERGATE_VE	= 2,
42	TEGRA_POWERGATE_PCX	= 3,
43	TEGRA_POWERGATE_VDE	= 4, /* Tegra124 only */
44	TEGRA_POWERGATE_L2C	= 5, /* Tegra124 only */
45	TEGRA_POWERGATE_MPE	= 6,
46	TEGRA_POWERGATE_HEG	= 7, /* Tegra124 only */
47	TEGRA_POWERGATE_SAX	= 8,
48	TEGRA_POWERGATE_CE1	= 9,
49	TEGRA_POWERGATE_CE2	= 10,
50	TEGRA_POWERGATE_CE3	= 11,
51	TEGRA_POWERGATE_CELP	= 12, /* Tegra124 only */
52	/* */
53	TEGRA_POWERGATE_CE0	= 14,
54	TEGRA_POWERGATE_C0NC	= 15,
55	TEGRA_POWERGATE_C1NC	= 16,
56	TEGRA_POWERGATE_SOR	= 17,
57	TEGRA_POWERGATE_DIS	= 18,
58	TEGRA_POWERGATE_DISB	= 19,
59	TEGRA_POWERGATE_XUSBA	= 20,
60	TEGRA_POWERGATE_XUSBB	= 21,
61	TEGRA_POWERGATE_XUSBC	= 22,
62	TEGRA_POWERGATE_VIC	= 23,
63	TEGRA_POWERGATE_IRAM	= 24,
64	TEGRA_POWERGATE_NVDEC	= 25, /* Tegra210 only */
65	TEGRA_POWERGATE_NVJPG	= 26, /* Tegra210 only */
66	TEGRA_POWERGATE_AUD	= 27, /* Tegra210 only */
67	TEGRA_POWERGATE_DFD	= 28, /* Tegra210 only */
68	TEGRA_POWERGATE_VE2	= 29, /* Tegra210 only */
69	/* */
70	TEGRA_POWERGATE_3D	= 32
71};
72
73/* PARTIDs for power rails */
74enum tegra_powerrail_id {
75	TEGRA_IO_RAIL_CSIA	= 0,
76	TEGRA_IO_RAIL_CSIB	= 1,
77	TEGRA_IO_RAIL_DSI	= 2,
78	TEGRA_IO_RAIL_MIPI_BIAS	= 3,
79	TEGRA_IO_RAIL_PEX_BIAS	= 4,
80	TEGRA_IO_RAIL_PEX_CLK1	= 5,
81	TEGRA_IO_RAIL_PEX_CLK2	= 6,
82	TEGRA_IO_RAIL_USB0	= 9,
83	TEGRA_IO_RAIL_USB1	= 10,
84	TEGRA_IO_RAIL_USB2	= 11,
85	TEGRA_IO_RAIL_USB_BIAS	= 12,
86	TEGRA_IO_RAIL_NAND	= 13,
87	TEGRA_IO_RAIL_UART	= 14,
88	TEGRA_IO_RAIL_BB	= 15,
89	TEGRA_IO_RAIL_AUDIO	= 17,
90	TEGRA_IO_RAIL_HSIC	= 19,
91	TEGRA_IO_RAIL_COMP	= 22,
92	TEGRA_IO_RAIL_HDMI	= 28,
93	TEGRA_IO_RAIL_PEX_CNTRL	= 32,
94	TEGRA_IO_RAIL_SDMMC1	= 33,
95	TEGRA_IO_RAIL_SDMMC3	= 34,
96	TEGRA_IO_RAIL_SDMMC4	= 35,
97	TEGRA_IO_RAIL_CAM	= 36,
98	TEGRA_IO_RAIL_RES	= 37,
99	TEGRA_IO_RAIL_HV	= 38,
100	TEGRA_IO_RAIL_DSIB	= 39,
101	TEGRA_IO_RAIL_DSIC	= 40,
102	TEGRA_IO_RAIL_DSID	= 41,
103	TEGRA_IO_RAIL_CSIE	= 44,
104	TEGRA_IO_RAIL_LVDS	= 57,
105	TEGRA_IO_RAIL_SYS_DDC	= 58,
106};
107
108int tegra_powergate_is_powered(enum tegra_powergate_id id);
109int tegra_powergate_power_on(enum tegra_powergate_id id);
110int tegra_powergate_power_off(enum tegra_powergate_id id);
111int tegra_powergate_remove_clamping(enum tegra_powergate_id id);
112int tegra_powergate_sequence_power_up(enum tegra_powergate_id id,
113    clk_t clk, hwreset_t rst);
114int tegra_io_rail_power_on(int tegra_powerrail_id);
115int tegra_io_rail_power_off(int tegra_powerrail_id);
116
117#endif /*_TEGRA_PMC_H_*/