1/*- 2 * Copyright (c) 2016 Michal Meloun <mmel@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 */ 26 27#include <sys/cdefs.h> 28/* 29 * AHCI driver for Tegra SoCs. 30 */ 31#include <sys/param.h> 32#include <sys/module.h> 33#include <sys/systm.h> 34#include <sys/bus.h> 35#include <sys/conf.h> 36#include <sys/endian.h> 37#include <sys/kernel.h> 38#include <sys/lock.h> 39#include <sys/malloc.h> 40#include <sys/mutex.h> 41#include <sys/rman.h> 42 43#include <machine/bus.h> 44#include <machine/resource.h> 45 46#include <dev/ahci/ahci.h> 47#include <dev/clk/clk.h> 48#include <dev/hwreset/hwreset.h> 49#include <dev/phy/phy.h> 50#include <dev/regulator/regulator.h> 51#include <dev/fdt/fdt_pinctrl.h> 52#include <dev/ofw/ofw_bus.h> 53#include <dev/ofw/ofw_bus_subr.h> 54 55#include <arm/nvidia/tegra_efuse.h> 56#include <arm/nvidia/tegra_pmc.h> 57 58 59#define SATA_CONFIGURATION 0x180 60#define SATA_CONFIGURATION_CLK_OVERRIDE (1U << 31) 61#define SATA_CONFIGURATION_EN_FPCI (1 << 0) 62 63#define SATA_FPCI_BAR5 0x94 64#define SATA_FPCI_BAR_START(x) (((x) & 0xFFFFFFF) << 4) 65#define SATA_FPCI_BAR_ACCESS_TYPE (1 << 0) 66 67#define SATA_INTR_MASK 0x188 68#define SATA_INTR_MASK_IP_INT_MASK (1 << 16) 69 70#define SCFG_OFFSET 0x1000 71 72#define T_SATA0_CFG_1 0x04 73#define T_SATA0_CFG_1_IO_SPACE (1 << 0) 74#define T_SATA0_CFG_1_MEMORY_SPACE (1 << 1) 75#define T_SATA0_CFG_1_BUS_MASTER (1 << 2) 76#define T_SATA0_CFG_1_SERR (1 << 8) 77 78#define T_SATA0_CFG_9 0x24 79#define T_SATA0_CFG_9_BASE_ADDRESS_SHIFT 13 80 81#define T_SATA0_CFG_35 0x94 82#define T_SATA0_CFG_35_IDP_INDEX_MASK (0x7ff << 2) 83#define T_SATA0_CFG_35_IDP_INDEX (0x2a << 2) 84 85#define T_SATA0_AHCI_IDP1 0x98 86#define T_SATA0_AHCI_IDP1_DATA 0x400040 87 88#define T_SATA0_CFG_PHY_1 0x12c 89#define T_SATA0_CFG_PHY_1_PADS_IDDQ_EN (1 << 23) 90#define T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN (1 << 22) 91 92#define T_SATA0_NVOOB 0x114 93#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK (0x3 << 26) 94#define T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH (0x3 << 26) 95#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK (0x3 << 24) 96#define T_SATA0_NVOOB_SQUELCH_FILTER_MODE (0x1 << 24) 97#define T_SATA0_NVOOB_COMMA_CNT_MASK (0xff << 16) 98#define T_SATA0_NVOOB_COMMA_CNT (0x07 << 16) 99 100#define T_SATA0_CFG_PHY 0x120 101#define T_SATA0_CFG_PHY_MASK_SQUELCH (1 << 24) 102#define T_SATA0_CFG_PHY_USE_7BIT_ALIGN_DET_FOR_SPD (1 << 11) 103 104#define T_SATA0_CFG2NVOOB_2 0x134 105#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK (0x1ff << 18) 106#define T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW (0xc << 18) 107 108#define T_SATA0_AHCI_HBA_CAP_BKDR 0x300 109#define T_SATA0_AHCI_HBA_CAP_BKDR_SNCQ (1 << 30) 110#define T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM (1 << 17) 111#define T_SATA0_AHCI_HBA_CAP_BKDR_SALP (1 << 26) 112#define T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP (1 << 14) 113#define T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP (1 << 13) 114 115#define T_SATA0_BKDOOR_CC 0x4a4 116#define T_SATA0_BKDOOR_CC_CLASS_CODE_MASK (0xffff << 16) 117#define T_SATA0_BKDOOR_CC_CLASS_CODE (0x0106 << 16) 118#define T_SATA0_BKDOOR_CC_PROG_IF_MASK (0xff << 8) 119#define T_SATA0_BKDOOR_CC_PROG_IF (0x01 << 8) 120 121#define T_SATA0_CFG_SATA 0x54c 122#define T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN (1 << 12) 123 124#define T_SATA0_CFG_MISC 0x550 125#define T_SATA0_INDEX 0x680 126 127#define T_SATA0_CHX_PHY_CTRL1_GEN1 0x690 128#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK 0xff 129#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT 8 130#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK 0xff 131#define T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT 0 132 133#define T_SATA0_CHX_PHY_CTRL1_GEN2 0x694 134#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK 0xff 135#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT 12 136#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK 0xff 137#define T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT 0 138 139#define T_SATA0_CHX_PHY_CTRL2 0x69c 140#define T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1 0x23 141 142#define T_SATA0_CHX_PHY_CTRL11 0x6d0 143#define T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ (0x2800 << 16) 144 145#define T_SATA0_CHX_PHY_CTRL17 0x6e8 146#define T_SATA0_CHX_PHY_CTRL18 0x6ec 147#define T_SATA0_CHX_PHY_CTRL20 0x6f4 148#define T_SATA0_CHX_PHY_CTRL21 0x6f8 149 150#define FUSE_SATA_CALIB 0x124 151#define FUSE_SATA_CALIB_MASK 0x3 152 153#define SATA_AUX_MISC_CNTL 0x1108 154#define SATA_AUX_PAD_PLL_CTRL_0 0x1120 155#define SATA_AUX_PAD_PLL_CTRL_1 0x1124 156#define SATA_AUX_PAD_PLL_CTRL_2 0x1128 157#define SATA_AUX_PAD_PLL_CTRL_3 0x112c 158 159#define T_AHCI_HBA_CCC_PORTS 0x0018 160#define T_AHCI_HBA_CAP_BKDR 0x00A0 161#define T_AHCI_HBA_CAP_BKDR_S64A (1 << 31) 162#define T_AHCI_HBA_CAP_BKDR_SNCQ (1 << 30) 163#define T_AHCI_HBA_CAP_BKDR_SSNTF (1 << 29) 164#define T_AHCI_HBA_CAP_BKDR_SMPS (1 << 28) 165#define T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP (1 << 27) 166#define T_AHCI_HBA_CAP_BKDR_SALP (1 << 26) 167#define T_AHCI_HBA_CAP_BKDR_SAL (1 << 25) 168#define T_AHCI_HBA_CAP_BKDR_SUPP_CLO (1 << 24) 169#define T_AHCI_HBA_CAP_BKDR_INTF_SPD_SUPP(x) (((x) & 0xF) << 20) 170#define T_AHCI_HBA_CAP_BKDR_SUPP_NONZERO_OFFSET (1 << 19) 171#define T_AHCI_HBA_CAP_BKDR_SUPP_AHCI_ONLY (1 << 18) 172#define T_AHCI_HBA_CAP_BKDR_SUPP_PM (1 << 17) 173#define T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING (1 << 16) 174#define T_AHCI_HBA_CAP_BKDR_PIO_MULT_DRQ_BLK (1 << 15) 175#define T_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP (1 << 14) 176#define T_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP (1 << 13) 177#define T_AHCI_HBA_CAP_BKDR_NUM_CMD_SLOTS(x) (((x) & 0x1F) << 8) 178#define T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING (1 << 7) 179#define T_AHCI_HBA_CAP_BKDR_ENCL_MGMT_SUPP (1 << 6) 180#define T_AHCI_HBA_CAP_BKDR_EXT_SATA (1 << 5) 181#define T_AHCI_HBA_CAP_BKDR_NUM_PORTS(x) (((x) & 0xF) << 0) 182 183#define T_AHCI_PORT_BKDR 0x0170 184 185#define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE_VAL(x) (((x) & 0xFF) << 24) 186#define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE_VAL(x) (((x) & 0x1F) << 16) 187#define T_AHCI_PORT_BKDR_PXDEVSLP_DETO_OVERRIDE (1 << 15) 188#define T_AHCI_PORT_BKDR_PXDEVSLP_MDAT_OVERRIDE (1 << 14) 189#define T_AHCI_PORT_BKDR_PXDEVSLP_DM(x) (((x) & 0xF) << 10) 190#define T_AHCI_PORT_BKDR_PORT_UNCONNECTED (1 << 9) 191#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_CLAMP_THIS_CH (1 << 8) 192#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_UNCLAMP (1 << 7) 193#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_TXRXCLK_CLAMP (1 << 6) 194#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_UNCLAMP (1 << 5) 195#define T_AHCI_PORT_BKDR_CLK_CLAMP_CTRL_DEVCLK_CLAMP (1 << 4) 196#define T_AHCI_PORT_BKDR_HOTPLUG_CAP (1 << 3) 197#define T_AHCI_PORT_BKDR_MECH_SWITCH (1 << 2) 198#define T_AHCI_PORT_BKDR_COLD_PRSN_DET (1 << 1) 199#define T_AHCI_PORT_BKDR_EXT_SATA_SUPP (1 << 0) 200 201/* AUX registers */ 202#define SATA_AUX_MISC_CNTL_1 0x008 203#define SATA_AUX_MISC_CNTL_1_DEVSLP_OVERRIDE (1 << 17) 204#define SATA_AUX_MISC_CNTL_1_SDS_SUPPORT (1 << 13) 205#define SATA_AUX_MISC_CNTL_1_DESO_SUPPORT (1 << 15) 206 207#define AHCI_WR4(_sc, _r, _v) bus_write_4((_sc)->ctlr.r_mem, (_r), (_v)) 208#define AHCI_RD4(_sc, _r) bus_read_4((_sc)->ctlr.r_mem, (_r)) 209#define SATA_WR4(_sc, _r, _v) bus_write_4((_sc)->sata_mem, (_r), (_v)) 210#define SATA_RD4(_sc, _r) bus_read_4((_sc)->sata_mem, (_r)) 211 212struct sata_pad_calibration { 213 uint32_t gen1_tx_amp; 214 uint32_t gen1_tx_peak; 215 uint32_t gen2_tx_amp; 216 uint32_t gen2_tx_peak; 217}; 218 219static const struct sata_pad_calibration tegra124_pad_calibration[] = { 220 {0x18, 0x04, 0x18, 0x0a}, 221 {0x0e, 0x04, 0x14, 0x0a}, 222 {0x0e, 0x07, 0x1a, 0x0e}, 223 {0x14, 0x0e, 0x1a, 0x0e}, 224}; 225 226struct ahci_soc; 227struct tegra_ahci_sc { 228 struct ahci_controller ctlr; /* Must be first */ 229 device_t dev; 230 struct ahci_soc *soc; 231 struct resource *sata_mem; 232 struct resource *aux_mem; 233 clk_t clk_sata; 234 clk_t clk_sata_oob; 235 clk_t clk_pll_e; 236 clk_t clk_cml; 237 hwreset_t hwreset_sata; 238 hwreset_t hwreset_sata_oob; 239 hwreset_t hwreset_sata_cold; 240 regulator_t regulators[16]; /* Safe maximum */ 241 phy_t phy; 242}; 243 244struct ahci_soc { 245 char **regulator_names; 246 int (*init)(struct tegra_ahci_sc *sc); 247}; 248 249/* Tegra 124 config. */ 250static char *tegra124_reg_names[] = { 251 "hvdd-supply", 252 "vddio-supply", 253 "avdd-supply", 254 "target-5v-supply", 255 "target-12v-supply", 256 NULL 257}; 258 259static int tegra124_ahci_init(struct tegra_ahci_sc *sc); 260static struct ahci_soc tegra124_soc = { 261 .regulator_names = tegra124_reg_names, 262 .init = tegra124_ahci_init, 263}; 264 265/* Tegra 210 config. */ 266static char *tegra210_reg_names[] = { 267 NULL 268}; 269 270static struct ahci_soc tegra210_soc = { 271 .regulator_names = tegra210_reg_names, 272}; 273 274 275static struct ofw_compat_data compat_data[] = { 276 {"nvidia,tegra124-ahci", (uintptr_t)&tegra124_soc}, 277 {"nvidia,tegra210-ahci", (uintptr_t)&tegra210_soc}, 278 {NULL, 0} 279}; 280 281static int 282get_fdt_resources(struct tegra_ahci_sc *sc, phandle_t node) 283{ 284 int i, rv; 285 286 /* Regulators. */ 287 for (i = 0; sc->soc->regulator_names[i] != NULL; i++) { 288 if (i >= nitems(sc->regulators)) { 289 device_printf(sc->dev, 290 "Too many regulators present in DT.\n"); 291 return (EOVERFLOW); 292 } 293 rv = regulator_get_by_ofw_property(sc->dev, 0, 294 sc->soc->regulator_names[i], sc->regulators + i); 295 if (rv != 0) { 296 device_printf(sc->dev, 297 "Cannot get '%s' regulator\n", 298 sc->soc->regulator_names[i]); 299 return (ENXIO); 300 } 301 } 302 303 /* Resets. */ 304 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata", &sc->hwreset_sata ); 305 if (rv != 0) { 306 device_printf(sc->dev, "Cannot get 'sata' reset\n"); 307 return (ENXIO); 308 } 309 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-oob", 310 &sc->hwreset_sata_oob); 311 if (rv != 0) { 312 device_printf(sc->dev, "Cannot get 'sata oob' reset\n"); 313 return (ENXIO); 314 } 315 rv = hwreset_get_by_ofw_name(sc->dev, 0, "sata-cold", 316 &sc->hwreset_sata_cold); 317 if (rv != 0) { 318 device_printf(sc->dev, "Cannot get 'sata cold' reset\n"); 319 return (ENXIO); 320 } 321 322 /* Phy */ 323 rv = phy_get_by_ofw_name(sc->dev, 0, "sata-0", &sc->phy); 324 if (rv != 0) { 325 rv = phy_get_by_ofw_idx(sc->dev, 0, 0, &sc->phy); 326 if (rv != 0) { 327 device_printf(sc->dev, "Cannot get 'sata' phy\n"); 328 return (ENXIO); 329 } 330 } 331 332 /* Clocks. */ 333 rv = clk_get_by_ofw_name(sc->dev, 0, "sata", &sc->clk_sata); 334 if (rv != 0) { 335 device_printf(sc->dev, "Cannot get 'sata' clock\n"); 336 return (ENXIO); 337 } 338 rv = clk_get_by_ofw_name(sc->dev, 0, "sata-oob", &sc->clk_sata_oob); 339 if (rv != 0) { 340 device_printf(sc->dev, "Cannot get 'sata oob' clock\n"); 341 return (ENXIO); 342 } 343 /* These are optional */ 344 rv = clk_get_by_ofw_name(sc->dev, 0, "cml1", &sc->clk_cml); 345 if (rv != 0) 346 sc->clk_cml = NULL; 347 348 rv = clk_get_by_ofw_name(sc->dev, 0, "pll_e", &sc->clk_pll_e); 349 if (rv != 0) 350 sc->clk_pll_e = NULL; 351 return (0); 352} 353 354static int 355enable_fdt_resources(struct tegra_ahci_sc *sc) 356{ 357 int i, rv; 358 359 /* Enable regulators. */ 360 for (i = 0; i < nitems(sc->regulators); i++) { 361 if (sc->regulators[i] == NULL) 362 continue; 363 rv = regulator_enable(sc->regulators[i]); 364 if (rv != 0) { 365 device_printf(sc->dev, 366 "Cannot enable '%s' regulator\n", 367 sc->soc->regulator_names[i]); 368 return (rv); 369 } 370 } 371 372 /* Stop clocks */ 373 clk_stop(sc->clk_sata); 374 clk_stop(sc->clk_sata_oob); 375 tegra_powergate_power_off(TEGRA_POWERGATE_SAX); 376 377 rv = hwreset_assert(sc->hwreset_sata); 378 if (rv != 0) { 379 device_printf(sc->dev, "Cannot assert 'sata' reset\n"); 380 return (rv); 381 } 382 rv = hwreset_assert(sc->hwreset_sata_oob); 383 if (rv != 0) { 384 device_printf(sc->dev, "Cannot assert 'sata oob' reset\n"); 385 return (rv); 386 } 387 388 rv = hwreset_assert(sc->hwreset_sata_cold); 389 if (rv != 0) { 390 device_printf(sc->dev, "Cannot assert 'sata cold' reset\n"); 391 return (rv); 392 } 393 rv = tegra_powergate_sequence_power_up(TEGRA_POWERGATE_SAX, 394 sc->clk_sata, sc->hwreset_sata); 395 if (rv != 0) { 396 device_printf(sc->dev, "Cannot enable 'SAX' powergate\n"); 397 return (rv); 398 } 399 400 rv = clk_enable(sc->clk_sata_oob); 401 if (rv != 0) { 402 device_printf(sc->dev, "Cannot enable 'sata oob' clock\n"); 403 return (rv); 404 } 405 if (sc->clk_cml != NULL) { 406 rv = clk_enable(sc->clk_cml); 407 if (rv != 0) { 408 device_printf(sc->dev, "Cannot enable 'cml' clock\n"); 409 return (rv); 410 } 411 } 412 if (sc->clk_pll_e != NULL) { 413 rv = clk_enable(sc->clk_pll_e); 414 if (rv != 0) { 415 device_printf(sc->dev, "Cannot enable 'pll e' clock\n"); 416 return (rv); 417 } 418 } 419 420 rv = hwreset_deassert(sc->hwreset_sata_cold); 421 if (rv != 0) { 422 device_printf(sc->dev, "Cannot unreset 'sata cold' reset\n"); 423 return (rv); 424 } 425 rv = hwreset_deassert(sc->hwreset_sata_oob); 426 if (rv != 0) { 427 device_printf(sc->dev, "Cannot unreset 'sata oob' reset\n"); 428 return (rv); 429 } 430 431 rv = phy_enable(sc->phy); 432 if (rv != 0) { 433 device_printf(sc->dev, "Cannot enable SATA phy\n"); 434 return (rv); 435 } 436 437 return (0); 438} 439 440static int 441tegra124_ahci_init(struct tegra_ahci_sc *sc) 442{ 443 uint32_t val; 444 const struct sata_pad_calibration *calib; 445 446 /* Pad calibration. */ 447 val = tegra_fuse_read_4(FUSE_SATA_CALIB); 448 calib = tegra124_pad_calibration + (val & FUSE_SATA_CALIB_MASK); 449 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 1); 450 451 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1); 452 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_MASK << 453 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT); 454 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_MASK << 455 T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT); 456 val |= calib->gen1_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_AMP_SHIFT; 457 val |= calib->gen1_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN1_TX_PEAK_SHIFT; 458 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN1, val); 459 460 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2); 461 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_MASK << 462 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT); 463 val &= ~(T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_MASK << 464 T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT); 465 val |= calib->gen2_tx_amp << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_AMP_SHIFT; 466 val |= calib->gen2_tx_peak << T_SATA0_CHX_PHY_CTRL1_GEN2_TX_PEAK_SHIFT; 467 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL1_GEN2, val); 468 469 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL11, 470 T_SATA0_CHX_PHY_CTRL11_GEN2_RX_EQ); 471 472 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL2, 473 T_SATA0_CHX_PHY_CTRL2_CDR_CNTL_GEN1); 474 475 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_INDEX, 0); 476 477 return (0); 478} 479 480static int 481tegra_ahci_ctrl_init(struct tegra_ahci_sc *sc) 482{ 483 uint32_t val; 484 int rv; 485 486 /* Enable SATA MMIO. */ 487 val = SATA_RD4(sc, SATA_FPCI_BAR5); 488 val &= ~SATA_FPCI_BAR_START(~0); 489 val |= SATA_FPCI_BAR_START(0x10000); 490 val |= SATA_FPCI_BAR_ACCESS_TYPE; 491 SATA_WR4(sc, SATA_FPCI_BAR5, val); 492 493 /* Enable FPCI access */ 494 val = SATA_RD4(sc, SATA_CONFIGURATION); 495 val |= SATA_CONFIGURATION_EN_FPCI; 496 SATA_WR4(sc, SATA_CONFIGURATION, val); 497 498 /* Recommended electrical settings for phy */ 499 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL17, 0x55010000); 500 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL18, 0x55010000); 501 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL20, 0x1); 502 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CHX_PHY_CTRL21, 0x1); 503 504 /* SQUELCH and Gen3 */ 505 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY); 506 val |= T_SATA0_CFG_PHY_MASK_SQUELCH; 507 val &= ~T_SATA0_CFG_PHY_USE_7BIT_ALIGN_DET_FOR_SPD; 508 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY, val); 509 510 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_NVOOB); 511 val &= ~T_SATA0_NVOOB_COMMA_CNT_MASK; 512 val &= ~T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH_MASK; 513 val &= ~T_SATA0_NVOOB_SQUELCH_FILTER_MODE_MASK; 514 val |= T_SATA0_NVOOB_COMMA_CNT; 515 val |= T_SATA0_NVOOB_SQUELCH_FILTER_LENGTH; 516 val |= T_SATA0_NVOOB_SQUELCH_FILTER_MODE; 517 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_NVOOB, val); 518 519 /* Setup COMWAKE_IDLE_CNT */ 520 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG2NVOOB_2); 521 val &= ~T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW_MASK; 522 val |= T_SATA0_CFG2NVOOB_2_COMWAKE_IDLE_CNT_LOW; 523 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG2NVOOB_2, val); 524 525 if (sc->soc->init != NULL) { 526 rv = sc->soc->init(sc); 527 if (rv != 0) { 528 device_printf(sc->dev, 529 "SOC specific intialization failed: %d\n", rv); 530 return (rv); 531 } 532 } 533 534 /* Enable backdoor programming. */ 535 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA); 536 val |= T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 537 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val); 538 539 /* Set device class and interface */ 540 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC); 541 val &= ~T_SATA0_BKDOOR_CC_CLASS_CODE_MASK; 542 val &= ~T_SATA0_BKDOOR_CC_PROG_IF_MASK; 543 val |= T_SATA0_BKDOOR_CC_CLASS_CODE; 544 val |= T_SATA0_BKDOOR_CC_PROG_IF; 545 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_BKDOOR_CC, val); 546 547 /* Enable LPM capabilities */ 548 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR); 549 val |= T_SATA0_AHCI_HBA_CAP_BKDR_PARTIAL_ST_CAP; 550 val |= T_SATA0_AHCI_HBA_CAP_BKDR_SLUMBER_ST_CAP; 551 val |= T_SATA0_AHCI_HBA_CAP_BKDR_SALP; 552 val |= T_SATA0_AHCI_HBA_CAP_BKDR_SUPP_PM; 553 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_AHCI_HBA_CAP_BKDR, val); 554 555 /* Disable backdoor programming. */ 556 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA); 557 val &= ~T_SATA0_CFG_SATA_BACKDOOR_PROG_IF_EN; 558 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_SATA, val); 559 560 /* SATA Second Level Clock Gating */ 561 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_35); 562 val &= ~T_SATA0_CFG_35_IDP_INDEX_MASK; 563 val |= T_SATA0_CFG_35_IDP_INDEX; 564 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_35, val); 565 566 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_AHCI_IDP1, 0x400040); 567 568 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY_1); 569 val |= T_SATA0_CFG_PHY_1_PADS_IDDQ_EN; 570 val |= T_SATA0_CFG_PHY_1_PAD_PLL_IDDQ_EN; 571 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_PHY_1, val); 572 573 /* 574 * Indicate Sata only has the capability to enter DevSleep 575 * from slumber link. 576 */ 577 if (sc->aux_mem != NULL) { 578 val = bus_read_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1); 579 val |= SATA_AUX_MISC_CNTL_1_DESO_SUPPORT; 580 bus_write_4(sc->aux_mem, SATA_AUX_MISC_CNTL_1, val); 581 } 582 583 /* Enable IPFS Clock Gating */ 584 val = SATA_RD4(sc, SCFG_OFFSET + SATA_CONFIGURATION); 585 val &= ~SATA_CONFIGURATION_CLK_OVERRIDE; 586 SATA_WR4(sc, SCFG_OFFSET + SATA_CONFIGURATION, val); 587 588 589 /* Enable IO & memory access, bus master mode */ 590 val = SATA_RD4(sc, SCFG_OFFSET + T_SATA0_CFG_1); 591 val |= T_SATA0_CFG_1_IO_SPACE; 592 val |= T_SATA0_CFG_1_MEMORY_SPACE; 593 val |= T_SATA0_CFG_1_BUS_MASTER; 594 val |= T_SATA0_CFG_1_SERR; 595 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_1, val); 596 597 /* AHCI bar */ 598 SATA_WR4(sc, SCFG_OFFSET + T_SATA0_CFG_9, 599 0x08000 << T_SATA0_CFG_9_BASE_ADDRESS_SHIFT); 600 601 /* Unmask interrupts. */ 602 val = SATA_RD4(sc, SATA_INTR_MASK); 603 val |= SATA_INTR_MASK_IP_INT_MASK; 604 SATA_WR4(sc, SATA_INTR_MASK, val); 605 606 return (0); 607} 608 609static int 610tegra_ahci_ctlr_reset(device_t dev) 611{ 612 struct tegra_ahci_sc *sc; 613 int rv; 614 uint32_t reg; 615 616 sc = device_get_softc(dev); 617 rv = ahci_ctlr_reset(dev); 618 if (rv != 0) 619 return (0); 620 AHCI_WR4(sc, T_AHCI_HBA_CCC_PORTS, 1); 621 622 /* Overwrite AHCI capabilites. */ 623 reg = AHCI_RD4(sc, T_AHCI_HBA_CAP_BKDR); 624 reg &= ~T_AHCI_HBA_CAP_BKDR_NUM_PORTS(~0); 625 reg |= T_AHCI_HBA_CAP_BKDR_NUM_PORTS(0); 626 reg |= T_AHCI_HBA_CAP_BKDR_EXT_SATA; 627 reg |= T_AHCI_HBA_CAP_BKDR_CMD_CMPL_COALESING; 628 reg |= T_AHCI_HBA_CAP_BKDR_FIS_SWITCHING; 629 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_PM; 630 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_CLO; 631 reg |= T_AHCI_HBA_CAP_BKDR_SUPP_STG_SPUP; 632 AHCI_WR4(sc, T_AHCI_HBA_CAP_BKDR, reg); 633 634 /* Overwrite AHCI portcapabilites. */ 635 reg = AHCI_RD4(sc, T_AHCI_PORT_BKDR); 636 reg |= T_AHCI_PORT_BKDR_COLD_PRSN_DET; 637 reg |= T_AHCI_PORT_BKDR_HOTPLUG_CAP; 638 reg |= T_AHCI_PORT_BKDR_EXT_SATA_SUPP; 639 AHCI_WR4(sc, T_AHCI_PORT_BKDR, reg); 640 641 return (0); 642} 643 644static int 645tegra_ahci_probe(device_t dev) 646{ 647 648 if (!ofw_bus_status_okay(dev)) 649 return (ENXIO); 650 651 if (!ofw_bus_search_compatible(dev, compat_data)->ocd_data) 652 return (ENXIO); 653 654 device_set_desc(dev, "AHCI SATA controller"); 655 return (BUS_PROBE_DEFAULT); 656} 657 658static int 659tegra_ahci_attach(device_t dev) 660{ 661 struct tegra_ahci_sc *sc; 662 struct ahci_controller *ctlr; 663 phandle_t node; 664 int rv, rid; 665 666 sc = device_get_softc(dev); 667 sc->dev = dev; 668 ctlr = &sc->ctlr; 669 node = ofw_bus_get_node(dev); 670 sc->soc = (struct ahci_soc *)ofw_bus_search_compatible(dev, 671 compat_data)->ocd_data; 672 673 ctlr->r_rid = 0; 674 ctlr->r_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 675 &ctlr->r_rid, RF_ACTIVE); 676 if (ctlr->r_mem == NULL) 677 return (ENXIO); 678 679 rid = 1; 680 sc->sata_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 681 &rid, RF_ACTIVE); 682 if (sc->sata_mem == NULL) { 683 rv = ENXIO; 684 goto fail; 685 } 686 687 /* Aux is optionall */ 688 rid = 2; 689 sc->aux_mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 690 &rid, RF_ACTIVE); 691 692 rv = get_fdt_resources(sc, node); 693 if (rv != 0) { 694 device_printf(sc->dev, "Failed to allocate FDT resource(s)\n"); 695 goto fail; 696 } 697 698 rv = enable_fdt_resources(sc); 699 if (rv != 0) { 700 device_printf(sc->dev, "Failed to enable FDT resource(s)\n"); 701 goto fail; 702 } 703 rv = tegra_ahci_ctrl_init(sc); 704 if (rv != 0) { 705 device_printf(sc->dev, "Failed to initialize controller)\n"); 706 goto fail; 707 } 708 709 /* Setup controller defaults. */ 710 ctlr->msi = 0; 711 ctlr->numirqs = 1; 712 ctlr->ccc = 0; 713 714 /* Reset controller. */ 715 rv = tegra_ahci_ctlr_reset(dev); 716 if (rv != 0) 717 goto fail; 718 rv = ahci_attach(dev); 719 return (rv); 720 721fail: 722 /* XXX FDT stuff */ 723 if (sc->sata_mem != NULL) 724 bus_release_resource(dev, SYS_RES_MEMORY, 1, sc->sata_mem); 725 if (ctlr->r_mem != NULL) 726 bus_release_resource(dev, SYS_RES_MEMORY, ctlr->r_rid, 727 ctlr->r_mem); 728 return (rv); 729} 730 731static int 732tegra_ahci_detach(device_t dev) 733{ 734 735 ahci_detach(dev); 736 return (0); 737} 738 739static int 740tegra_ahci_suspend(device_t dev) 741{ 742 struct tegra_ahci_sc *sc = device_get_softc(dev); 743 744 bus_generic_suspend(dev); 745 /* Disable interupts, so the state change(s) doesn't trigger. */ 746 ATA_OUTL(sc->ctlr.r_mem, AHCI_GHC, 747 ATA_INL(sc->ctlr.r_mem, AHCI_GHC) & (~AHCI_GHC_IE)); 748 return (0); 749} 750 751static int 752tegra_ahci_resume(device_t dev) 753{ 754 int res; 755 756 if ((res = tegra_ahci_ctlr_reset(dev)) != 0) 757 return (res); 758 ahci_ctlr_setup(dev); 759 return (bus_generic_resume(dev)); 760} 761 762static device_method_t tegra_ahci_methods[] = { 763 DEVMETHOD(device_probe, tegra_ahci_probe), 764 DEVMETHOD(device_attach, tegra_ahci_attach), 765 DEVMETHOD(device_detach, tegra_ahci_detach), 766 DEVMETHOD(device_suspend, tegra_ahci_suspend), 767 DEVMETHOD(device_resume, tegra_ahci_resume), 768 DEVMETHOD(bus_print_child, ahci_print_child), 769 DEVMETHOD(bus_alloc_resource, ahci_alloc_resource), 770 DEVMETHOD(bus_release_resource, ahci_release_resource), 771 DEVMETHOD(bus_setup_intr, ahci_setup_intr), 772 DEVMETHOD(bus_teardown_intr, ahci_teardown_intr), 773 DEVMETHOD(bus_child_location, ahci_child_location), 774 DEVMETHOD(bus_get_dma_tag, ahci_get_dma_tag), 775 776 DEVMETHOD_END 777}; 778 779static DEFINE_CLASS_0(ahci, tegra_ahci_driver, tegra_ahci_methods, 780 sizeof(struct tegra_ahci_sc)); 781DRIVER_MODULE(tegra_ahci, simplebus, tegra_ahci_driver, NULL, NULL); 782