1/*-
2 * SPDX-License-Identifier: BSD-3-Clause
3 *
4 * Copyright (C) 2007-2011 MARVELL INTERNATIONAL LTD.
5 * All rights reserved.
6 *
7 * Developed by Semihalf.
8 *
9 * Redistribution and use in source and binary forms, with or without
10 * modification, are permitted provided that the following conditions
11 * are met:
12 * 1. Redistributions of source code must retain the above copyright
13 *    notice, this list of conditions and the following disclaimer.
14 * 2. Redistributions in binary form must reproduce the above copyright
15 *    notice, this list of conditions and the following disclaimer in the
16 *    documentation and/or other materials provided with the distribution.
17 * 3. Neither the name of MARVELL nor the names of contributors
18 *    may be used to endorse or promote products derived from this software
19 *    without specific prior written permission.
20 *
21 * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS ``AS IS'' AND
22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
24 * ARE DISCLAIMED.  IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE
25 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
26 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
27 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
28 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
29 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
31 * SUCH DAMAGE.
32 */
33
34#ifndef _MVWIN_H_
35#define _MVWIN_H_
36
37/*
38 * Decode windows addresses.
39 *
40 * All decoding windows must be aligned to their size, which has to be
41 * a power of 2.
42 */
43
44/*
45 * SoC Integrated devices: 0xF1000000, 16 MB (VA == PA)
46 */
47
48/* SoC Regs */
49#define MV_PHYS_BASE		0xF1000000
50#define MV_SIZE			(1024 * 1024)	/* 1 MB */
51
52/* SRAM */
53#define MV_CESA_SRAM_BASE	0xF1100000
54
55/*
56 * External devices: 0x80000000, 1 GB (VA == PA)
57 * Includes Device Bus, PCI and PCIE.
58 */
59#if defined(SOC_MV_ORION)
60#define MV_PCI_PORTS	2	/* 1x PCI + 1x PCIE */
61#elif defined(SOC_MV_KIRKWOOD)
62#define MV_PCI_PORTS	1	/* 1x PCIE */
63#elif defined(SOC_MV_DISCOVERY)
64#define MV_PCI_PORTS	8	/* 8x PCIE */
65#else
66#define	MV_PCI_PORTS    1       /* 1x PCIE -> worst case */
67#endif
68
69/* PCI/PCIE Memory */
70#define MV_PCI_MEM_PHYS_BASE	0x80000000
71#define MV_PCI_MEM_SIZE		(512 * 1024 * 1024)	/* 512 MB */
72#define MV_PCI_MEM_BASE		MV_PCI_MEM_PHYS_BASE
73#define MV_PCI_MEM_SLICE_SIZE	(MV_PCI_MEM_SIZE / MV_PCI_PORTS)
74/* PCI/PCIE I/O */
75#define MV_PCI_IO_PHYS_BASE	0xBF000000
76#define MV_PCI_IO_SIZE		(16 * 1024 * 1024)	/* 16 MB */
77#define MV_PCI_IO_BASE		MV_PCI_IO_PHYS_BASE
78#define MV_PCI_IO_SLICE_SIZE	(MV_PCI_IO_SIZE / MV_PCI_PORTS)
79#define MV_PCI_VA_MEM_BASE	0
80#define MV_PCI_VA_IO_BASE	0
81
82/*
83 * Device Bus (VA == PA)
84 */
85#define MV_DEV_BOOT_BASE    0xF9300000
86#define MV_DEV_BOOT_SIZE    (1024 * 1024)   /* 1 MB */
87
88#define MV_DEV_CS0_BASE     0xF9400000
89#define MV_DEV_CS0_SIZE     (1024 * 1024)   /* 1 MB */
90
91#define MV_DEV_CS1_BASE     0xF9500000
92#define MV_DEV_CS1_SIZE     (32 * 1024 * 1024)  /* 32 MB */
93
94#define MV_DEV_CS2_BASE     0xFB500000
95#define MV_DEV_CS2_SIZE     (1024 * 1024)   /* 1 MB */
96
97/*
98 * Integrated SoC peripherals addresses
99 */
100#define MV_BASE			MV_PHYS_BASE	/* VA == PA mapping */
101#define	MV_DDR_CADR_BASE_ARMV7	(MV_BASE + 0x20180)
102#define MV_DDR_CADR_BASE	(MV_BASE + 0x1500)
103#define MV_MPP_BASE		(MV_BASE + 0x10000)
104
105#define MV_MISC_BASE		(MV_BASE + 0x18200)
106#define MV_MBUS_BRIDGE_BASE	(MV_BASE + 0x20000)
107#define MV_INTREGS_BASE		(MV_MBUS_BRIDGE_BASE + 0x80)
108#define MV_MP_CLOCKS_BASE	(MV_MBUS_BRIDGE_BASE + 0x700)
109
110#define	MV_CPU_CONTROL_BASE_ARMV7	(MV_MBUS_BRIDGE_BASE + 0x1800)
111#define MV_CPU_CONTROL_BASE	(MV_MBUS_BRIDGE_BASE + 0x100)
112
113#define MV_PCI_BASE		(MV_BASE + 0x30000)
114#define MV_PCI_SIZE		0x2000
115
116#define	MV_PCIE_BASE_ARMADA38X	(MV_BASE + 0x80000)
117#define MV_PCIE_BASE		(MV_BASE + 0x40000)
118#define MV_PCIE_SIZE		0x2000
119#define MV_SDIO_BASE		(MV_BASE + 0x90000)
120#define MV_SDIO_SIZE		0x10000
121
122/*
123 * Decode windows definitions and macros
124 */
125#define	MV_WIN_CPU_CTRL_ARMV7(n)		(((n) < 8) ? 0x10 * (n) :  0x90 + (0x8 * ((n) - 8)))
126#define	MV_WIN_CPU_BASE_ARMV7(n)		((((n) < 8) ? 0x10 * (n) :  0x90 + (0x8 * ((n) - 8))) + 0x4)
127#define	MV_WIN_CPU_REMAP_LO_ARMV7(n)	(0x10 * (n) +  0x008)
128#define	MV_WIN_CPU_REMAP_HI_ARMV7(n)	(0x10 * (n) +  0x00C)
129
130#define	MV_WIN_CPU_CTRL_ARMV5(n)		(0x10 * (n) + (((n) < 8) ? 0x000 : 0x880))
131#define	MV_WIN_CPU_BASE_ARMV5(n)		(0x10 * (n) + (((n) < 8) ? 0x004 : 0x884))
132#define	MV_WIN_CPU_REMAP_LO_ARMV5(n)		(0x10 * (n) + (((n) < 8) ? 0x008 : 0x888))
133#define	MV_WIN_CPU_REMAP_HI_ARMV5(n)		(0x10 * (n) + (((n) < 8) ? 0x00C : 0x88C))
134
135#if defined(SOC_MV_DISCOVERY)
136#define MV_WIN_CPU_MAX			14
137#else
138#define MV_WIN_CPU_MAX			8
139#endif
140#define	MV_WIN_CPU_MAX_ARMV7		20
141
142#define MV_WIN_CPU_ATTR_SHIFT		8
143#define MV_WIN_CPU_TARGET_SHIFT		4
144#define MV_WIN_CPU_ENABLE_BIT		1
145
146#define MV_WIN_DDR_BASE(n)		(0x8 * (n) + 0x0)
147#define MV_WIN_DDR_SIZE(n)		(0x8 * (n) + 0x4)
148#define MV_WIN_DDR_MAX			4
149
150/*
151 * These values are valid only for peripherals decoding windows
152 * Bit in ATTR is zeroed according to CS bank number
153 */
154#define MV_WIN_DDR_ATTR(cs)		(0x0F & ~(0x01 << (cs)))
155#define MV_WIN_DDR_TARGET		0x0
156
157#if defined(SOC_MV_DISCOVERY)
158#define MV_WIN_CESA_TARGET		9
159#define MV_WIN_CESA_ATTR(eng_sel)	1
160#else
161#define	MV_WIN_CESA_TARGET		3
162#define	MV_WIN_CESA_ATTR(eng_sel)	0
163#endif
164
165#define	MV_WIN_CESA_TARGET_ARMADAXP	9
166/*
167 * Bits [2:3] of cesa attribute select engine:
168 * eng_sel:
169 *  1: engine1
170 *  2: engine0
171 */
172#define	MV_WIN_CESA_ATTR_ARMADAXP(eng_sel)	(1 | ((eng_sel) << 2))
173#define	MV_WIN_CESA_TARGET_ARMADA38X		9
174/*
175 * Bits [1:0] = Data swapping
176 *  0x0 = Byte swap
177 *  0x1 = No swap
178 *  0x2 = Byte and word swap
179 *  0x3 = Word swap
180 * Bits [4:2] = CESA select:
181 *  0x6 = CESA0
182 *  0x5 = CESA1
183 */
184#define	MV_WIN_CESA_ATTR_ARMADA38X(eng_sel)	(0x11 | (1 << (3 - (eng_sel))))
185/* CESA TDMA address decoding registers */
186#define MV_WIN_CESA_CTRL(n)		(0x8 * (n) + 0xA04)
187#define MV_WIN_CESA_BASE(n)		(0x8 * (n) + 0xA00)
188#define MV_WIN_CESA_MAX			4
189
190#define MV_WIN_USB_CTRL(n)		(0x10 * (n) + 0x320)
191#define MV_WIN_USB_BASE(n)		(0x10 * (n) + 0x324)
192#define MV_WIN_USB_MAX			4
193
194#define	MV_WIN_USB3_CTRL(n)		(0x8 * (n) + 0x4000)
195#define	MV_WIN_USB3_BASE(n)		(0x8 * (n) + 0x4004)
196#define	MV_WIN_USB3_MAX			8
197
198#define	MV_WIN_NETA_OFFSET		0x2000
199#define	MV_WIN_NETA_BASE(n)		MV_WIN_ETH_BASE(n) + MV_WIN_NETA_OFFSET
200
201#define MV_WIN_CESA_OFFSET		0x2000
202
203#define MV_WIN_ETH_BASE(n)		(0x8 * (n) + 0x200)
204#define MV_WIN_ETH_SIZE(n)		(0x8 * (n) + 0x204)
205#define MV_WIN_ETH_REMAP(n)		(0x4 * (n) + 0x280)
206#define MV_WIN_ETH_MAX			6
207
208#define MV_WIN_IDMA_BASE(n)		(0x8 * (n) + 0xa00)
209#define MV_WIN_IDMA_SIZE(n)		(0x8 * (n) + 0xa04)
210#define MV_WIN_IDMA_REMAP(n)		(0x4 * (n) + 0xa60)
211#define MV_WIN_IDMA_CAP(n)		(0x4 * (n) + 0xa70)
212#define MV_WIN_IDMA_MAX			8
213#define MV_IDMA_CHAN_MAX		4
214
215#define MV_WIN_XOR_BASE(n, m)		(0x4 * (n) + 0xa50 + (m) * 0x100)
216#define MV_WIN_XOR_SIZE(n, m)		(0x4 * (n) + 0xa70 + (m) * 0x100)
217#define MV_WIN_XOR_REMAP(n, m)		(0x4 * (n) + 0xa90 + (m) * 0x100)
218#define MV_WIN_XOR_CTRL(n, m)		(0x4 * (n) + 0xa40 + (m) * 0x100)
219#define MV_WIN_XOR_OVERR(n, m)		(0x4 * (n) + 0xaa0 + (m) * 0x100)
220#define MV_WIN_XOR_MAX			8
221#define MV_XOR_CHAN_MAX			2
222#define MV_XOR_NON_REMAP		4
223
224#define	MV_WIN_PCIE_TARGET_ARMADAXP(n)		(4 + (4 * ((n) % 2)))
225#define	MV_WIN_PCIE_MEM_ATTR_ARMADAXP(n)	(0xE8 + (0x10 * ((n) / 2)))
226#define	MV_WIN_PCIE_IO_ATTR_ARMADAXP(n)		(0xE0 + (0x10 * ((n) / 2)))
227#define	MV_WIN_PCIE_TARGET_ARMADA38X(n)		((n) == 0 ? 8 : 4)
228#define	MV_WIN_PCIE_MEM_ATTR_ARMADA38X(n)	((n) < 2 ? 0xE8 : (0xD8 - (((n) % 2) * 0x20)))
229#define	MV_WIN_PCIE_IO_ATTR_ARMADA38X(n)	((n) < 2 ? 0xE0 : (0xD0 - (((n) % 2) * 0x20)))
230#if defined(SOC_MV_DISCOVERY) || defined(SOC_MV_KIRKWOOD)
231#define MV_WIN_PCIE_TARGET(n)		4
232#define MV_WIN_PCIE_MEM_ATTR(n)		0xE8
233#define MV_WIN_PCIE_IO_ATTR(n)		0xE0
234#elif defined(SOC_MV_ORION)
235#define MV_WIN_PCIE_TARGET(n)		4
236#define MV_WIN_PCIE_MEM_ATTR(n)		0x59
237#define MV_WIN_PCIE_IO_ATTR(n)		0x51
238#else
239#define	MV_WIN_PCIE_TARGET(n)           (4 + (4 * ((n) % 2)))
240#define	MV_WIN_PCIE_MEM_ATTR(n)         (0xE8 + (0x10 * ((n) / 2)))
241#define	MV_WIN_PCIE_IO_ATTR(n)          (0xE0 + (0x10 * ((n) / 2)))
242#endif
243
244#define MV_WIN_PCI_TARGET		3
245#define MV_WIN_PCI_MEM_ATTR		0x59
246#define MV_WIN_PCI_IO_ATTR		0x51
247
248#define MV_WIN_PCIE_CTRL(n)		(0x10 * (((n) < 5) ? (n) : \
249					    (n) + 1) + 0x1820)
250#define MV_WIN_PCIE_BASE(n)		(0x10 * (((n) < 5) ? (n) : \
251					    (n) + 1) + 0x1824)
252#define MV_WIN_PCIE_REMAP(n)		(0x10 * (((n) < 5) ? (n) : \
253					    (n) + 1) + 0x182C)
254#define MV_WIN_PCIE_MAX			6
255
256#define MV_PCIE_BAR_CTRL(n)		(0x04 * (n) + 0x1800)
257#define MV_PCIE_BAR_BASE(n)		(0x08 * ((n) < 3 ? (n) : 4) + 0x0010)
258#define MV_PCIE_BAR_BASE_H(n)		(0x08 * (n) + 0x0014)
259#define MV_PCIE_BAR_MAX			4
260#define MV_PCIE_BAR_64BIT		(0x4)
261#define MV_PCIE_BAR_PREFETCH_EN		(0x8)
262
263#define MV_PCIE_CONTROL			(0x1a00)
264#define MV_PCIE_ROOT_CMPLX		(1 << 1)
265
266#define	MV_WIN_SATA_CTRL_ARMADA38X(n)	(0x10 * (n) + 0x60)
267#define	MV_WIN_SATA_BASE_ARMADA38X(n)	(0x10 * (n) + 0x64)
268#define	MV_WIN_SATA_SIZE_ARMADA38X(n)	(0x10 * (n) + 0x68)
269#define	MV_WIN_SATA_MAX_ARMADA38X	4
270#define	MV_WIN_SATA_CTRL(n)		(0x10 * (n) + 0x30)
271#define	MV_WIN_SATA_BASE(n)		(0x10 * (n) + 0x34)
272#define	MV_WIN_SATA_MAX			4
273
274#define	MV_WIN_SDHCI_CTRL(n)		(0x8 * (n) + 0x4080)
275#define	MV_WIN_SDHCI_BASE(n)		(0x8 * (n) + 0x4084)
276#define	MV_WIN_SDHCI_MAX		8
277
278#define	MV_BOOTROM_MEM_ADDR	0xFFF00000
279#define	MV_BOOTROM_WIN_SIZE	0xF
280#define	MV_CPU_SUBSYS_REGS_LEN	0x100
281
282#define	IO_WIN_9_CTRL_OFFSET	0x98
283#define	IO_WIN_9_BASE_OFFSET	0x9C
284
285/* Mbus decoding unit IDs and attributes */
286#define	MBUS_BOOTROM_TGT_ID	0x1
287#define	MBUS_BOOTROM_ATTR	0x1D
288
289/* Internal Units Sync Barrier Control Register */
290#define	MV_SYNC_BARRIER_CTRL		0x84
291#define	MV_SYNC_BARRIER_CTRL_ALL	0xFFFF
292
293/* IO Window Control Register fields */
294#define	IO_WIN_SIZE_SHIFT	16
295#define	IO_WIN_SIZE_MASK	0xFFFF
296#define	IO_WIN_COH_ATTR_MASK	(0xF << 12)
297#define	IO_WIN_ATTR_SHIFT	8
298#define	IO_WIN_ATTR_MASK	0xFF
299#define	IO_WIN_TGT_SHIFT	4
300#define	IO_WIN_TGT_MASK		0xF
301#define	IO_WIN_SYNC_SHIFT	1
302#define	IO_WIN_SYNC_MASK	0x1
303#define	IO_WIN_ENA_SHIFT	0
304#define	IO_WIN_ENA_MASK		0x1
305
306#define WIN_REG_IDX_RD(pre,reg,off,base)					\
307	static __inline uint32_t						\
308	pre ## _ ## reg ## _read(int i)						\
309	{									\
310		return (bus_space_read_4(fdtbus_bs_tag, base, off(i)));		\
311	}
312
313#define WIN_REG_IDX_RD2(pre,reg,off,base)					\
314	static  __inline uint32_t						\
315	pre ## _ ## reg ## _read(int i, int j)					\
316	{									\
317		return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j)));		\
318	}									\
319
320#define WIN_REG_BASE_IDX_RD(pre,reg,off)					\
321	static __inline uint32_t						\
322	pre ## _ ## reg ## _read(uint32_t base, int i)				\
323	{									\
324		return (bus_space_read_4(fdtbus_bs_tag, base, off(i)));		\
325	}
326
327#define WIN_REG_BASE_IDX_RD2(pre,reg,off)					\
328	static __inline uint32_t						\
329	pre ## _ ## reg ## _read(uint32_t base, int i, int j)				\
330	{									\
331		return (bus_space_read_4(fdtbus_bs_tag, base, off(i, j)));		\
332	}
333
334#define WIN_REG_IDX_WR(pre,reg,off,base)					\
335	static __inline void							\
336	pre ## _ ## reg ## _write(int i, uint32_t val)				\
337	{									\
338		bus_space_write_4(fdtbus_bs_tag, base, off(i), val);			\
339	}
340
341#define WIN_REG_IDX_WR2(pre,reg,off,base)					\
342	static __inline void							\
343	pre ## _ ## reg ## _write(int i, int j, uint32_t val)			\
344	{									\
345		bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val);		\
346	}
347
348#define WIN_REG_BASE_IDX_WR(pre,reg,off)					\
349	static __inline void							\
350	pre ## _ ## reg ## _write(uint32_t base, int i, uint32_t val)		\
351	{									\
352		bus_space_write_4(fdtbus_bs_tag, base, off(i), val);			\
353	}
354
355#define WIN_REG_BASE_IDX_WR2(pre,reg,off)					\
356	static __inline void							\
357	pre ## _ ## reg ## _write(uint32_t base, int i, int j, uint32_t val)		\
358	{									\
359		bus_space_write_4(fdtbus_bs_tag, base, off(i, j), val);			\
360	}
361
362#define WIN_REG_RD(pre,reg,off,base)						\
363	static __inline uint32_t						\
364	pre ## _ ## reg ## _read(void)						\
365	{									\
366		return (bus_space_read_4(fdtbus_bs_tag, base, off));			\
367	}
368
369#define WIN_REG_BASE_RD(pre,reg,off)						\
370	static __inline uint32_t						\
371	pre ## _ ## reg ## _read(uint32_t base)					\
372	{									\
373		return (bus_space_read_4(fdtbus_bs_tag, base, off));			\
374	}
375
376#define WIN_REG_WR(pre,reg,off,base)						\
377	static __inline void							\
378	pre ## _ ## reg ## _write(uint32_t val)					\
379	{									\
380		bus_space_write_4(fdtbus_bs_tag, base, off, val);			\
381	}
382
383#define WIN_REG_BASE_WR(pre,reg,off)						\
384	static __inline void							\
385	pre ## _ ## reg ## _write(uint32_t base, uint32_t val)			\
386	{									\
387		bus_space_write_4(fdtbus_bs_tag, base, off, val);			\
388	}
389
390#endif /* _MVWIN_H_ */
391