1/* $NetBSD: armreg.h,v 1.37 2007/01/06 00:50:54 christos Exp $ */ 2 3/*- 4 * SPDX-License-Identifier: BSD-4-Clause 5 * 6 * Copyright (c) 1998, 2001 Ben Harris 7 * Copyright (c) 1994-1996 Mark Brinicombe. 8 * Copyright (c) 1994 Brini. 9 * All rights reserved. 10 * 11 * This code is derived from software written for Brini by Mark Brinicombe 12 * 13 * Redistribution and use in source and binary forms, with or without 14 * modification, are permitted provided that the following conditions 15 * are met: 16 * 1. Redistributions of source code must retain the above copyright 17 * notice, this list of conditions and the following disclaimer. 18 * 2. Redistributions in binary form must reproduce the above copyright 19 * notice, this list of conditions and the following disclaimer in the 20 * documentation and/or other materials provided with the distribution. 21 * 3. All advertising materials mentioning features or use of this software 22 * must display the following acknowledgement: 23 * This product includes software developed by Brini. 24 * 4. The name of the company nor the name of the author may be used to 25 * endorse or promote products derived from this software without specific 26 * prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY BRINI ``AS IS'' AND ANY EXPRESS OR IMPLIED 29 * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 30 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 31 * IN NO EVENT SHALL BRINI OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, 32 * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES 33 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR 34 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 35 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 37 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 38 * SUCH DAMAGE. 39 */ 40 41#ifndef MACHINE_ARMREG_H 42#define MACHINE_ARMREG_H 43 44#define PSR_MODE 0x0000001f /* mode mask */ 45#define PSR_USR32_MODE 0x00000010 46#define PSR_FIQ32_MODE 0x00000011 47#define PSR_IRQ32_MODE 0x00000012 48#define PSR_SVC32_MODE 0x00000013 49#define PSR_MON32_MODE 0x00000016 50#define PSR_ABT32_MODE 0x00000017 51#define PSR_HYP32_MODE 0x0000001a 52#define PSR_UND32_MODE 0x0000001b 53#define PSR_SYS32_MODE 0x0000001f 54#define PSR_32_MODE 0x00000010 55#define PSR_T 0x00000020 /* Instruction set bit */ 56#define PSR_F 0x00000040 /* FIQ disable bit */ 57#define PSR_I 0x00000080 /* IRQ disable bit */ 58#define PSR_A 0x00000100 /* Imprecise abort bit */ 59#define PSR_E 0x00000200 /* Data endianess bit */ 60#define PSR_GE 0x000f0000 /* Greater than or equal to bits */ 61#define PSR_J 0x01000000 /* Java bit */ 62#define PSR_Q 0x08000000 /* Sticky overflow bit */ 63#define PSR_V 0x10000000 /* Overflow bit */ 64#define PSR_C 0x20000000 /* Carry bit */ 65#define PSR_Z 0x40000000 /* Zero bit */ 66#define PSR_N 0x80000000 /* Negative bit */ 67#define PSR_FLAGS 0xf0000000 /* Flags mask. */ 68 69/* The high-order byte is always the implementor */ 70#define CPU_ID_IMPLEMENTOR_MASK 0xff000000 71#define CPU_ID_ARM_LTD 0x41000000 /* 'A' */ 72#define CPU_ID_DEC 0x44000000 /* 'D' */ 73#define CPU_ID_MOTOROLA 0x4D000000 /* 'M' */ 74#define CPU_ID_QUALCOM 0x51000000 /* 'Q' */ 75#define CPU_ID_TI 0x54000000 /* 'T' */ 76#define CPU_ID_MARVELL 0x56000000 /* 'V' */ 77#define CPU_ID_INTEL 0x69000000 /* 'i' */ 78#define CPU_ID_FARADAY 0x66000000 /* 'f' */ 79 80#define CPU_ID_VARIANT_SHIFT 20 81#define CPU_ID_VARIANT_MASK 0x00f00000 82 83/* How to decide what format the CPUID is in. */ 84#define CPU_ID_ISOLD(x) (((x) & 0x0000f000) == 0x00000000) 85#define CPU_ID_IS7(x) (((x) & 0x0000f000) == 0x00007000) 86#define CPU_ID_ISNEW(x) (!CPU_ID_ISOLD(x) && !CPU_ID_IS7(x)) 87 88/* On recent ARMs this byte holds the architecture and variant (sub-model) */ 89#define CPU_ID_ARCH_MASK 0x000f0000 90#define CPU_ID_ARCH_V3 0x00000000 91#define CPU_ID_ARCH_V4 0x00010000 92#define CPU_ID_ARCH_V4T 0x00020000 93#define CPU_ID_ARCH_V5 0x00030000 94#define CPU_ID_ARCH_V5T 0x00040000 95#define CPU_ID_ARCH_V5TE 0x00050000 96#define CPU_ID_ARCH_V5TEJ 0x00060000 97#define CPU_ID_ARCH_V6 0x00070000 98#define CPU_ID_CPUID_SCHEME 0x000f0000 99 100/* Next three nybbles are part number */ 101#define CPU_ID_PARTNO_MASK 0x0000fff0 102 103/* Intel XScale has sub fields in part number */ 104#define CPU_ID_XSCALE_COREGEN_MASK 0x0000e000 /* core generation */ 105#define CPU_ID_XSCALE_COREREV_MASK 0x00001c00 /* core revision */ 106#define CPU_ID_XSCALE_PRODUCT_MASK 0x000003f0 /* product number */ 107 108/* And finally, the revision number. */ 109#define CPU_ID_REVISION_MASK 0x0000000f 110 111/* Individual CPUs are probably best IDed by everything but the revision. */ 112#define CPU_ID_CPU_MASK 0xfffffff0 113 114/* ARM9 and later CPUs */ 115#define CPU_ID_ARM920T 0x41129200 116#define CPU_ID_ARM920T_ALT 0x41009200 117#define CPU_ID_ARM922T 0x41029220 118#define CPU_ID_ARM926EJS 0x41069260 119#define CPU_ID_ARM940T 0x41029400 /* XXX no MMU */ 120#define CPU_ID_ARM946ES 0x41049460 /* XXX no MMU */ 121#define CPU_ID_ARM966ES 0x41049660 /* XXX no MMU */ 122#define CPU_ID_ARM966ESR1 0x41059660 /* XXX no MMU */ 123#define CPU_ID_ARM1020E 0x4115a200 /* (AKA arm10 rev 1) */ 124#define CPU_ID_ARM1022ES 0x4105a220 125#define CPU_ID_ARM1026EJS 0x4106a260 126#define CPU_ID_ARM1136JS 0x4107b360 127#define CPU_ID_ARM1136JSR1 0x4117b360 128#define CPU_ID_ARM1176JZS 0x410fb760 129 130/* CPUs that follow the CPUID scheme */ 131#define CPU_ID_SCHEME_MASK \ 132 (CPU_ID_IMPLEMENTOR_MASK | CPU_ID_ARCH_MASK | CPU_ID_PARTNO_MASK) 133 134#define CPU_ID_CORTEXA5 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc050) 135#define CPU_ID_CORTEXA7 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc070) 136#define CPU_ID_CORTEXA8 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc080) 137#define CPU_ID_CORTEXA8R1 (CPU_ID_CORTEXA8 | (1 << CPU_ID_VARIANT_SHIFT)) 138#define CPU_ID_CORTEXA8R2 (CPU_ID_CORTEXA8 | (2 << CPU_ID_VARIANT_SHIFT)) 139#define CPU_ID_CORTEXA8R3 (CPU_ID_CORTEXA8 | (3 << CPU_ID_VARIANT_SHIFT)) 140#define CPU_ID_CORTEXA9 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc090) 141#define CPU_ID_CORTEXA9R1 (CPU_ID_CORTEXA9 | (1 << CPU_ID_VARIANT_SHIFT)) 142#define CPU_ID_CORTEXA9R2 (CPU_ID_CORTEXA9 | (2 << CPU_ID_VARIANT_SHIFT)) 143#define CPU_ID_CORTEXA9R3 (CPU_ID_CORTEXA9 | (3 << CPU_ID_VARIANT_SHIFT)) 144#define CPU_ID_CORTEXA9R4 (CPU_ID_CORTEXA9 | (4 << CPU_ID_VARIANT_SHIFT)) 145/* XXX: Cortex-A12 is the old name for this part, it has been renamed the A17 */ 146#define CPU_ID_CORTEXA12 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0d0) 147#define CPU_ID_CORTEXA12R0 (CPU_ID_CORTEXA12 | (0 << CPU_ID_VARIANT_SHIFT)) 148#define CPU_ID_CORTEXA15 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xc0f0) 149#define CPU_ID_CORTEXA15R0 (CPU_ID_CORTEXA15 | (0 << CPU_ID_VARIANT_SHIFT)) 150#define CPU_ID_CORTEXA15R1 (CPU_ID_CORTEXA15 | (1 << CPU_ID_VARIANT_SHIFT)) 151#define CPU_ID_CORTEXA15R2 (CPU_ID_CORTEXA15 | (2 << CPU_ID_VARIANT_SHIFT)) 152#define CPU_ID_CORTEXA15R3 (CPU_ID_CORTEXA15 | (3 << CPU_ID_VARIANT_SHIFT)) 153#define CPU_ID_CORTEXA53 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd030) 154#define CPU_ID_CORTEXA57 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd070) 155#define CPU_ID_CORTEXA72 (CPU_ID_ARM_LTD | CPU_ID_CPUID_SCHEME | 0xd080) 156 157#define CPU_ID_KRAIT300 (CPU_ID_QUALCOM | CPU_ID_CPUID_SCHEME | 0x06f0) 158/* Snapdragon S4 Pro/APQ8064 */ 159#define CPU_ID_KRAIT300R0 (CPU_ID_KRAIT300 | (0 << CPU_ID_VARIANT_SHIFT)) 160#define CPU_ID_KRAIT300R1 (CPU_ID_KRAIT300 | (1 << CPU_ID_VARIANT_SHIFT)) 161 162#define CPU_ID_TI925T 0x54029250 163#define CPU_ID_MV88FR131 0x56251310 /* Marvell Feroceon 88FR131 Core */ 164#define CPU_ID_MV88FR331 0x56153310 /* Marvell Feroceon 88FR331 Core */ 165#define CPU_ID_MV88FR571_VD 0x56155710 /* Marvell Feroceon 88FR571-VD Core (ID from datasheet) */ 166 167/* 168 * LokiPlus core has also ID set to 0x41159260 and this define cause execution of unsupported 169 * L2-cache instructions so need to disable it. 0x41159260 is a generic ARM926E-S ID. 170 */ 171#ifdef SOC_MV_LOKIPLUS 172#define CPU_ID_MV88FR571_41 0x00000000 173#else 174#define CPU_ID_MV88FR571_41 0x41159260 /* Marvell Feroceon 88FR571-VD Core (actual ID from CPU reg) */ 175#endif 176 177#define CPU_ID_MV88SV581X_V7 0x561F5810 /* Marvell Sheeva 88SV581x v7 Core */ 178#define CPU_ID_MV88SV584X_V7 0x562F5840 /* Marvell Sheeva 88SV584x v7 Core */ 179/* Marvell's CPUIDs with ARM ID in implementor field */ 180#define CPU_ID_ARM_88SV581X_V7 0x413FC080 /* Marvell Sheeva 88SV581x v7 Core */ 181 182#define CPU_ID_FA526 0x66015260 183#define CPU_ID_FA626TE 0x66056260 184#define CPU_ID_80200 0x69052000 185#define CPU_ID_PXA250 0x69052100 /* sans core revision */ 186#define CPU_ID_PXA210 0x69052120 187#define CPU_ID_PXA250A 0x69052100 /* 1st version Core */ 188#define CPU_ID_PXA210A 0x69052120 /* 1st version Core */ 189#define CPU_ID_PXA250B 0x69052900 /* 3rd version Core */ 190#define CPU_ID_PXA210B 0x69052920 /* 3rd version Core */ 191#define CPU_ID_PXA250C 0x69052d00 /* 4th version Core */ 192#define CPU_ID_PXA210C 0x69052d20 /* 4th version Core */ 193#define CPU_ID_PXA27X 0x69054110 194#define CPU_ID_80321_400 0x69052420 195#define CPU_ID_80321_600 0x69052430 196#define CPU_ID_80321_400_B0 0x69052c20 197#define CPU_ID_80321_600_B0 0x69052c30 198#define CPU_ID_80219_400 0x69052e20 /* A0 stepping/revision. */ 199#define CPU_ID_80219_600 0x69052e30 /* A0 stepping/revision. */ 200#define CPU_ID_81342 0x69056810 201#define CPU_ID_IXP425 0x690541c0 202#define CPU_ID_IXP425_533 0x690541c0 203#define CPU_ID_IXP425_400 0x690541d0 204#define CPU_ID_IXP425_266 0x690541f0 205#define CPU_ID_IXP435 0x69054040 206#define CPU_ID_IXP465 0x69054200 207 208/* CPUID registers */ 209#define ARM_PFR0_ARM_ISA_MASK 0x0000000f 210 211#define ARM_PFR0_THUMB_MASK 0x000000f0 212#define ARM_PFR0_THUMB 0x10 213#define ARM_PFR0_THUMB2 0x30 214 215#define ARM_PFR0_JAZELLE_MASK 0x00000f00 216#define ARM_PFR0_THUMBEE_MASK 0x0000f000 217 218#define ARM_PFR1_ARMV4_MASK 0x0000000f 219#define ARM_PFR1_SEC_EXT_MASK 0x000000f0 220#define ARM_PFR1_MICROCTRL_MASK 0x00000f00 221 222/* 223 * Post-ARM3 CP15 registers: 224 * 225 * 1 Control register 226 * 227 * 2 Translation Table Base 228 * 229 * 3 Domain Access Control 230 * 231 * 4 Reserved 232 * 233 * 5 Fault Status 234 * 235 * 6 Fault Address 236 * 237 * 7 Cache/write-buffer Control 238 * 239 * 8 TLB Control 240 * 241 * 9 Cache Lockdown 242 * 243 * 10 TLB Lockdown 244 * 245 * 11 Reserved 246 * 247 * 12 Reserved 248 * 249 * 13 Process ID (for FCSE) 250 * 251 * 14 Reserved 252 * 253 * 15 Implementation Dependent 254 */ 255 256/* Some of the definitions below need cleaning up for V3/V4 architectures */ 257 258/* CPU control register (CP15 register 1) */ 259#define CPU_CONTROL_MMU_ENABLE 0x00000001 /* M: MMU/Protection unit enable */ 260#define CPU_CONTROL_AFLT_ENABLE 0x00000002 /* A: Alignment fault enable */ 261#define CPU_CONTROL_DC_ENABLE 0x00000004 /* C: IDC/DC enable */ 262#define CPU_CONTROL_WBUF_ENABLE 0x00000008 /* W: Write buffer enable */ 263#define CPU_CONTROL_32BP_ENABLE 0x00000010 /* P: 32-bit exception handlers */ 264#define CPU_CONTROL_32BD_ENABLE 0x00000020 /* D: 32-bit addressing */ 265#define CPU_CONTROL_LABT_ENABLE 0x00000040 /* L: Late abort enable */ 266#define CPU_CONTROL_BEND_ENABLE 0x00000080 /* B: Big-endian mode */ 267#define CPU_CONTROL_SYST_ENABLE 0x00000100 /* S: System protection bit */ 268#define CPU_CONTROL_ROM_ENABLE 0x00000200 /* R: ROM protection bit */ 269#define CPU_CONTROL_CPCLK 0x00000400 /* F: Implementation defined */ 270#define CPU_CONTROL_SW_ENABLE 0x00000400 /* SW: SWP instruction enable */ 271#define CPU_CONTROL_BPRD_ENABLE 0x00000800 /* Z: Branch prediction enable */ 272#define CPU_CONTROL_IC_ENABLE 0x00001000 /* I: IC enable */ 273#define CPU_CONTROL_VECRELOC 0x00002000 /* V: Vector relocation */ 274#define CPU_CONTROL_ROUNDROBIN 0x00004000 /* RR: Predictable replacement */ 275#define CPU_CONTROL_V4COMPAT 0x00008000 /* L4: ARMv4 compat LDR R15 etc */ 276#define CPU_CONTROL_HAF_ENABLE 0x00020000 /* HA: Hardware Access Flag Enable */ 277#define CPU_CONTROL_FI_ENABLE 0x00200000 /* FI: Low interrupt latency */ 278#define CPU_CONTROL_UNAL_ENABLE 0x00400000 /* U: unaligned data access */ 279#define CPU_CONTROL_V6_EXTPAGE 0x00800000 /* XP: ARMv6 extended page tables */ 280#define CPU_CONTROL_V_ENABLE 0x01000000 /* VE: Interrupt vectors enable */ 281#define CPU_CONTROL_EX_BEND 0x02000000 /* EE: exception endianness */ 282#define CPU_CONTROL_L2_ENABLE 0x04000000 /* L2 Cache enabled */ 283#define CPU_CONTROL_NMFI 0x08000000 /* NMFI: Non maskable FIQ */ 284#define CPU_CONTROL_TR_ENABLE 0x10000000 /* TRE: TEX Remap*/ 285#define CPU_CONTROL_AF_ENABLE 0x20000000 /* AFE: Access Flag enable */ 286#define CPU_CONTROL_TE_ENABLE 0x40000000 /* TE: Thumb Exception enable */ 287 288#define CPU_CONTROL_IDC_ENABLE CPU_CONTROL_DC_ENABLE 289 290/* ARM11x6 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 291#define ARM11X6_AUXCTL_RS 0x00000001 /* return stack */ 292#define ARM11X6_AUXCTL_DB 0x00000002 /* dynamic branch prediction */ 293#define ARM11X6_AUXCTL_SB 0x00000004 /* static branch prediction */ 294#define ARM11X6_AUXCTL_TR 0x00000008 /* MicroTLB replacement strat. */ 295#define ARM11X6_AUXCTL_EX 0x00000010 /* exclusive L1/L2 cache */ 296#define ARM11X6_AUXCTL_RA 0x00000020 /* clean entire cache disable */ 297#define ARM11X6_AUXCTL_RV 0x00000040 /* block transfer cache disable */ 298#define ARM11X6_AUXCTL_CZ 0x00000080 /* restrict cache size */ 299 300/* ARM1136 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 301#define ARM1136_AUXCTL_PFI 0x80000000 /* PFI: partial FI mode. */ 302 /* This is an undocumented flag 303 * used to work around a cache bug 304 * in r0 steppings. See errata 305 * 364296. 306 */ 307/* ARM1176 Auxiliary Control Register (CP15 register 1, opcode2 1) */ 308#define ARM1176_AUXCTL_PHD 0x10000000 /* inst. prefetch halting disable */ 309#define ARM1176_AUXCTL_BFD 0x20000000 /* branch folding disable */ 310#define ARM1176_AUXCTL_FSD 0x40000000 /* force speculative ops disable */ 311#define ARM1176_AUXCTL_FIO 0x80000000 /* low intr latency override */ 312 313/* XScale Auxillary Control Register (CP15 register 1, opcode2 1) */ 314#define XSCALE_AUXCTL_K 0x00000001 /* dis. write buffer coalescing */ 315#define XSCALE_AUXCTL_P 0x00000002 /* ECC protect page table access */ 316/* Note: XSCale core 3 uses those for LLR DCcahce attributes */ 317#define XSCALE_AUXCTL_MD_WB_RA 0x00000000 /* mini-D$ wb, read-allocate */ 318#define XSCALE_AUXCTL_MD_WB_RWA 0x00000010 /* mini-D$ wb, read/write-allocate */ 319#define XSCALE_AUXCTL_MD_WT 0x00000020 /* mini-D$ wt, read-allocate */ 320#define XSCALE_AUXCTL_MD_MASK 0x00000030 321 322/* Xscale Core 3 only */ 323#define XSCALE_AUXCTL_LLR 0x00000400 /* Enable L2 for LLR Cache */ 324 325/* Marvell Extra Features Register (CP15 register 1, opcode2 0) */ 326#define MV_DC_REPLACE_LOCK 0x80000000 /* Replace DCache Lock */ 327#define MV_DC_STREAM_ENABLE 0x20000000 /* DCache Streaming Switch */ 328#define MV_WA_ENABLE 0x10000000 /* Enable Write Allocate */ 329#define MV_L2_PREFETCH_DISABLE 0x01000000 /* L2 Cache Prefetch Disable */ 330#define MV_L2_INV_EVICT_ERR 0x00800000 /* L2 Invalidates Uncorrectable Error Line Eviction */ 331#define MV_L2_ENABLE 0x00400000 /* L2 Cache enable */ 332#define MV_IC_REPLACE_LOCK 0x00080000 /* Replace ICache Lock */ 333#define MV_BGH_ENABLE 0x00040000 /* Branch Global History Register Enable */ 334#define MV_BTB_DISABLE 0x00020000 /* Branch Target Buffer Disable */ 335#define MV_L1_PARERR_ENABLE 0x00010000 /* L1 Parity Error Enable */ 336 337/* Cache type register definitions */ 338#define CPU_CT_ISIZE(x) ((x) & 0xfff) /* I$ info */ 339#define CPU_CT_DSIZE(x) (((x) >> 12) & 0xfff) /* D$ info */ 340#define CPU_CT_S (1U << 24) /* split cache */ 341#define CPU_CT_CTYPE(x) (((x) >> 25) & 0xf) /* cache type */ 342#define CPU_CT_FORMAT(x) ((x) >> 29) 343/* Cache type register definitions for ARM v7 */ 344#define CPU_CT_IMINLINE(x) ((x) & 0xf) /* I$ min line size */ 345#define CPU_CT_DMINLINE(x) (((x) >> 16) & 0xf) /* D$ min line size */ 346 347#define CPU_CT_CTYPE_WT 0 /* write-through */ 348#define CPU_CT_CTYPE_WB1 1 /* write-back, clean w/ read */ 349#define CPU_CT_CTYPE_WB2 2 /* w/b, clean w/ cp15,7 */ 350#define CPU_CT_CTYPE_WB6 6 /* w/b, cp15,7, lockdown fmt A */ 351#define CPU_CT_CTYPE_WB7 7 /* w/b, cp15,7, lockdown fmt B */ 352 353#define CPU_CT_xSIZE_LEN(x) ((x) & 0x3) /* line size */ 354#define CPU_CT_xSIZE_M (1U << 2) /* multiplier */ 355#define CPU_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x7) /* associativity */ 356#define CPU_CT_xSIZE_SIZE(x) (((x) >> 6) & 0x7) /* size */ 357 358#define CPU_CT_ARMV7 0x4 359/* ARM v7 Cache type definitions */ 360#define CPUV7_CT_CTYPE_WT (1U << 31) 361#define CPUV7_CT_CTYPE_WB (1 << 30) 362#define CPUV7_CT_CTYPE_RA (1 << 29) 363#define CPUV7_CT_CTYPE_WA (1 << 28) 364 365#define CPUV7_CT_xSIZE_LEN(x) ((x) & 0x7) /* line size */ 366#define CPUV7_CT_xSIZE_ASSOC(x) (((x) >> 3) & 0x3ff) /* associativity */ 367#define CPUV7_CT_xSIZE_SET(x) (((x) >> 13) & 0x7fff) /* num sets */ 368 369#define CPUV7_L2CTLR_NPROC_SHIFT 24 370#define CPUV7_L2CTLR_NPROC(r) ((((r) >> CPUV7_L2CTLR_NPROC_SHIFT) & 3) + 1) 371 372#define CPU_CLIDR_CTYPE(reg,x) (((reg) >> ((x) * 3)) & 0x7) 373#define CPU_CLIDR_LOUIS(reg) (((reg) >> 21) & 0x7) 374#define CPU_CLIDR_LOC(reg) (((reg) >> 24) & 0x7) 375#define CPU_CLIDR_LOUU(reg) (((reg) >> 27) & 0x7) 376 377#define CACHE_ICACHE 1 378#define CACHE_DCACHE 2 379#define CACHE_SEP_CACHE 3 380#define CACHE_UNI_CACHE 4 381 382/* Fault status register definitions */ 383#define FAULT_USER 0x10 384 385#define FAULT_ALIGN 0x001 /* Alignment Fault */ 386#define FAULT_DEBUG 0x002 /* Debug Event */ 387#define FAULT_ACCESS_L1 0x003 /* Access Bit (L1) */ 388#define FAULT_ICACHE 0x004 /* Instruction cache maintenance */ 389#define FAULT_TRAN_L1 0x005 /* Translation Fault (L1) */ 390#define FAULT_ACCESS_L2 0x006 /* Access Bit (L2) */ 391#define FAULT_TRAN_L2 0x007 /* Translation Fault (L2) */ 392#define FAULT_EA_PREC 0x008 /* External Abort */ 393#define FAULT_DOMAIN_L1 0x009 /* Domain Fault (L1) */ 394#define FAULT_DOMAIN_L2 0x00B /* Domain Fault (L2) */ 395#define FAULT_EA_TRAN_L1 0x00C /* External Translation Abort (L1) */ 396#define FAULT_PERM_L1 0x00D /* Permission Fault (L1) */ 397#define FAULT_EA_TRAN_L2 0x00E /* External Translation Abort (L2) */ 398#define FAULT_PERM_L2 0x00F /* Permission Fault (L2) */ 399#define FAULT_TLB_CONFLICT 0x010 /* TLB Conflict Abort */ 400#define FAULT_EA_IMPREC 0x016 /* Asynchronous External Abort */ 401#define FAULT_PE_IMPREC 0x018 /* Asynchronous Parity Error */ 402#define FAULT_PARITY 0x019 /* Parity Error */ 403#define FAULT_PE_TRAN_L1 0x01C /* Parity Error on Translation (L1) */ 404#define FAULT_PE_TRAN_L2 0x01E /* Parity Error on Translation (L2) */ 405 406#define FSR_TO_FAULT(fsr) (((fsr) & 0xF) | \ 407 ((((fsr) & (1 << 10)) >> (10 - 4)))) 408#define FSR_LPAE (1 << 9) /* LPAE indicator */ 409#define FSR_WNR (1 << 11) /* Write-not-Read access */ 410#define FSR_EXT (1 << 12) /* DECERR/SLVERR for external*/ 411#define FSR_CM (1 << 13) /* Cache maintenance fault */ 412 413/* 414 * Address of the vector page, low and high versions. 415 */ 416#ifndef __ASSEMBLER__ 417#define ARM_VECTORS_LOW 0x00000000U 418#define ARM_VECTORS_HIGH 0xffff0000U 419#else 420#define ARM_VECTORS_LOW 0 421#define ARM_VECTORS_HIGH 0xffff0000 422#endif 423 424/* 425 * ARM Instructions 426 * 427 * 3 3 2 2 2 428 * 1 0 9 8 7 0 429 * +-------+-------------------------------------------------------+ 430 * | cond | instruction dependant | 431 * |c c c c| | 432 * +-------+-------------------------------------------------------+ 433 */ 434 435#define INSN_SIZE 4 /* Always 4 bytes */ 436#define INSN_COND_MASK 0xf0000000 /* Condition mask */ 437#define INSN_COND_AL 0xe0000000 /* Always condition */ 438 439/* ARM register defines */ 440#define ARM_REG_SIZE 4 441#define ARM_REG_NUM_PC 15 442#define ARM_REG_NUM_LR 14 443#define ARM_REG_NUM_SP 13 444 445#define THUMB_INSN_SIZE 2 /* Some are 4 bytes. */ 446 447/* ARM Hypervisor Related Defines */ 448#define ARM_CP15_HDCR_HPMN 0x0000001f 449 450#endif /* !MACHINE_ARMREG_H */ 451