1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2014 Ruslan Bukin <br@bsdpad.com>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29/*
30 * Vybrid Family Enhanced Direct Memory Access Controller (eDMA)
31 * Chapter 21, Vybrid Reference Manual, Rev. 5, 07/2013
32 */
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/malloc.h>
40#include <sys/rman.h>
41#include <sys/timeet.h>
42#include <sys/timetc.h>
43#include <sys/watchdog.h>
44
45#include <dev/ofw/openfirm.h>
46#include <dev/ofw/ofw_bus.h>
47#include <dev/ofw/ofw_bus_subr.h>
48
49#include <machine/bus.h>
50#include <machine/cpu.h>
51#include <machine/intr.h>
52
53#include <arm/freescale/vybrid/vf_edma.h>
54#include <arm/freescale/vybrid/vf_dmamux.h>
55#include <arm/freescale/vybrid/vf_common.h>
56
57struct edma_channel {
58	uint32_t	enabled;
59	uint32_t	mux_num;
60	uint32_t	mux_src;
61	uint32_t	mux_chn;
62	uint32_t	(*ih) (void *, int);
63	void		*ih_user;
64};
65
66static struct edma_channel edma_map[EDMA_NUM_CHANNELS];
67
68static struct resource_spec edma_spec[] = {
69	{ SYS_RES_MEMORY,	0,	RF_ACTIVE },
70	{ SYS_RES_MEMORY,	1,	RF_ACTIVE }, /* TCD */
71	{ SYS_RES_IRQ,		0,	RF_ACTIVE }, /* Transfer complete */
72	{ SYS_RES_IRQ,		1,	RF_ACTIVE }, /* Error Interrupt */
73	{ -1, 0 }
74};
75
76static int
77edma_probe(device_t dev)
78{
79
80	if (!ofw_bus_status_okay(dev))
81		return (ENXIO);
82
83	if (!ofw_bus_is_compatible(dev, "fsl,mvf600-edma"))
84		return (ENXIO);
85
86	device_set_desc(dev, "Vybrid Family eDMA Controller");
87	return (BUS_PROBE_DEFAULT);
88}
89
90static void
91edma_transfer_complete_intr(void *arg)
92{
93	struct edma_channel *ch;
94	struct edma_softc *sc;
95	int interrupts;
96	int i;
97
98	sc = arg;
99
100	interrupts = READ4(sc, DMA_INT);
101	WRITE1(sc, DMA_CINT, CINT_CAIR);
102
103	for (i = 0; i < EDMA_NUM_CHANNELS; i++) {
104		if (interrupts & (0x1 << i)) {
105			ch = &edma_map[i];
106			if (ch->enabled == 1) {
107				if (ch->ih != NULL) {
108					ch->ih(ch->ih_user, i);
109				}
110			}
111		}
112	}
113}
114
115static void
116edma_err_intr(void *arg)
117{
118	struct edma_softc *sc;
119#if 0
120	int reg;
121#endif
122
123	sc = arg;
124
125	/* reg = */ READ4(sc, DMA_ERR);
126
127#if 0
128	device_printf(sc->dev, "DMA_ERR 0x%08x, ES 0x%08x\n",
129	    reg, READ4(sc, DMA_ES));
130#endif
131
132	WRITE1(sc, DMA_CERR, CERR_CAEI);
133}
134
135static int
136channel_free(struct edma_softc *sc, int chnum)
137{
138	struct edma_channel *ch;
139
140	ch = &edma_map[chnum];
141	ch->enabled = 0;
142
143	dmamux_configure(ch->mux_num, ch->mux_src, ch->mux_chn, 0);
144
145	return (0);
146}
147
148static int
149channel_configure(struct edma_softc *sc, int mux_grp, int mux_src)
150{
151	struct edma_channel *ch;
152	int channel_first;
153	int mux_num;
154	int chnum;
155	int i;
156
157	if ((sc->device_id == 0 && mux_grp == 1) ||	\
158	    (sc->device_id == 1 && mux_grp == 0)) {
159		channel_first = NCHAN_PER_MUX;
160		mux_num = (sc->device_id * 2) + 1;
161	} else {
162		channel_first = 0;
163		mux_num = sc->device_id * 2;
164	}
165
166	/* Take first unused eDMA channel */
167	ch = NULL;
168	for (i = channel_first; i < (channel_first + NCHAN_PER_MUX); i++) {
169		ch = &edma_map[i];
170		if (ch->enabled == 0) {
171			break;
172		}
173		ch = NULL;
174	}
175
176	if (ch == NULL) {
177		/* Can't find free channel */
178		return (-1);
179	}
180
181	chnum = i;
182
183	ch->enabled = 1;
184	ch->mux_num = mux_num;
185	ch->mux_src = mux_src;
186	ch->mux_chn = (chnum - channel_first);	/* 0 to 15 */
187
188	dmamux_configure(ch->mux_num, ch->mux_src, ch->mux_chn, 1);
189
190	return (chnum);
191}
192
193static int
194dma_stop(struct edma_softc *sc, int chnum)
195{
196	int reg;
197
198	reg = READ4(sc, DMA_ERQ);
199	reg &= ~(0x1 << chnum);
200	WRITE4(sc, DMA_ERQ, reg);
201
202	return (0);
203}
204
205static int
206dma_setup(struct edma_softc *sc, struct tcd_conf *tcd)
207{
208	struct edma_channel *ch;
209	int chnum;
210	int reg;
211
212	chnum = tcd->channel;
213
214	ch = &edma_map[chnum];
215	ch->ih = tcd->ih;
216	ch->ih_user = tcd->ih_user;
217
218	TCD_WRITE4(sc, DMA_TCDn_SADDR(chnum), tcd->saddr);
219	TCD_WRITE4(sc, DMA_TCDn_DADDR(chnum), tcd->daddr);
220
221	reg = (tcd->smod << TCD_ATTR_SMOD_SHIFT);
222	reg |= (tcd->dmod << TCD_ATTR_DMOD_SHIFT);
223	reg |= (tcd->ssize << TCD_ATTR_SSIZE_SHIFT);
224	reg |= (tcd->dsize << TCD_ATTR_DSIZE_SHIFT);
225	TCD_WRITE2(sc, DMA_TCDn_ATTR(chnum), reg);
226
227	TCD_WRITE2(sc, DMA_TCDn_SOFF(chnum), tcd->soff);
228	TCD_WRITE2(sc, DMA_TCDn_DOFF(chnum), tcd->doff);
229	TCD_WRITE4(sc, DMA_TCDn_SLAST(chnum), tcd->slast);
230	TCD_WRITE4(sc, DMA_TCDn_DLASTSGA(chnum), tcd->dlast_sga);
231	TCD_WRITE4(sc, DMA_TCDn_NBYTES_MLOFFYES(chnum), tcd->nbytes);
232
233	reg = tcd->nmajor; /* Current Major Iteration Count */
234	TCD_WRITE2(sc, DMA_TCDn_CITER_ELINKNO(chnum), reg);
235	TCD_WRITE2(sc, DMA_TCDn_BITER_ELINKNO(chnum), reg);
236
237	reg = (TCD_CSR_INTMAJOR);
238	if(tcd->majorelink == 1) {
239		reg |= TCD_CSR_MAJORELINK;
240		reg |= (tcd->majorelinkch << TCD_CSR_MAJORELINKCH_SHIFT);
241	}
242	TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg);
243
244	/* Enable requests */
245	reg = READ4(sc, DMA_ERQ);
246	reg |= (0x1 << chnum);
247	WRITE4(sc, DMA_ERQ, reg);
248
249	/* Enable error interrupts */
250	reg = READ4(sc, DMA_EEI);
251	reg |= (0x1 << chnum);
252	WRITE4(sc, DMA_EEI, reg);
253
254	return (0);
255}
256
257static int
258dma_request(struct edma_softc *sc, int chnum)
259{
260	int reg;
261
262	/* Start */
263	reg = TCD_READ2(sc, DMA_TCDn_CSR(chnum));
264	reg |= TCD_CSR_START;
265	TCD_WRITE2(sc, DMA_TCDn_CSR(chnum), reg);
266
267	return (0);
268}
269
270static int
271edma_attach(device_t dev)
272{
273	struct edma_softc *sc;
274	phandle_t node;
275	int dts_value;
276	int len;
277
278	sc = device_get_softc(dev);
279	sc->dev = dev;
280
281	if ((node = ofw_bus_get_node(sc->dev)) == -1)
282		return (ENXIO);
283
284	if ((len = OF_getproplen(node, "device-id")) <= 0)
285		return (ENXIO);
286
287	OF_getencprop(node, "device-id", &dts_value, len);
288	sc->device_id = dts_value;
289
290	sc->dma_stop = dma_stop;
291	sc->dma_setup = dma_setup;
292	sc->dma_request = dma_request;
293	sc->channel_configure = channel_configure;
294	sc->channel_free = channel_free;
295
296	if (bus_alloc_resources(dev, edma_spec, sc->res)) {
297		device_printf(dev, "could not allocate resources\n");
298		return (ENXIO);
299	}
300
301	/* Memory interface */
302	sc->bst = rman_get_bustag(sc->res[0]);
303	sc->bsh = rman_get_bushandle(sc->res[0]);
304	sc->bst_tcd = rman_get_bustag(sc->res[1]);
305	sc->bsh_tcd = rman_get_bushandle(sc->res[1]);
306
307	/* Setup interrupt handlers */
308	if (bus_setup_intr(dev, sc->res[2], INTR_TYPE_BIO | INTR_MPSAFE,
309		NULL, edma_transfer_complete_intr, sc, &sc->tc_ih)) {
310		device_printf(dev, "Unable to alloc DMA intr resource.\n");
311		return (ENXIO);
312	}
313
314	if (bus_setup_intr(dev, sc->res[3], INTR_TYPE_BIO | INTR_MPSAFE,
315		NULL, edma_err_intr, sc, &sc->err_ih)) {
316		device_printf(dev, "Unable to alloc DMA Err intr resource.\n");
317		return (ENXIO);
318	}
319
320	return (0);
321}
322
323static device_method_t edma_methods[] = {
324	DEVMETHOD(device_probe,		edma_probe),
325	DEVMETHOD(device_attach,	edma_attach),
326	{ 0, 0 }
327};
328
329static driver_t edma_driver = {
330	"edma",
331	edma_methods,
332	sizeof(struct edma_softc),
333};
334
335DRIVER_MODULE(edma, simplebus, edma_driver, 0, 0);
336