1/*-
2 * SPDX-License-Identifier: BSD-2-Clause
3 *
4 * Copyright (c) 2013 Ian Lepore <ian@freebsd.org>
5 * All rights reserved.
6 *
7 * Redistribution and use in source and binary forms, with or without
8 * modification, are permitted provided that the following conditions
9 * are met:
10 * 1. Redistributions of source code must retain the above copyright
11 *    notice, this list of conditions and the following disclaimer.
12 * 2. Redistributions in binary form must reproduce the above copyright
13 *    notice, this list of conditions and the following disclaimer in the
14 *    documentation and/or other materials provided with the distribution.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
19 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
26 * SUCH DAMAGE.
27 */
28
29#include "opt_platform.h"
30
31#include <sys/param.h>
32#include <sys/systm.h>
33#include <sys/reboot.h>
34#include <sys/devmap.h>
35
36#include <vm/vm.h>
37#include <vm/pmap.h>
38
39#include <machine/armreg.h>
40#include <machine/bus.h>
41#include <machine/cpu.h>
42#include <machine/machdep.h>
43
44#include <arm/freescale/imx/imx_machdep.h>
45#include <arm/freescale/imx/imx_wdogreg.h>
46
47SYSCTL_NODE(_hw, OID_AUTO, imx, CTLFLAG_RW | CTLFLAG_MPSAFE, NULL,
48    "i.MX container");
49
50static int last_reset_status;
51SYSCTL_UINT(_hw_imx, OID_AUTO, last_reset_status, CTLFLAG_RD,
52    &last_reset_status, 0, "Last reset status register");
53
54SYSCTL_STRING(_hw_imx, OID_AUTO, last_reset_reason, CTLFLAG_RD,
55    "unknown", 0, "Last reset reason");
56
57/*
58 * This code which manipulates the watchdog hardware is here to implement
59 * cpu_reset() because the watchdog is the only way for software to reset the
60 * chip.  Why here and not in imx_wdog.c?  Because there's no requirement that
61 * the watchdog driver be compiled in, but it's nice to be able to reboot even
62 * if it's not.
63 */
64void
65imx_wdog_cpu_reset(vm_offset_t wdcr_physaddr)
66{
67	volatile uint16_t cr, *pcr;
68
69	if ((pcr = devmap_ptov(wdcr_physaddr, sizeof(*pcr))) == NULL) {
70		printf("imx_wdog_cpu_reset(): "
71		    "cannot find control register... locking up now.");
72		for (;;)
73			cpu_spinwait();
74	}
75	cr = *pcr;
76
77	/*
78	 * If the watchdog hardware has been set up to trigger an external reset
79	 * signal on watchdog timeout, then we do software-requested rebooting
80	 * the same way, by asserting the external reset signal.
81	 *
82	 * Asserting external reset is supposed to result in some external
83	 * component asserting the POR pin on the SoC, possibly after adjusting
84	 * and stabilizing system voltages, or taking other system-wide reset
85	 * actions.  Just in case there is some kind of misconfiguration, we
86	 * hang out and do nothing for a full second, then continue on into
87	 * the code to assert a software reset as well.
88	 */
89	if (cr & WDOG_CR_WDT) {
90		cr &= ~WDOG_CR_WDA; /* Assert active-low ext reset bit. */
91		*pcr = cr;
92		DELAY(1000000);
93		printf("imx_wdog_cpu_reset(): "
94		    "External reset failed, trying internal cpu-reset\n");
95		DELAY(10000); /* Time for printf to appear */
96	}
97
98	/*
99	 * Imx6 erratum ERR004346 says the SRS bit has to be cleared twice
100	 * within the same cycle of the 32khz clock to reliably trigger the
101	 * reset.  Writing it 3 times in a row ensures at least 2 of the writes
102	 * happen in the same 32k clock cycle.
103	 */
104	cr &= ~WDOG_CR_SRS; /* Assert active-low software reset bit. */
105	*pcr = cr;
106	*pcr = cr;
107	*pcr = cr;
108
109	/* Reset happens on the next tick of the 32khz clock, wait for it. */
110	for (;;)
111		cpu_spinwait();
112}
113
114void
115imx_wdog_init_last_reset(vm_offset_t wdsr_phys)
116{
117	volatile uint16_t * psr;
118
119	if ((psr = devmap_ptov(wdsr_phys, sizeof(*psr))) == NULL)
120		return;
121	last_reset_status = *psr;
122	if (last_reset_status & WDOG_RSR_SFTW) {
123		sysctl___hw_imx_last_reset_reason.oid_arg1 = "SoftwareReset";
124	} else if (last_reset_status & WDOG_RSR_TOUT) {
125		sysctl___hw_imx_last_reset_reason.oid_arg1 = "WatchdogTimeout";
126	} else if (last_reset_status & WDOG_RSR_POR) {
127		sysctl___hw_imx_last_reset_reason.oid_arg1 = "PowerOnReset";
128	}
129}
130