1/*- 2 * Copyright (c) 2012, 2013 The FreeBSD Foundation 3 * 4 * This software was developed by Oleksandr Rybalko under sponsorship 5 * from the FreeBSD Foundation. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * Freescale i.MX515 GPIO driver. 31 */ 32 33#include <sys/cdefs.h> 34#include "opt_platform.h" 35 36#include <sys/param.h> 37#include <sys/systm.h> 38#include <sys/bus.h> 39 40#include <sys/kernel.h> 41#include <sys/module.h> 42#include <sys/rman.h> 43#include <sys/lock.h> 44#include <sys/mutex.h> 45#include <sys/gpio.h> 46#include <sys/proc.h> 47 48#include <machine/bus.h> 49#include <machine/intr.h> 50#include <machine/resource.h> 51 52#include <dev/gpio/gpiobusvar.h> 53#include <dev/ofw/openfirm.h> 54#include <dev/ofw/ofw_bus.h> 55#include <dev/ofw/ofw_bus_subr.h> 56 57#if defined(__aarch64__) 58#define IMX_ENABLE_CLOCKS 59#endif 60 61#ifdef IMX_ENABLE_CLOCKS 62#include <dev/clk/clk.h> 63#endif 64 65#include "gpio_if.h" 66 67#ifdef INTRNG 68#include "pic_if.h" 69#endif 70 71#define WRITE4(_sc, _r, _v) \ 72 bus_space_write_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r), (_v)) 73#define READ4(_sc, _r) \ 74 bus_space_read_4((_sc)->sc_iot, (_sc)->sc_ioh, (_r)) 75#define SET4(_sc, _r, _m) \ 76 WRITE4((_sc), (_r), READ4((_sc), (_r)) | (_m)) 77#define CLEAR4(_sc, _r, _m) \ 78 WRITE4((_sc), (_r), READ4((_sc), (_r)) & ~(_m)) 79 80/* Registers definition for Freescale i.MX515 GPIO controller */ 81 82#define IMX_GPIO_DR_REG 0x000 /* Pin Data */ 83#define IMX_GPIO_OE_REG 0x004 /* Set Pin Output */ 84#define IMX_GPIO_PSR_REG 0x008 /* Pad Status */ 85#define IMX_GPIO_ICR1_REG 0x00C /* Interrupt Configuration */ 86#define IMX_GPIO_ICR2_REG 0x010 /* Interrupt Configuration */ 87#define GPIO_ICR_COND_LOW 0 88#define GPIO_ICR_COND_HIGH 1 89#define GPIO_ICR_COND_RISE 2 90#define GPIO_ICR_COND_FALL 3 91#define GPIO_ICR_COND_MASK 0x3 92#define IMX_GPIO_IMR_REG 0x014 /* Interrupt Mask Register */ 93#define IMX_GPIO_ISR_REG 0x018 /* Interrupt Status Register */ 94#define IMX_GPIO_EDGE_REG 0x01C /* Edge Detect Register */ 95 96#ifdef INTRNG 97#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT | \ 98 GPIO_INTR_LEVEL_LOW | GPIO_INTR_LEVEL_HIGH | GPIO_INTR_EDGE_RISING | \ 99 GPIO_INTR_EDGE_FALLING | GPIO_INTR_EDGE_BOTH) 100#else 101#define DEFAULT_CAPS (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT) 102#endif 103 104#define NGPIO 32 105 106#ifdef INTRNG 107struct gpio_irqsrc { 108 struct intr_irqsrc gi_isrc; 109 u_int gi_irq; 110 uint32_t gi_mode; 111}; 112#endif 113 114struct imx51_gpio_softc { 115 device_t dev; 116 device_t sc_busdev; 117 struct mtx sc_mtx; 118 struct resource *sc_res[3]; /* 1 x mem, 2 x IRQ */ 119 void *gpio_ih[2]; 120 bus_space_tag_t sc_iot; 121 bus_space_handle_t sc_ioh; 122 int gpio_npins; 123 struct gpio_pin gpio_pins[NGPIO]; 124#ifdef INTRNG 125 struct gpio_irqsrc gpio_pic_irqsrc[NGPIO]; 126#endif 127#ifdef IMX_ENABLE_CLOCKS 128 clk_t clk; 129#endif 130}; 131 132static struct ofw_compat_data compat_data[] = { 133 {"fsl,imx8mq-gpio", 1}, 134 {"fsl,imx6q-gpio", 1}, 135 {"fsl,imx53-gpio", 1}, 136 {"fsl,imx51-gpio", 1}, 137 {NULL, 0} 138}; 139 140static struct resource_spec imx_gpio_spec[] = { 141 { SYS_RES_MEMORY, 0, RF_ACTIVE }, 142 { SYS_RES_IRQ, 0, RF_ACTIVE }, 143 { SYS_RES_IRQ, 1, RF_ACTIVE }, 144 { -1, 0 } 145}; 146#define FIRST_IRQRES 1 147#define NUM_IRQRES 2 148 149/* 150 * Helpers 151 */ 152static void imx51_gpio_pin_configure(struct imx51_gpio_softc *, 153 struct gpio_pin *, uint32_t); 154 155/* 156 * Driver stuff 157 */ 158static int imx51_gpio_probe(device_t); 159static int imx51_gpio_attach(device_t); 160static int imx51_gpio_detach(device_t); 161 162/* 163 * GPIO interface 164 */ 165static device_t imx51_gpio_get_bus(device_t); 166static int imx51_gpio_pin_max(device_t, int *); 167static int imx51_gpio_pin_getcaps(device_t, uint32_t, uint32_t *); 168static int imx51_gpio_pin_getflags(device_t, uint32_t, uint32_t *); 169static int imx51_gpio_pin_getname(device_t, uint32_t, char *); 170static int imx51_gpio_pin_setflags(device_t, uint32_t, uint32_t); 171static int imx51_gpio_pin_set(device_t, uint32_t, unsigned int); 172static int imx51_gpio_pin_get(device_t, uint32_t, unsigned int *); 173static int imx51_gpio_pin_toggle(device_t, uint32_t pin); 174 175#ifdef INTRNG 176static int 177gpio_pic_map_fdt(struct imx51_gpio_softc *sc, struct intr_map_data_fdt *daf, 178 u_int *irqp, uint32_t *modep) 179{ 180 u_int irq; 181 uint32_t mode; 182 183 /* 184 * From devicetree/bindings/gpio/fsl-imx-gpio.txt: 185 * #interrupt-cells: 2. The first cell is the GPIO number. The second 186 * cell bits[3:0] is used to specify trigger type and level flags: 187 * 1 = low-to-high edge triggered. 188 * 2 = high-to-low edge triggered. 189 * 4 = active high level-sensitive. 190 * 8 = active low level-sensitive. 191 * We can do any single one of these modes, and also edge low+high 192 * (i.e., trigger on both edges); other combinations are not supported. 193 */ 194 195 if (daf->ncells != 2) { 196 device_printf(sc->dev, "Invalid #interrupt-cells\n"); 197 return (EINVAL); 198 } 199 200 irq = daf->cells[0]; 201 if (irq >= sc->gpio_npins) { 202 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 203 return (EINVAL); 204 } 205 switch (daf->cells[1]) { 206 case 1: 207 mode = GPIO_INTR_EDGE_RISING; 208 break; 209 case 2: 210 mode = GPIO_INTR_EDGE_FALLING; 211 break; 212 case 3: 213 mode = GPIO_INTR_EDGE_BOTH; 214 break; 215 case 4: 216 mode = GPIO_INTR_LEVEL_HIGH; 217 break; 218 case 8: 219 mode = GPIO_INTR_LEVEL_LOW; 220 break; 221 default: 222 device_printf(sc->dev, "Unsupported interrupt mode 0x%2x\n", 223 daf->cells[1]); 224 return (ENOTSUP); 225 } 226 *irqp = irq; 227 if (modep != NULL) 228 *modep = mode; 229 return (0); 230} 231 232static int 233gpio_pic_map_gpio(struct imx51_gpio_softc *sc, struct intr_map_data_gpio *dag, 234 u_int *irqp, uint32_t *modep) 235{ 236 u_int irq; 237 238 irq = dag->gpio_pin_num; 239 if (irq >= sc->gpio_npins) { 240 device_printf(sc->dev, "Invalid interrupt number %u\n", irq); 241 return (EINVAL); 242 } 243 244 switch (dag->gpio_intr_mode) { 245 case GPIO_INTR_LEVEL_LOW: 246 case GPIO_INTR_LEVEL_HIGH: 247 case GPIO_INTR_EDGE_RISING: 248 case GPIO_INTR_EDGE_FALLING: 249 case GPIO_INTR_EDGE_BOTH: 250 break; 251 default: 252 device_printf(sc->dev, "Unsupported interrupt mode 0x%8x\n", 253 dag->gpio_intr_mode); 254 return (EINVAL); 255 } 256 257 *irqp = irq; 258 if (modep != NULL) 259 *modep = dag->gpio_intr_mode; 260 return (0); 261} 262 263static int 264gpio_pic_map(struct imx51_gpio_softc *sc, struct intr_map_data *data, 265 u_int *irqp, uint32_t *modep) 266{ 267 268 switch (data->type) { 269 case INTR_MAP_DATA_FDT: 270 return (gpio_pic_map_fdt(sc, (struct intr_map_data_fdt *)data, 271 irqp, modep)); 272 case INTR_MAP_DATA_GPIO: 273 return (gpio_pic_map_gpio(sc, (struct intr_map_data_gpio *)data, 274 irqp, modep)); 275 default: 276 return (ENOTSUP); 277 } 278} 279 280static int 281gpio_pic_map_intr(device_t dev, struct intr_map_data *data, 282 struct intr_irqsrc **isrcp) 283{ 284 int error; 285 u_int irq; 286 struct imx51_gpio_softc *sc; 287 288 sc = device_get_softc(dev); 289 error = gpio_pic_map(sc, data, &irq, NULL); 290 if (error == 0) 291 *isrcp = &sc->gpio_pic_irqsrc[irq].gi_isrc; 292 return (error); 293} 294 295static int 296gpio_pic_teardown_intr(device_t dev, struct intr_irqsrc *isrc, 297 struct resource *res, struct intr_map_data *data) 298{ 299 struct imx51_gpio_softc *sc; 300 struct gpio_irqsrc *gi; 301 302 sc = device_get_softc(dev); 303 if (isrc->isrc_handlers == 0) { 304 gi = (struct gpio_irqsrc *)isrc; 305 gi->gi_mode = GPIO_INTR_CONFORM; 306 307 // XXX Not sure this is necessary 308 mtx_lock_spin(&sc->sc_mtx); 309 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << gi->gi_irq)); 310 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << gi->gi_irq)); 311 mtx_unlock_spin(&sc->sc_mtx); 312 } 313 return (0); 314} 315 316static int 317gpio_pic_setup_intr(device_t dev, struct intr_irqsrc *isrc, 318 struct resource *res, struct intr_map_data *data) 319{ 320 struct imx51_gpio_softc *sc; 321 struct gpio_irqsrc *gi; 322 int error; 323 u_int icfg, irq, reg, shift, wrk; 324 uint32_t mode; 325 326 if (data == NULL) 327 return (ENOTSUP); 328 329 sc = device_get_softc(dev); 330 gi = (struct gpio_irqsrc *)isrc; 331 332 /* Get config for interrupt. */ 333 error = gpio_pic_map(sc, data, &irq, &mode); 334 if (error != 0) 335 return (error); 336 if (gi->gi_irq != irq) 337 return (EINVAL); 338 339 /* Compare config if this is not first setup. */ 340 if (isrc->isrc_handlers != 0) 341 return (gi->gi_mode == mode ? 0 : EINVAL); 342 gi->gi_mode = mode; 343 344 /* 345 * To interrupt on both edges we have to use the EDGE register. The 346 * manual says it only exists for backwards compatibilty with older imx 347 * chips, but it's also the only way to configure interrupting on both 348 * edges. If the EDGE bit is on, the corresponding ICRn bit is ignored. 349 */ 350 mtx_lock_spin(&sc->sc_mtx); 351 if (mode == GPIO_INTR_EDGE_BOTH) { 352 SET4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 353 } else { 354 CLEAR4(sc, IMX_GPIO_EDGE_REG, (1u << irq)); 355 switch (mode) { 356 default: 357 /* silence warnings; default can't actually happen. */ 358 /* FALLTHROUGH */ 359 case GPIO_INTR_LEVEL_LOW: 360 icfg = GPIO_ICR_COND_LOW; 361 break; 362 case GPIO_INTR_LEVEL_HIGH: 363 icfg = GPIO_ICR_COND_HIGH; 364 break; 365 case GPIO_INTR_EDGE_RISING: 366 icfg = GPIO_ICR_COND_RISE; 367 break; 368 case GPIO_INTR_EDGE_FALLING: 369 icfg = GPIO_ICR_COND_FALL; 370 break; 371 } 372 if (irq < 16) { 373 reg = IMX_GPIO_ICR1_REG; 374 shift = 2 * irq; 375 } else { 376 reg = IMX_GPIO_ICR2_REG; 377 shift = 2 * (irq - 16); 378 } 379 wrk = READ4(sc, reg); 380 wrk &= ~(GPIO_ICR_COND_MASK << shift); 381 wrk |= icfg << shift; 382 WRITE4(sc, reg, wrk); 383 } 384 WRITE4(sc, IMX_GPIO_ISR_REG, (1u << irq)); 385 SET4(sc, IMX_GPIO_IMR_REG, (1u << irq)); 386 mtx_unlock_spin(&sc->sc_mtx); 387 388 return (0); 389} 390 391/* 392 * this is mask_intr 393 */ 394static void 395gpio_pic_disable_intr(device_t dev, struct intr_irqsrc *isrc) 396{ 397 struct imx51_gpio_softc *sc; 398 u_int irq; 399 400 sc = device_get_softc(dev); 401 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 402 403 mtx_lock_spin(&sc->sc_mtx); 404 CLEAR4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 405 mtx_unlock_spin(&sc->sc_mtx); 406} 407 408/* 409 * this is unmask_intr 410 */ 411static void 412gpio_pic_enable_intr(device_t dev, struct intr_irqsrc *isrc) 413{ 414 struct imx51_gpio_softc *sc; 415 u_int irq; 416 417 sc = device_get_softc(dev); 418 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 419 420 mtx_lock_spin(&sc->sc_mtx); 421 SET4(sc, IMX_GPIO_IMR_REG, (1U << irq)); 422 mtx_unlock_spin(&sc->sc_mtx); 423} 424 425static void 426gpio_pic_post_filter(device_t dev, struct intr_irqsrc *isrc) 427{ 428 struct imx51_gpio_softc *sc; 429 u_int irq; 430 431 sc = device_get_softc(dev); 432 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 433 434 arm_irq_memory_barrier(0); 435 /* EOI. W1C reg so no r-m-w, no locking needed. */ 436 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 437} 438 439static void 440gpio_pic_post_ithread(device_t dev, struct intr_irqsrc *isrc) 441{ 442 struct imx51_gpio_softc *sc; 443 u_int irq; 444 445 sc = device_get_softc(dev); 446 irq = ((struct gpio_irqsrc *)isrc)->gi_irq; 447 448 arm_irq_memory_barrier(0); 449 /* EOI. W1C reg so no r-m-w, no locking needed. */ 450 WRITE4(sc, IMX_GPIO_ISR_REG, (1U << irq)); 451 gpio_pic_enable_intr(dev, isrc); 452} 453 454static void 455gpio_pic_pre_ithread(device_t dev, struct intr_irqsrc *isrc) 456{ 457 gpio_pic_disable_intr(dev, isrc); 458} 459 460static int 461gpio_pic_filter(void *arg) 462{ 463 struct imx51_gpio_softc *sc; 464 struct intr_irqsrc *isrc; 465 uint32_t i, interrupts; 466 467 sc = arg; 468 mtx_lock_spin(&sc->sc_mtx); 469 interrupts = READ4(sc, IMX_GPIO_ISR_REG) & READ4(sc, IMX_GPIO_IMR_REG); 470 mtx_unlock_spin(&sc->sc_mtx); 471 472 for (i = 0; interrupts != 0; i++, interrupts >>= 1) { 473 if ((interrupts & 0x1) == 0) 474 continue; 475 isrc = &sc->gpio_pic_irqsrc[i].gi_isrc; 476 if (intr_isrc_dispatch(isrc, curthread->td_intr_frame) != 0) { 477 gpio_pic_disable_intr(sc->dev, isrc); 478 gpio_pic_post_filter(sc->dev, isrc); 479 device_printf(sc->dev, "Stray irq %u disabled\n", i); 480 } 481 } 482 483 return (FILTER_HANDLED); 484} 485 486/* 487 * Initialize our isrcs and register them with intrng. 488 */ 489static int 490gpio_pic_register_isrcs(struct imx51_gpio_softc *sc) 491{ 492 int error; 493 uint32_t irq; 494 const char *name; 495 496 name = device_get_nameunit(sc->dev); 497 for (irq = 0; irq < NGPIO; irq++) { 498 sc->gpio_pic_irqsrc[irq].gi_irq = irq; 499 sc->gpio_pic_irqsrc[irq].gi_mode = GPIO_INTR_CONFORM; 500 501 error = intr_isrc_register(&sc->gpio_pic_irqsrc[irq].gi_isrc, 502 sc->dev, 0, "%s,%u", name, irq); 503 if (error != 0) { 504 /* XXX call intr_isrc_deregister() */ 505 device_printf(sc->dev, "%s failed", __func__); 506 return (error); 507 } 508 } 509 return (0); 510} 511#endif 512 513/* 514 * 515 */ 516static void 517imx51_gpio_pin_configure(struct imx51_gpio_softc *sc, struct gpio_pin *pin, 518 unsigned int flags) 519{ 520 u_int newflags, pad; 521 522 mtx_lock_spin(&sc->sc_mtx); 523 524 /* 525 * Manage input/output; other flags not supported yet (maybe not ever, 526 * since we have no connection to the pad config registers from here). 527 * 528 * When setting a pin to output, honor the PRESET_[LOW,HIGH] flags if 529 * present. Otherwise, for glitchless transitions on pins with pulls, 530 * read the current state of the pad and preset the DR register to drive 531 * the current value onto the pin before enabling the pin for output. 532 * 533 * Note that changes to pin->gp_flags must be acccumulated in newflags 534 * and stored with a single writeback to gp_flags at the end, to enable 535 * unlocked reads of that value elsewhere. This is only about unlocked 536 * access to gp_flags from elsewhere; we still use locking in this 537 * function to protect r-m-w access to the hardware registers. 538 */ 539 if (flags & (GPIO_PIN_INPUT | GPIO_PIN_OUTPUT)) { 540 newflags = pin->gp_flags & ~(GPIO_PIN_INPUT | GPIO_PIN_OUTPUT); 541 if (flags & GPIO_PIN_OUTPUT) { 542 if (flags & GPIO_PIN_PRESET_LOW) { 543 pad = 0; 544 } else if (flags & GPIO_PIN_PRESET_HIGH) { 545 pad = 1; 546 } else { 547 if (flags & GPIO_PIN_OPENDRAIN) 548 pad = READ4(sc, IMX_GPIO_PSR_REG); 549 else 550 pad = READ4(sc, IMX_GPIO_DR_REG); 551 pad = (pad >> pin->gp_pin) & 1; 552 } 553 newflags |= GPIO_PIN_OUTPUT; 554 SET4(sc, IMX_GPIO_DR_REG, (pad << pin->gp_pin)); 555 SET4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 556 } else { 557 newflags |= GPIO_PIN_INPUT; 558 CLEAR4(sc, IMX_GPIO_OE_REG, (1U << pin->gp_pin)); 559 } 560 pin->gp_flags = newflags; 561 } 562 563 mtx_unlock_spin(&sc->sc_mtx); 564} 565 566static device_t 567imx51_gpio_get_bus(device_t dev) 568{ 569 struct imx51_gpio_softc *sc; 570 571 sc = device_get_softc(dev); 572 573 return (sc->sc_busdev); 574} 575 576static int 577imx51_gpio_pin_max(device_t dev, int *maxpin) 578{ 579 struct imx51_gpio_softc *sc; 580 581 sc = device_get_softc(dev); 582 *maxpin = sc->gpio_npins - 1; 583 584 return (0); 585} 586 587static int 588imx51_gpio_pin_getcaps(device_t dev, uint32_t pin, uint32_t *caps) 589{ 590 struct imx51_gpio_softc *sc; 591 592 sc = device_get_softc(dev); 593 594 if (pin >= sc->gpio_npins) 595 return (EINVAL); 596 597 *caps = sc->gpio_pins[pin].gp_caps; 598 599 return (0); 600} 601 602static int 603imx51_gpio_pin_getflags(device_t dev, uint32_t pin, uint32_t *flags) 604{ 605 struct imx51_gpio_softc *sc; 606 607 sc = device_get_softc(dev); 608 609 if (pin >= sc->gpio_npins) 610 return (EINVAL); 611 612 *flags = sc->gpio_pins[pin].gp_flags; 613 614 return (0); 615} 616 617static int 618imx51_gpio_pin_getname(device_t dev, uint32_t pin, char *name) 619{ 620 struct imx51_gpio_softc *sc; 621 622 sc = device_get_softc(dev); 623 if (pin >= sc->gpio_npins) 624 return (EINVAL); 625 626 mtx_lock_spin(&sc->sc_mtx); 627 memcpy(name, sc->gpio_pins[pin].gp_name, GPIOMAXNAME); 628 mtx_unlock_spin(&sc->sc_mtx); 629 630 return (0); 631} 632 633static int 634imx51_gpio_pin_setflags(device_t dev, uint32_t pin, uint32_t flags) 635{ 636 struct imx51_gpio_softc *sc; 637 638 sc = device_get_softc(dev); 639 640 if (pin >= sc->gpio_npins) 641 return (EINVAL); 642 643 imx51_gpio_pin_configure(sc, &sc->gpio_pins[pin], flags); 644 645 return (0); 646} 647 648static int 649imx51_gpio_pin_set(device_t dev, uint32_t pin, unsigned int value) 650{ 651 struct imx51_gpio_softc *sc; 652 653 sc = device_get_softc(dev); 654 655 if (pin >= sc->gpio_npins) 656 return (EINVAL); 657 658 mtx_lock_spin(&sc->sc_mtx); 659 if (value) 660 SET4(sc, IMX_GPIO_DR_REG, (1U << pin)); 661 else 662 CLEAR4(sc, IMX_GPIO_DR_REG, (1U << pin)); 663 mtx_unlock_spin(&sc->sc_mtx); 664 665 return (0); 666} 667 668static int 669imx51_gpio_pin_get(device_t dev, uint32_t pin, unsigned int *val) 670{ 671 struct imx51_gpio_softc *sc; 672 673 sc = device_get_softc(dev); 674 675 if (pin >= sc->gpio_npins) 676 return (EINVAL); 677 678 /* 679 * Normally a pin set for output can be read by reading the DR reg which 680 * indicates what value is being driven to that pin. The exception is 681 * pins configured for open-drain mode, in which case we have to read 682 * the pad status register in case the pin is being driven externally. 683 * Doing so requires that the SION bit be configured in pinmux, which 684 * isn't the case for most normal gpio pins, so only try to read via PSR 685 * if the OPENDRAIN flag is set, and it's the user's job to correctly 686 * configure SION along with open-drain output mode for those pins. 687 */ 688 if (sc->gpio_pins[pin].gp_flags & GPIO_PIN_OPENDRAIN) 689 *val = (READ4(sc, IMX_GPIO_PSR_REG) >> pin) & 1; 690 else 691 *val = (READ4(sc, IMX_GPIO_DR_REG) >> pin) & 1; 692 693 return (0); 694} 695 696static int 697imx51_gpio_pin_toggle(device_t dev, uint32_t pin) 698{ 699 struct imx51_gpio_softc *sc; 700 701 sc = device_get_softc(dev); 702 703 if (pin >= sc->gpio_npins) 704 return (EINVAL); 705 706 mtx_lock_spin(&sc->sc_mtx); 707 WRITE4(sc, IMX_GPIO_DR_REG, 708 (READ4(sc, IMX_GPIO_DR_REG) ^ (1U << pin))); 709 mtx_unlock_spin(&sc->sc_mtx); 710 711 return (0); 712} 713 714static int 715imx51_gpio_pin_access_32(device_t dev, uint32_t first_pin, uint32_t clear_pins, 716 uint32_t change_pins, uint32_t *orig_pins) 717{ 718 struct imx51_gpio_softc *sc; 719 720 if (first_pin != 0) 721 return (EINVAL); 722 723 sc = device_get_softc(dev); 724 725 if (orig_pins != NULL) 726 *orig_pins = READ4(sc, IMX_GPIO_DR_REG); 727 728 if ((clear_pins | change_pins) != 0) { 729 mtx_lock_spin(&sc->sc_mtx); 730 WRITE4(sc, IMX_GPIO_DR_REG, 731 (READ4(sc, IMX_GPIO_DR_REG) & ~clear_pins) ^ change_pins); 732 mtx_unlock_spin(&sc->sc_mtx); 733 } 734 735 return (0); 736} 737 738static int 739imx51_gpio_pin_config_32(device_t dev, uint32_t first_pin, uint32_t num_pins, 740 uint32_t *pin_flags) 741{ 742 struct imx51_gpio_softc *sc; 743 u_int i; 744 uint32_t bit, drclr, drset, flags, oeclr, oeset, pads; 745 746 sc = device_get_softc(dev); 747 748 if (first_pin != 0 || num_pins > sc->gpio_npins) 749 return (EINVAL); 750 751 drclr = drset = oeclr = oeset = 0; 752 pads = READ4(sc, IMX_GPIO_DR_REG); 753 754 for (i = 0; i < num_pins; ++i) { 755 bit = 1u << i; 756 flags = pin_flags[i]; 757 if (flags & GPIO_PIN_INPUT) { 758 oeclr |= bit; 759 } else if (flags & GPIO_PIN_OUTPUT) { 760 oeset |= bit; 761 if (flags & GPIO_PIN_PRESET_LOW) 762 drclr |= bit; 763 else if (flags & GPIO_PIN_PRESET_HIGH) 764 drset |= bit; 765 else /* Drive whatever it's now pulled to. */ 766 drset |= pads & bit; 767 } 768 } 769 770 mtx_lock_spin(&sc->sc_mtx); 771 WRITE4(sc, IMX_GPIO_DR_REG, 772 (READ4(sc, IMX_GPIO_DR_REG) & ~drclr) | drset); 773 WRITE4(sc, IMX_GPIO_OE_REG, 774 (READ4(sc, IMX_GPIO_OE_REG) & ~oeclr) | oeset); 775 mtx_unlock_spin(&sc->sc_mtx); 776 777 return (0); 778} 779 780static int 781imx51_gpio_probe(device_t dev) 782{ 783 784 if (!ofw_bus_status_okay(dev)) 785 return (ENXIO); 786 787 if (ofw_bus_search_compatible(dev, compat_data)->ocd_data != 0) { 788 device_set_desc(dev, "Freescale i.MX GPIO Controller"); 789 return (BUS_PROBE_DEFAULT); 790 } 791 792 return (ENXIO); 793} 794 795static int 796imx51_gpio_attach(device_t dev) 797{ 798 struct imx51_gpio_softc *sc; 799 int i, irq, unit; 800#ifdef IMX_ENABLE_CLOCKS 801 int err; 802#endif 803 804 sc = device_get_softc(dev); 805 sc->dev = dev; 806 sc->gpio_npins = NGPIO; 807 808 mtx_init(&sc->sc_mtx, device_get_nameunit(sc->dev), NULL, MTX_SPIN); 809 810#ifdef IMX_ENABLE_CLOCKS 811 if (clk_get_by_ofw_index(sc->dev, 0, 0, &sc->clk) != 0) { 812 device_printf(dev, "could not get clock"); 813 return (ENOENT); 814 } 815 816 err = clk_enable(sc->clk); 817 if (err != 0) { 818 device_printf(sc->dev, "could not enable ipg clock\n"); 819 return (err); 820 } 821#endif 822 823 if (bus_alloc_resources(dev, imx_gpio_spec, sc->sc_res)) { 824 device_printf(dev, "could not allocate resources\n"); 825 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 826 mtx_destroy(&sc->sc_mtx); 827 return (ENXIO); 828 } 829 830 sc->sc_iot = rman_get_bustag(sc->sc_res[0]); 831 sc->sc_ioh = rman_get_bushandle(sc->sc_res[0]); 832 /* 833 * Mask off all interrupts in hardware, then set up interrupt handling. 834 */ 835 WRITE4(sc, IMX_GPIO_IMR_REG, 0); 836 for (irq = 0; irq < 2; irq++) { 837#ifdef INTRNG 838 if ((bus_setup_intr(dev, sc->sc_res[1 + irq], INTR_TYPE_CLK, 839 gpio_pic_filter, NULL, sc, &sc->gpio_ih[irq]))) { 840 device_printf(dev, 841 "WARNING: unable to register interrupt handler\n"); 842 imx51_gpio_detach(dev); 843 return (ENXIO); 844 } 845#endif 846 } 847 848 unit = device_get_unit(dev); 849 for (i = 0; i < sc->gpio_npins; i++) { 850 sc->gpio_pins[i].gp_pin = i; 851 sc->gpio_pins[i].gp_caps = DEFAULT_CAPS; 852 sc->gpio_pins[i].gp_flags = 853 (READ4(sc, IMX_GPIO_OE_REG) & (1U << i)) ? GPIO_PIN_OUTPUT : 854 GPIO_PIN_INPUT; 855 snprintf(sc->gpio_pins[i].gp_name, GPIOMAXNAME, 856 "GPIO%d_IO%02d", unit + 1, i); 857 } 858 859#ifdef INTRNG 860 gpio_pic_register_isrcs(sc); 861 intr_pic_register(dev, OF_xref_from_node(ofw_bus_get_node(dev))); 862#endif 863 sc->sc_busdev = gpiobus_attach_bus(dev); 864 865 if (sc->sc_busdev == NULL) { 866 imx51_gpio_detach(dev); 867 return (ENXIO); 868 } 869 870 return (0); 871} 872 873static int 874imx51_gpio_detach(device_t dev) 875{ 876 int irq; 877 struct imx51_gpio_softc *sc; 878#ifdef IMX_ENABLE_CLOCKS 879 int error; 880#endif 881 882 sc = device_get_softc(dev); 883 884#ifdef IMX_ENABLE_CLOCKS 885 error = clk_disable(sc->clk); 886 if (error != 0) { 887 device_printf(sc->dev, "could not disable ipg clock\n"); 888 return (error); 889 } 890#endif 891 892 gpiobus_detach_bus(dev); 893 for (irq = 0; irq < NUM_IRQRES; irq++) { 894 if (sc->gpio_ih[irq]) 895 bus_teardown_intr(dev, sc->sc_res[irq + FIRST_IRQRES], 896 sc->gpio_ih[irq]); 897 } 898 bus_release_resources(dev, imx_gpio_spec, sc->sc_res); 899 mtx_destroy(&sc->sc_mtx); 900 901 return(0); 902} 903 904static phandle_t 905imx51_gpio_get_node(device_t bus, device_t dev) 906{ 907 /* 908 * Share controller node with gpiobus device 909 */ 910 return ofw_bus_get_node(bus); 911} 912 913static device_method_t imx51_gpio_methods[] = { 914 DEVMETHOD(device_probe, imx51_gpio_probe), 915 DEVMETHOD(device_attach, imx51_gpio_attach), 916 DEVMETHOD(device_detach, imx51_gpio_detach), 917 918#ifdef INTRNG 919 /* Interrupt controller interface */ 920 DEVMETHOD(pic_disable_intr, gpio_pic_disable_intr), 921 DEVMETHOD(pic_enable_intr, gpio_pic_enable_intr), 922 DEVMETHOD(pic_map_intr, gpio_pic_map_intr), 923 DEVMETHOD(pic_setup_intr, gpio_pic_setup_intr), 924 DEVMETHOD(pic_teardown_intr, gpio_pic_teardown_intr), 925 DEVMETHOD(pic_post_filter, gpio_pic_post_filter), 926 DEVMETHOD(pic_post_ithread, gpio_pic_post_ithread), 927 DEVMETHOD(pic_pre_ithread, gpio_pic_pre_ithread), 928#endif 929 930 /* OFW methods */ 931 DEVMETHOD(ofw_bus_get_node, imx51_gpio_get_node), 932 933 /* GPIO protocol */ 934 DEVMETHOD(gpio_get_bus, imx51_gpio_get_bus), 935 DEVMETHOD(gpio_pin_max, imx51_gpio_pin_max), 936 DEVMETHOD(gpio_pin_getname, imx51_gpio_pin_getname), 937 DEVMETHOD(gpio_pin_getflags, imx51_gpio_pin_getflags), 938 DEVMETHOD(gpio_pin_getcaps, imx51_gpio_pin_getcaps), 939 DEVMETHOD(gpio_pin_setflags, imx51_gpio_pin_setflags), 940 DEVMETHOD(gpio_pin_get, imx51_gpio_pin_get), 941 DEVMETHOD(gpio_pin_set, imx51_gpio_pin_set), 942 DEVMETHOD(gpio_pin_toggle, imx51_gpio_pin_toggle), 943 DEVMETHOD(gpio_pin_access_32, imx51_gpio_pin_access_32), 944 DEVMETHOD(gpio_pin_config_32, imx51_gpio_pin_config_32), 945 {0, 0}, 946}; 947 948static driver_t imx51_gpio_driver = { 949 "gpio", 950 imx51_gpio_methods, 951 sizeof(struct imx51_gpio_softc), 952}; 953 954EARLY_DRIVER_MODULE(imx51_gpio, simplebus, imx51_gpio_driver, 0, 0, 955 BUS_PASS_INTERRUPT + BUS_PASS_ORDER_LATE); 956