1/*-
2 * Copyright (c) 2016 Jared McNeill <jmcneill@invisible.ca>
3 *
4 * Redistribution and use in source and binary forms, with or without
5 * modification, are permitted provided that the following conditions
6 * are met:
7 * 1. Redistributions of source code must retain the above copyright
8 *    notice, this list of conditions and the following disclaimer.
9 * 2. Redistributions in binary form must reproduce the above copyright
10 *    notice, this list of conditions and the following disclaimer in the
11 *    documentation and/or other materials provided with the distribution.
12 *
13 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
14 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
15 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
16 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
17 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
18 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
19 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
20 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
21 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
22 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
23 * SUCH DAMAGE.
24 */
25
26/*
27 * Allwinner GMAC clock
28 */
29
30#include <sys/param.h>
31#include <sys/systm.h>
32#include <sys/bus.h>
33#include <sys/rman.h>
34#include <sys/kernel.h>
35#include <sys/module.h>
36#include <machine/bus.h>
37
38#include <dev/ofw/ofw_bus.h>
39#include <dev/ofw/ofw_bus_subr.h>
40#include <dev/ofw/ofw_subr.h>
41
42#include <dev/clk/clk_mux.h>
43#include <dev/clk/clk_gate.h>
44
45#include "clkdev_if.h"
46
47#define	GMAC_CLK_PIT		(0x1 << 2)
48#define	GMAC_CLK_PIT_SHIFT	2
49#define	GMAC_CLK_PIT_MII	0
50#define	GMAC_CLK_PIT_RGMII	1
51#define	GMAC_CLK_SRC		(0x3 << 0)
52#define	GMAC_CLK_SRC_SHIFT	0
53#define	GMAC_CLK_SRC_MII	0
54#define	GMAC_CLK_SRC_EXT_RGMII	1
55#define	GMAC_CLK_SRC_RGMII	2
56
57#define	EMAC_TXC_DIV_CFG	(1 << 15)
58#define	EMAC_TXC_DIV_CFG_SHIFT	15
59#define	EMAC_TXC_DIV_CFG_125MHZ	0
60#define	EMAC_TXC_DIV_CFG_25MHZ	1
61#define	EMAC_PHY_SELECT		(1 << 16)
62#define	EMAC_PHY_SELECT_SHIFT	16
63#define	EMAC_PHY_SELECT_INT	0
64#define	EMAC_PHY_SELECT_EXT	1
65#define	EMAC_ETXDC		(0x7 << 10)
66#define	EMAC_ETXDC_SHIFT	10
67#define	EMAC_ERXDC		(0x1f << 5)
68#define	EMAC_ERXDC_SHIFT	5
69
70#define	CLK_IDX_MII		0
71#define	CLK_IDX_RGMII		1
72#define	CLK_IDX_COUNT		2
73
74static struct ofw_compat_data compat_data[] = {
75	{ "allwinner,sun7i-a20-gmac-clk",	1 },
76	{ NULL, 0 }
77};
78
79struct aw_gmacclk_sc {
80	device_t	clkdev;
81	bus_addr_t	reg;
82
83	int		rx_delay;
84	int		tx_delay;
85};
86
87#define	GMACCLK_READ(sc, val)	CLKDEV_READ_4((sc)->clkdev, (sc)->reg, (val))
88#define	GMACCLK_WRITE(sc, val)	CLKDEV_WRITE_4((sc)->clkdev, (sc)->reg, (val))
89#define	DEVICE_LOCK(sc)		CLKDEV_DEVICE_LOCK((sc)->clkdev)
90#define	DEVICE_UNLOCK(sc)	CLKDEV_DEVICE_UNLOCK((sc)->clkdev)
91
92static int
93aw_gmacclk_init(struct clknode *clk, device_t dev)
94{
95	struct aw_gmacclk_sc *sc;
96	uint32_t val, index;
97
98	sc = clknode_get_softc(clk);
99
100	DEVICE_LOCK(sc);
101	GMACCLK_READ(sc, &val);
102	DEVICE_UNLOCK(sc);
103
104	switch ((val & GMAC_CLK_SRC) >> GMAC_CLK_SRC_SHIFT) {
105	case GMAC_CLK_SRC_MII:
106		index = CLK_IDX_MII;
107		break;
108	case GMAC_CLK_SRC_RGMII:
109		index = CLK_IDX_RGMII;
110		break;
111	default:
112		return (ENXIO);
113	}
114
115	clknode_init_parent_idx(clk, index);
116	return (0);
117}
118
119static int
120aw_gmacclk_set_mux(struct clknode *clk, int index)
121{
122	struct aw_gmacclk_sc *sc;
123	uint32_t val, clk_src, pit;
124
125	sc = clknode_get_softc(clk);
126
127	switch (index) {
128	case CLK_IDX_MII:
129		clk_src = GMAC_CLK_SRC_MII;
130		pit = GMAC_CLK_PIT_MII;
131		break;
132	case CLK_IDX_RGMII:
133		clk_src = GMAC_CLK_SRC_RGMII;
134		pit = GMAC_CLK_PIT_RGMII;
135		break;
136	default:
137		return (ENXIO);
138	}
139
140	DEVICE_LOCK(sc);
141	GMACCLK_READ(sc, &val);
142	val &= ~(GMAC_CLK_SRC | GMAC_CLK_PIT);
143	val |= (clk_src << GMAC_CLK_SRC_SHIFT);
144	val |= (pit << GMAC_CLK_PIT_SHIFT);
145	GMACCLK_WRITE(sc, val);
146	DEVICE_UNLOCK(sc);
147
148	return (0);
149}
150
151static clknode_method_t aw_gmacclk_clknode_methods[] = {
152	/* Device interface */
153	CLKNODEMETHOD(clknode_init,		aw_gmacclk_init),
154	CLKNODEMETHOD(clknode_set_mux,		aw_gmacclk_set_mux),
155	CLKNODEMETHOD_END
156};
157DEFINE_CLASS_1(aw_gmacclk_clknode, aw_gmacclk_clknode_class,
158    aw_gmacclk_clknode_methods, sizeof(struct aw_gmacclk_sc), clknode_class);
159
160static int
161aw_gmacclk_probe(device_t dev)
162{
163	if (!ofw_bus_status_okay(dev))
164		return (ENXIO);
165
166	if (ofw_bus_search_compatible(dev, compat_data)->ocd_data == 0)
167		return (ENXIO);
168
169	device_set_desc(dev, "Allwinner GMAC Clock");
170	return (BUS_PROBE_DEFAULT);
171}
172
173static int
174aw_gmacclk_attach(device_t dev)
175{
176	struct clknode_init_def def;
177	struct aw_gmacclk_sc *sc;
178	struct clkdom *clkdom;
179	struct clknode *clk;
180	clk_t clk_parent;
181	bus_addr_t paddr;
182	bus_size_t psize;
183	phandle_t node;
184	int error, ncells, i;
185
186	node = ofw_bus_get_node(dev);
187
188	if (ofw_reg_to_paddr(node, 0, &paddr, &psize, NULL) != 0) {
189		device_printf(dev, "cannot parse 'reg' property\n");
190		return (ENXIO);
191	}
192
193	error = ofw_bus_parse_xref_list_get_length(node, "clocks",
194	    "#clock-cells", &ncells);
195	if (error != 0 || ncells != CLK_IDX_COUNT) {
196		device_printf(dev, "couldn't find parent clocks\n");
197		return (ENXIO);
198	}
199
200	clkdom = clkdom_create(dev);
201
202	memset(&def, 0, sizeof(def));
203	error = clk_parse_ofw_clk_name(dev, node, &def.name);
204	if (error != 0) {
205		device_printf(dev, "cannot parse clock name\n");
206		error = ENXIO;
207		goto fail;
208	}
209	def.id = 1;
210	def.parent_names = malloc(sizeof(char *) * ncells, M_OFWPROP, M_WAITOK);
211	for (i = 0; i < ncells; i++) {
212		error = clk_get_by_ofw_index(dev, 0, i, &clk_parent);
213		if (error != 0) {
214			device_printf(dev, "cannot get clock %d\n", error);
215			goto fail;
216		}
217		def.parent_names[i] = clk_get_name(clk_parent);
218		clk_release(clk_parent);
219	}
220	def.parent_cnt = ncells;
221
222	clk = clknode_create(clkdom, &aw_gmacclk_clknode_class, &def);
223	if (clk == NULL) {
224		device_printf(dev, "cannot create clknode\n");
225		error = ENXIO;
226		goto fail;
227	}
228
229	sc = clknode_get_softc(clk);
230	sc->reg = paddr;
231	sc->clkdev = device_get_parent(dev);
232	sc->tx_delay = sc->rx_delay = -1;
233	OF_getencprop(node, "tx-delay", &sc->tx_delay, sizeof(sc->tx_delay));
234	OF_getencprop(node, "rx-delay", &sc->rx_delay, sizeof(sc->rx_delay));
235
236	clknode_register(clkdom, clk);
237
238	if (clkdom_finit(clkdom) != 0) {
239		device_printf(dev, "cannot finalize clkdom initialization\n");
240		error = ENXIO;
241		goto fail;
242	}
243
244	if (bootverbose)
245		clkdom_dump(clkdom);
246
247	return (0);
248
249fail:
250	return (error);
251}
252
253static device_method_t aw_gmacclk_methods[] = {
254	/* Device interface */
255	DEVMETHOD(device_probe,		aw_gmacclk_probe),
256	DEVMETHOD(device_attach,	aw_gmacclk_attach),
257
258	DEVMETHOD_END
259};
260
261static driver_t aw_gmacclk_driver = {
262	"aw_gmacclk",
263	aw_gmacclk_methods,
264	0
265};
266
267EARLY_DRIVER_MODULE(aw_gmacclk, simplebus, aw_gmacclk_driver, 0, 0,
268    BUS_PASS_RESOURCE + BUS_PASS_ORDER_MIDDLE);
269