1//===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file declares the Mips specific subclass of TargetSubtargetInfo.
10//
11//===----------------------------------------------------------------------===//
12
13#ifndef LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
14#define LLVM_LIB_TARGET_MIPS_MIPSSUBTARGET_H
15
16#include "MCTargetDesc/MipsABIInfo.h"
17#include "MipsFrameLowering.h"
18#include "MipsISelLowering.h"
19#include "MipsInstrInfo.h"
20#include "llvm/CodeGen/GlobalISel/CallLowering.h"
21#include "llvm/CodeGen/GlobalISel/InstructionSelector.h"
22#include "llvm/CodeGen/GlobalISel/LegalizerInfo.h"
23#include "llvm/CodeGen/RegisterBankInfo.h"
24#include "llvm/CodeGen/SelectionDAGTargetInfo.h"
25#include "llvm/CodeGen/TargetSubtargetInfo.h"
26#include "llvm/IR/DataLayout.h"
27#include "llvm/MC/MCInstrItineraries.h"
28#include "llvm/Support/ErrorHandling.h"
29
30#define GET_SUBTARGETINFO_HEADER
31#include "MipsGenSubtargetInfo.inc"
32
33namespace llvm {
34class StringRef;
35
36class MipsTargetMachine;
37
38class MipsSubtarget : public MipsGenSubtargetInfo {
39  virtual void anchor();
40
41  enum MipsArchEnum {
42    MipsDefault,
43    Mips1, Mips2, Mips32, Mips32r2, Mips32r3, Mips32r5, Mips32r6, Mips32Max,
44    Mips3, Mips4, Mips5, Mips64, Mips64r2, Mips64r3, Mips64r5, Mips64r6
45  };
46
47  enum class CPU { P5600 };
48
49  // Used to avoid printing dsp warnings multiple times.
50  static bool DspWarningPrinted;
51
52  // Used to avoid printing msa warnings multiple times.
53  static bool MSAWarningPrinted;
54
55  // Used to avoid printing crc warnings multiple times.
56  static bool CRCWarningPrinted;
57
58  // Used to avoid printing ginv warnings multiple times.
59  static bool GINVWarningPrinted;
60
61  // Used to avoid printing Mips1 warnings multiple times.
62  static bool MIPS1WarningPrinted;
63
64  // Used to avoid printing virt warnings multiple times.
65  static bool VirtWarningPrinted;
66
67  // Mips architecture version
68  MipsArchEnum MipsArchVersion;
69
70  // Processor implementation (unused but required to exist by
71  // tablegen-erated code).
72  CPU ProcImpl;
73
74  // IsLittle - The target is Little Endian
75  bool IsLittle;
76
77  // IsSoftFloat - The target does not support any floating point instructions.
78  bool IsSoftFloat;
79
80  // IsSingleFloat - The target only supports single precision float
81  // point operations. This enable the target to use all 32 32-bit
82  // floating point registers instead of only using even ones.
83  bool IsSingleFloat;
84
85  // IsFPXX - MIPS O32 modeless ABI.
86  bool IsFPXX;
87
88  // NoABICalls - Disable SVR4-style position-independent code.
89  bool NoABICalls;
90
91  // Abs2008 - Use IEEE 754-2008 abs.fmt instruction.
92  bool Abs2008;
93
94  // IsFP64bit - The target processor has 64-bit floating point registers.
95  bool IsFP64bit;
96
97  /// Are odd single-precision registers permitted?
98  /// This corresponds to -modd-spreg and -mno-odd-spreg
99  bool UseOddSPReg;
100
101  // IsNan2008 - IEEE 754-2008 NaN encoding.
102  bool IsNaN2008bit;
103
104  // IsGP64bit - General-purpose registers are 64 bits wide
105  bool IsGP64bit;
106
107  // IsPTR64bit - Pointers are 64 bit wide
108  bool IsPTR64bit;
109
110  // HasVFPU - Processor has a vector floating point unit.
111  bool HasVFPU;
112
113  // CPU supports cnMIPS (Cavium Networks Octeon CPU).
114  bool HasCnMips;
115
116  // CPU supports cnMIPSP (Cavium Networks Octeon+ CPU).
117  bool HasCnMipsP;
118
119  // isLinux - Target system is Linux. Is false we consider ELFOS for now.
120  bool IsLinux;
121
122  // UseSmallSection - Small section is used.
123  bool UseSmallSection;
124
125  /// Features related to the presence of specific instructions.
126
127  // HasMips3_32 - The subset of MIPS-III instructions added to MIPS32
128  bool HasMips3_32;
129
130  // HasMips3_32r2 - The subset of MIPS-III instructions added to MIPS32r2
131  bool HasMips3_32r2;
132
133  // HasMips4_32 - Has the subset of MIPS-IV present in MIPS32
134  bool HasMips4_32;
135
136  // HasMips4_32r2 - Has the subset of MIPS-IV present in MIPS32r2
137  bool HasMips4_32r2;
138
139  // HasMips5_32r2 - Has the subset of MIPS-V present in MIPS32r2
140  bool HasMips5_32r2;
141
142  // InMips16 -- can process Mips16 instructions
143  bool InMips16Mode;
144
145  // Mips16 hard float
146  bool InMips16HardFloat;
147
148  // InMicroMips -- can process MicroMips instructions
149  bool InMicroMipsMode;
150
151  // HasDSP, HasDSPR2, HasDSPR3 -- supports DSP ASE.
152  bool HasDSP, HasDSPR2, HasDSPR3;
153
154  // Has3D -- Supports Mips3D ASE.
155  bool Has3D;
156
157  // Allow mixed Mips16 and Mips32 in one source file
158  bool AllowMixed16_32;
159
160  // Optimize for space by compiling all functions as Mips 16 unless
161  // it needs floating point. Functions needing floating point are
162  // compiled as Mips32
163  bool Os16;
164
165  // HasMSA -- supports MSA ASE.
166  bool HasMSA;
167
168  // UseTCCInDIV -- Enables the use of trapping in the assembler.
169  bool UseTCCInDIV;
170
171  // Sym32 -- On Mips64 symbols are 32 bits.
172  bool HasSym32;
173
174  // HasEVA -- supports EVA ASE.
175  bool HasEVA;
176
177  // nomadd4 - disables generation of 4-operand madd.s, madd.d and
178  // related instructions.
179  bool DisableMadd4;
180
181  // HasMT -- support MT ASE.
182  bool HasMT;
183
184  // HasCRC -- supports R6 CRC ASE
185  bool HasCRC;
186
187  // HasVirt -- supports Virtualization ASE
188  bool HasVirt;
189
190  // HasGINV -- supports R6 Global INValidate ASE
191  bool HasGINV;
192
193  // Use hazard variants of the jump register instructions for indirect
194  // function calls and jump tables.
195  bool UseIndirectJumpsHazard;
196
197  // Disable use of the `jal` instruction.
198  bool UseLongCalls = false;
199
200  // Assume 32-bit GOT.
201  bool UseXGOT = false;
202
203  /// The minimum alignment known to hold of the stack frame on
204  /// entry to the function and which must be maintained by every function.
205  Align stackAlignment;
206
207  /// The overridden stack alignment.
208  MaybeAlign StackAlignOverride;
209
210  InstrItineraryData InstrItins;
211
212  // We can override the determination of whether we are in mips16 mode
213  // as from the command line
214  enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
215
216  const MipsTargetMachine &TM;
217
218  Triple TargetTriple;
219
220  const SelectionDAGTargetInfo TSInfo;
221  std::unique_ptr<const MipsInstrInfo> InstrInfo;
222  std::unique_ptr<const MipsFrameLowering> FrameLowering;
223  std::unique_ptr<const MipsTargetLowering> TLInfo;
224
225public:
226  bool isPositionIndependent() const;
227  /// This overrides the PostRAScheduler bit in the SchedModel for each CPU.
228  bool enablePostRAScheduler() const override;
229  void getCriticalPathRCs(RegClassVector &CriticalPathRCs) const override;
230  CodeGenOptLevel getOptLevelToEnablePostRAScheduler() const override;
231
232  bool isABI_N64() const;
233  bool isABI_N32() const;
234  bool isABI_O32() const;
235  const MipsABIInfo &getABI() const;
236  bool isABI_FPXX() const { return isABI_O32() && IsFPXX; }
237
238  /// This constructor initializes the data members to match that
239  /// of the specified triple.
240  MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS, bool little,
241                const MipsTargetMachine &TM, MaybeAlign StackAlignOverride);
242
243  /// ParseSubtargetFeatures - Parses features string setting specified
244  /// subtarget options.  Definition of function is auto generated by tblgen.
245  void ParseSubtargetFeatures(StringRef CPU, StringRef TuneCPU, StringRef FS);
246
247  bool hasMips1() const { return MipsArchVersion >= Mips1; }
248  bool hasMips2() const { return MipsArchVersion >= Mips2; }
249  bool hasMips3() const { return MipsArchVersion >= Mips3; }
250  bool hasMips4() const { return MipsArchVersion >= Mips4; }
251  bool hasMips5() const { return MipsArchVersion >= Mips5; }
252  bool hasMips4_32() const { return HasMips4_32; }
253  bool hasMips4_32r2() const { return HasMips4_32r2; }
254  bool hasMips32() const {
255    return (MipsArchVersion >= Mips32 && MipsArchVersion < Mips32Max) ||
256           hasMips64();
257  }
258  bool hasMips32r2() const {
259    return (MipsArchVersion >= Mips32r2 && MipsArchVersion < Mips32Max) ||
260           hasMips64r2();
261  }
262  bool hasMips32r3() const {
263    return (MipsArchVersion >= Mips32r3 && MipsArchVersion < Mips32Max) ||
264           hasMips64r2();
265  }
266  bool hasMips32r5() const {
267    return (MipsArchVersion >= Mips32r5 && MipsArchVersion < Mips32Max) ||
268           hasMips64r5();
269  }
270  bool hasMips32r6() const {
271    return (MipsArchVersion >= Mips32r6 && MipsArchVersion < Mips32Max) ||
272           hasMips64r6();
273  }
274  bool hasMips64() const { return MipsArchVersion >= Mips64; }
275  bool hasMips64r2() const { return MipsArchVersion >= Mips64r2; }
276  bool hasMips64r3() const { return MipsArchVersion >= Mips64r3; }
277  bool hasMips64r5() const { return MipsArchVersion >= Mips64r5; }
278  bool hasMips64r6() const { return MipsArchVersion >= Mips64r6; }
279
280  bool hasCnMips() const { return HasCnMips; }
281  bool hasCnMipsP() const { return HasCnMipsP; }
282
283  bool isLittle() const { return IsLittle; }
284  bool isABICalls() const { return !NoABICalls; }
285  bool isFPXX() const { return IsFPXX; }
286  bool isFP64bit() const { return IsFP64bit; }
287  bool useOddSPReg() const { return UseOddSPReg; }
288  bool noOddSPReg() const { return !UseOddSPReg; }
289  bool isNaN2008() const { return IsNaN2008bit; }
290  bool inAbs2008Mode() const { return Abs2008; }
291  bool isGP64bit() const { return IsGP64bit; }
292  bool isGP32bit() const { return !IsGP64bit; }
293  unsigned getGPRSizeInBytes() const { return isGP64bit() ? 8 : 4; }
294  bool isPTR64bit() const { return IsPTR64bit; }
295  bool isPTR32bit() const { return !IsPTR64bit; }
296  bool hasSym32() const {
297    return (HasSym32 && isABI_N64()) || isABI_N32() || isABI_O32();
298  }
299  bool isSingleFloat() const { return IsSingleFloat; }
300  bool isTargetELF() const { return TargetTriple.isOSBinFormatELF(); }
301  bool hasVFPU() const { return HasVFPU; }
302  bool inMips16Mode() const { return InMips16Mode; }
303  bool inMips16ModeDefault() const {
304    return InMips16Mode;
305  }
306  // Hard float for mips16 means essentially to compile as soft float
307  // but to use a runtime library for soft float that is written with
308  // native mips32 floating point instructions (those runtime routines
309  // run in mips32 hard float mode).
310  bool inMips16HardFloat() const {
311    return inMips16Mode() && InMips16HardFloat;
312  }
313  bool inMicroMipsMode() const { return InMicroMipsMode && !InMips16Mode; }
314  bool inMicroMips32r6Mode() const {
315    return inMicroMipsMode() && hasMips32r6();
316  }
317  bool hasDSP() const { return HasDSP; }
318  bool hasDSPR2() const { return HasDSPR2; }
319  bool hasDSPR3() const { return HasDSPR3; }
320  bool has3D() const { return Has3D; }
321  bool hasMSA() const { return HasMSA; }
322  bool disableMadd4() const { return DisableMadd4; }
323  bool hasEVA() const { return HasEVA; }
324  bool hasMT() const { return HasMT; }
325  bool hasCRC() const { return HasCRC; }
326  bool hasVirt() const { return HasVirt; }
327  bool hasGINV() const { return HasGINV; }
328  bool useIndirectJumpsHazard() const {
329    return UseIndirectJumpsHazard && hasMips32r2();
330  }
331  bool useSmallSection() const { return UseSmallSection; }
332
333  bool hasStandardEncoding() const { return !InMips16Mode && !InMicroMipsMode; }
334
335  bool useSoftFloat() const { return IsSoftFloat; }
336
337  bool useLongCalls() const { return UseLongCalls; }
338
339  bool useXGOT() const { return UseXGOT; }
340
341  bool enableLongBranchPass() const {
342    return hasStandardEncoding() || inMicroMipsMode() || allowMixed16_32();
343  }
344
345  /// Features related to the presence of specific instructions.
346  bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
347  bool hasMTHC1() const { return hasMips32r2(); }
348
349  bool allowMixed16_32() const { return inMips16ModeDefault() |
350                                        AllowMixed16_32; }
351
352  bool os16() const { return Os16; }
353
354  bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
355
356  bool isXRaySupported() const override { return true; }
357
358  // for now constant islands are on for the whole compilation unit but we only
359  // really use them if in addition we are in mips16 mode
360  static bool useConstantIslands();
361
362  Align getStackAlignment() const { return stackAlignment; }
363
364  // Grab relocation model
365  Reloc::Model getRelocationModel() const;
366
367  MipsSubtarget &initializeSubtargetDependencies(StringRef CPU, StringRef FS,
368                                                 const TargetMachine &TM);
369
370  /// Does the system support unaligned memory access.
371  ///
372  /// MIPS32r6/MIPS64r6 require full unaligned access support but does not
373  /// specify which component of the system provides it. Hardware, software, and
374  /// hybrid implementations are all valid.
375  bool systemSupportsUnalignedAccess() const { return hasMips32r6(); }
376
377  // Set helper classes
378  void setHelperClassesMips16();
379  void setHelperClassesMipsSE();
380
381  const SelectionDAGTargetInfo *getSelectionDAGInfo() const override {
382    return &TSInfo;
383  }
384  const MipsInstrInfo *getInstrInfo() const override { return InstrInfo.get(); }
385  const TargetFrameLowering *getFrameLowering() const override {
386    return FrameLowering.get();
387  }
388  const MipsRegisterInfo *getRegisterInfo() const override {
389    return &InstrInfo->getRegisterInfo();
390  }
391  const MipsTargetLowering *getTargetLowering() const override {
392    return TLInfo.get();
393  }
394  const InstrItineraryData *getInstrItineraryData() const override {
395    return &InstrItins;
396  }
397
398protected:
399  // GlobalISel related APIs.
400  std::unique_ptr<CallLowering> CallLoweringInfo;
401  std::unique_ptr<LegalizerInfo> Legalizer;
402  std::unique_ptr<RegisterBankInfo> RegBankInfo;
403  std::unique_ptr<InstructionSelector> InstSelector;
404
405public:
406  const CallLowering *getCallLowering() const override;
407  const LegalizerInfo *getLegalizerInfo() const override;
408  const RegisterBankInfo *getRegBankInfo() const override;
409  InstructionSelector *getInstructionSelector() const override;
410};
411} // End llvm namespace
412
413#endif
414