1//===- MipsInstrInfo.h - Mips Instruction Information -----------*- C++ -*-===//
2//
3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4// See https://llvm.org/LICENSE.txt for license information.
5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6//
7//===----------------------------------------------------------------------===//
8//
9// This file contains the Mips implementation of the TargetInstrInfo class.
10//
11// FIXME: We need to override TargetInstrInfo::getInlineAsmLength method in
12// order for MipsLongBranch pass to work correctly when the code has inline
13// assembly.  The returned value doesn't have to be the asm instruction's exact
14// size in bytes; MipsLongBranch only expects it to be the correct upper bound.
15//===----------------------------------------------------------------------===//
16
17#ifndef LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
18#define LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
19
20#include "MCTargetDesc/MipsMCTargetDesc.h"
21#include "Mips.h"
22#include "MipsRegisterInfo.h"
23#include "llvm/ADT/ArrayRef.h"
24#include "llvm/CodeGen/MachineBasicBlock.h"
25#include "llvm/CodeGen/MachineInstrBuilder.h"
26#include "llvm/CodeGen/MachineMemOperand.h"
27#include "llvm/CodeGen/TargetInstrInfo.h"
28#include <cstdint>
29
30#define GET_INSTRINFO_HEADER
31#include "MipsGenInstrInfo.inc"
32
33namespace llvm {
34
35class MachineInstr;
36class MachineOperand;
37class MipsSubtarget;
38class TargetRegisterClass;
39class TargetRegisterInfo;
40
41class MipsInstrInfo : public MipsGenInstrInfo {
42  virtual void anchor();
43
44protected:
45  const MipsSubtarget &Subtarget;
46  unsigned UncondBrOpc;
47
48public:
49  enum BranchType {
50    BT_None,       // Couldn't analyze branch.
51    BT_NoBranch,   // No branches found.
52    BT_Uncond,     // One unconditional branch.
53    BT_Cond,       // One conditional branch.
54    BT_CondUncond, // A conditional branch followed by an unconditional branch.
55    BT_Indirect    // One indirct branch.
56  };
57
58  explicit MipsInstrInfo(const MipsSubtarget &STI, unsigned UncondBrOpc);
59
60  static const MipsInstrInfo *create(MipsSubtarget &STI);
61
62  /// Branch Analysis
63  bool analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
64                     MachineBasicBlock *&FBB,
65                     SmallVectorImpl<MachineOperand> &Cond,
66                     bool AllowModify) const override;
67
68  unsigned removeBranch(MachineBasicBlock &MBB,
69                        int *BytesRemoved = nullptr) const override;
70
71  unsigned insertBranch(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
72                        MachineBasicBlock *FBB, ArrayRef<MachineOperand> Cond,
73                        const DebugLoc &DL,
74                        int *BytesAdded = nullptr) const override;
75
76  bool
77  reverseBranchCondition(SmallVectorImpl<MachineOperand> &Cond) const override;
78
79  BranchType analyzeBranch(MachineBasicBlock &MBB, MachineBasicBlock *&TBB,
80                           MachineBasicBlock *&FBB,
81                           SmallVectorImpl<MachineOperand> &Cond,
82                           bool AllowModify,
83                           SmallVectorImpl<MachineInstr *> &BranchInstrs) const;
84
85  /// Determine the opcode of a non-delay slot form for a branch if one exists.
86  unsigned getEquivalentCompactForm(const MachineBasicBlock::iterator I) const;
87
88  /// Determine if the branch target is in range.
89  bool isBranchOffsetInRange(unsigned BranchOpc,
90                             int64_t BrOffset) const override;
91
92  /// Predicate to determine if an instruction can go in a forbidden slot.
93  bool SafeInForbiddenSlot(const MachineInstr &MI) const;
94
95  /// Predicate to determine if an instruction can go in an FPU delay slot.
96  bool SafeInFPUDelaySlot(const MachineInstr &MIInSlot,
97                          const MachineInstr &FPUMI) const;
98
99  /// Predicate to determine if an instruction can go in a load delay slot.
100  bool SafeInLoadDelaySlot(const MachineInstr &MIInSlot,
101                           const MachineInstr &LoadMI) const;
102
103  /// Predicate to determine if an instruction has a forbidden slot.
104  bool HasForbiddenSlot(const MachineInstr &MI) const;
105
106  /// Predicate to determine if an instruction has an FPU delay slot.
107  bool HasFPUDelaySlot(const MachineInstr &MI) const;
108
109  /// Predicate to determine if an instruction has a load delay slot.
110  bool HasLoadDelaySlot(const MachineInstr &MI) const;
111
112  /// Insert nop instruction when hazard condition is found
113  void insertNoop(MachineBasicBlock &MBB,
114                  MachineBasicBlock::iterator MI) const override;
115
116  /// Insert an ISA appropriate `nop`.
117  // FIXME: Add support for MIPS16e.
118  MachineInstrBuilder insertNop(MachineBasicBlock &MBB,
119                                MachineBasicBlock::iterator MI,
120                                DebugLoc DL) const;
121
122  /// getRegisterInfo - TargetInstrInfo is a superset of MRegister info.  As
123  /// such, whenever a client has an instance of instruction info, it should
124  /// always be able to get register info as well (through this method).
125  virtual const MipsRegisterInfo &getRegisterInfo() const = 0;
126
127  virtual unsigned getOppositeBranchOpc(unsigned Opc) const = 0;
128
129  virtual bool isBranchWithImm(unsigned Opc) const {
130    return false;
131  }
132
133  /// Return the number of bytes of code the specified instruction may be.
134  unsigned getInstSizeInBytes(const MachineInstr &MI) const override;
135
136  void storeRegToStackSlot(MachineBasicBlock &MBB,
137                           MachineBasicBlock::iterator MBBI, Register SrcReg,
138                           bool isKill, int FrameIndex,
139                           const TargetRegisterClass *RC,
140                           const TargetRegisterInfo *TRI,
141                           Register VReg) const override {
142    storeRegToStack(MBB, MBBI, SrcReg, isKill, FrameIndex, RC, TRI, 0);
143  }
144
145  void loadRegFromStackSlot(MachineBasicBlock &MBB,
146                            MachineBasicBlock::iterator MBBI, Register DestReg,
147                            int FrameIndex, const TargetRegisterClass *RC,
148                            const TargetRegisterInfo *TRI,
149                            Register VReg) const override {
150    loadRegFromStack(MBB, MBBI, DestReg, FrameIndex, RC, TRI, 0);
151  }
152
153  virtual void storeRegToStack(MachineBasicBlock &MBB,
154                               MachineBasicBlock::iterator MI,
155                               Register SrcReg, bool isKill, int FrameIndex,
156                               const TargetRegisterClass *RC,
157                               const TargetRegisterInfo *TRI,
158                               int64_t Offset) const = 0;
159
160  virtual void loadRegFromStack(MachineBasicBlock &MBB,
161                                MachineBasicBlock::iterator MI,
162                                Register DestReg, int FrameIndex,
163                                const TargetRegisterClass *RC,
164                                const TargetRegisterInfo *TRI,
165                                int64_t Offset) const = 0;
166
167  virtual void adjustStackPtr(unsigned SP, int64_t Amount,
168                              MachineBasicBlock &MBB,
169                              MachineBasicBlock::iterator I) const = 0;
170
171  /// Create an instruction which has the same operands and memory operands
172  /// as MI but has a new opcode.
173  MachineInstrBuilder genInstrWithNewOpc(unsigned NewOpc,
174                                         MachineBasicBlock::iterator I) const;
175
176  bool findCommutedOpIndices(const MachineInstr &MI, unsigned &SrcOpIdx1,
177                             unsigned &SrcOpIdx2) const override;
178
179  /// Perform target specific instruction verification.
180  bool verifyInstruction(const MachineInstr &MI,
181                         StringRef &ErrInfo) const override;
182
183  std::pair<unsigned, unsigned>
184  decomposeMachineOperandsTargetFlags(unsigned TF) const override;
185
186  ArrayRef<std::pair<unsigned, const char *>>
187  getSerializableDirectMachineOperandTargetFlags() const override;
188
189  std::optional<RegImmPair> isAddImmediate(const MachineInstr &MI,
190                                           Register Reg) const override;
191
192  std::optional<ParamLoadedValue>
193  describeLoadedValue(const MachineInstr &MI, Register Reg) const override;
194
195protected:
196  bool isZeroImm(const MachineOperand &op) const;
197
198  MachineMemOperand *GetMemOperand(MachineBasicBlock &MBB, int FI,
199                                   MachineMemOperand::Flags Flags) const;
200
201private:
202  virtual unsigned getAnalyzableBrOpc(unsigned Opc) const = 0;
203
204  void AnalyzeCondBr(const MachineInstr *Inst, unsigned Opc,
205                     MachineBasicBlock *&BB,
206                     SmallVectorImpl<MachineOperand> &Cond) const;
207
208  void BuildCondBr(MachineBasicBlock &MBB, MachineBasicBlock *TBB,
209                   const DebugLoc &DL, ArrayRef<MachineOperand> Cond) const;
210};
211
212/// Create MipsInstrInfo objects.
213const MipsInstrInfo *createMips16InstrInfo(const MipsSubtarget &STI);
214const MipsInstrInfo *createMipsSEInstrInfo(const MipsSubtarget &STI);
215
216} // end namespace llvm
217
218#endif // LLVM_LIB_TARGET_MIPS_MIPSINSTRINFO_H
219