1//===-- ARMAsmBackend.cpp - ARM Assembler Backend -------------------------===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8 9#include "MCTargetDesc/ARMAsmBackend.h" 10#include "MCTargetDesc/ARMAddressingModes.h" 11#include "MCTargetDesc/ARMAsmBackendDarwin.h" 12#include "MCTargetDesc/ARMAsmBackendELF.h" 13#include "MCTargetDesc/ARMAsmBackendWinCOFF.h" 14#include "MCTargetDesc/ARMFixupKinds.h" 15#include "MCTargetDesc/ARMMCTargetDesc.h" 16#include "llvm/ADT/StringSwitch.h" 17#include "llvm/BinaryFormat/ELF.h" 18#include "llvm/BinaryFormat/MachO.h" 19#include "llvm/MC/MCAsmBackend.h" 20#include "llvm/MC/MCAsmLayout.h" 21#include "llvm/MC/MCAssembler.h" 22#include "llvm/MC/MCContext.h" 23#include "llvm/MC/MCDirectives.h" 24#include "llvm/MC/MCELFObjectWriter.h" 25#include "llvm/MC/MCExpr.h" 26#include "llvm/MC/MCFixupKindInfo.h" 27#include "llvm/MC/MCObjectWriter.h" 28#include "llvm/MC/MCRegisterInfo.h" 29#include "llvm/MC/MCSectionELF.h" 30#include "llvm/MC/MCSectionMachO.h" 31#include "llvm/MC/MCSubtargetInfo.h" 32#include "llvm/MC/MCValue.h" 33#include "llvm/Support/Debug.h" 34#include "llvm/Support/EndianStream.h" 35#include "llvm/Support/ErrorHandling.h" 36#include "llvm/Support/Format.h" 37#include "llvm/Support/raw_ostream.h" 38using namespace llvm; 39 40namespace { 41class ARMELFObjectWriter : public MCELFObjectTargetWriter { 42public: 43 ARMELFObjectWriter(uint8_t OSABI) 44 : MCELFObjectTargetWriter(/*Is64Bit*/ false, OSABI, ELF::EM_ARM, 45 /*HasRelocationAddend*/ false) {} 46}; 47} // end anonymous namespace 48 49std::optional<MCFixupKind> ARMAsmBackend::getFixupKind(StringRef Name) const { 50 return std::nullopt; 51} 52 53std::optional<MCFixupKind> 54ARMAsmBackendELF::getFixupKind(StringRef Name) const { 55 unsigned Type = llvm::StringSwitch<unsigned>(Name) 56#define ELF_RELOC(X, Y) .Case(#X, Y) 57#include "llvm/BinaryFormat/ELFRelocs/ARM.def" 58#undef ELF_RELOC 59 .Case("BFD_RELOC_NONE", ELF::R_ARM_NONE) 60 .Case("BFD_RELOC_8", ELF::R_ARM_ABS8) 61 .Case("BFD_RELOC_16", ELF::R_ARM_ABS16) 62 .Case("BFD_RELOC_32", ELF::R_ARM_ABS32) 63 .Default(-1u); 64 if (Type == -1u) 65 return std::nullopt; 66 return static_cast<MCFixupKind>(FirstLiteralRelocationKind + Type); 67} 68 69const MCFixupKindInfo &ARMAsmBackend::getFixupKindInfo(MCFixupKind Kind) const { 70 const static MCFixupKindInfo InfosLE[ARM::NumTargetFixupKinds] = { 71 // This table *must* be in the order that the fixup_* kinds are defined in 72 // ARMFixupKinds.h. 73 // 74 // Name Offset (bits) Size (bits) Flags 75 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 76 {"fixup_t2_ldst_pcrel_12", 0, 32, 77 MCFixupKindInfo::FKF_IsPCRel | 78 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 79 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 80 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 81 {"fixup_t2_pcrel_10", 0, 32, 82 MCFixupKindInfo::FKF_IsPCRel | 83 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 84 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 85 {"fixup_t2_pcrel_9", 0, 32, 86 MCFixupKindInfo::FKF_IsPCRel | 87 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 88 {"fixup_arm_ldst_abs_12", 0, 32, 0}, 89 {"fixup_thumb_adr_pcrel_10", 0, 8, 90 MCFixupKindInfo::FKF_IsPCRel | 91 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 92 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 93 {"fixup_t2_adr_pcrel_12", 0, 32, 94 MCFixupKindInfo::FKF_IsPCRel | 95 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 96 {"fixup_arm_condbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 97 {"fixup_arm_uncondbranch", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 98 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 99 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 100 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 101 {"fixup_arm_uncondbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 102 {"fixup_arm_condbl", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 103 {"fixup_arm_blx", 0, 24, MCFixupKindInfo::FKF_IsPCRel}, 104 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 105 {"fixup_arm_thumb_blx", 0, 32, 106 MCFixupKindInfo::FKF_IsPCRel | 107 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 108 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 109 {"fixup_arm_thumb_cp", 0, 8, 110 MCFixupKindInfo::FKF_IsPCRel | 111 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 112 {"fixup_arm_thumb_bcc", 0, 8, MCFixupKindInfo::FKF_IsPCRel}, 113 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 114 // - 19. 115 {"fixup_arm_movt_hi16", 0, 20, 0}, 116 {"fixup_arm_movw_lo16", 0, 20, 0}, 117 {"fixup_t2_movt_hi16", 0, 20, 0}, 118 {"fixup_t2_movw_lo16", 0, 20, 0}, 119 {"fixup_arm_thumb_upper_8_15", 0, 8, 0}, 120 {"fixup_arm_thumb_upper_0_7", 0, 8, 0}, 121 {"fixup_arm_thumb_lower_8_15", 0, 8, 0}, 122 {"fixup_arm_thumb_lower_0_7", 0, 8, 0}, 123 {"fixup_arm_mod_imm", 0, 12, 0}, 124 {"fixup_t2_so_imm", 0, 26, 0}, 125 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 126 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 127 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 128 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 129 {"fixup_bfcsel_else_target", 0, 32, 0}, 130 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 131 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}}; 132 const static MCFixupKindInfo InfosBE[ARM::NumTargetFixupKinds] = { 133 // This table *must* be in the order that the fixup_* kinds are defined in 134 // ARMFixupKinds.h. 135 // 136 // Name Offset (bits) Size (bits) Flags 137 {"fixup_arm_ldst_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 138 {"fixup_t2_ldst_pcrel_12", 0, 32, 139 MCFixupKindInfo::FKF_IsPCRel | 140 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 141 {"fixup_arm_pcrel_10_unscaled", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 142 {"fixup_arm_pcrel_10", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 143 {"fixup_t2_pcrel_10", 0, 32, 144 MCFixupKindInfo::FKF_IsPCRel | 145 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 146 {"fixup_arm_pcrel_9", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 147 {"fixup_t2_pcrel_9", 0, 32, 148 MCFixupKindInfo::FKF_IsPCRel | 149 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 150 {"fixup_arm_ldst_abs_12", 0, 32, 0}, 151 {"fixup_thumb_adr_pcrel_10", 8, 8, 152 MCFixupKindInfo::FKF_IsPCRel | 153 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 154 {"fixup_arm_adr_pcrel_12", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 155 {"fixup_t2_adr_pcrel_12", 0, 32, 156 MCFixupKindInfo::FKF_IsPCRel | 157 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 158 {"fixup_arm_condbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 159 {"fixup_arm_uncondbranch", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 160 {"fixup_t2_condbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 161 {"fixup_t2_uncondbranch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 162 {"fixup_arm_thumb_br", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 163 {"fixup_arm_uncondbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 164 {"fixup_arm_condbl", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 165 {"fixup_arm_blx", 8, 24, MCFixupKindInfo::FKF_IsPCRel}, 166 {"fixup_arm_thumb_bl", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 167 {"fixup_arm_thumb_blx", 0, 32, 168 MCFixupKindInfo::FKF_IsPCRel | 169 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 170 {"fixup_arm_thumb_cb", 0, 16, MCFixupKindInfo::FKF_IsPCRel}, 171 {"fixup_arm_thumb_cp", 8, 8, 172 MCFixupKindInfo::FKF_IsPCRel | 173 MCFixupKindInfo::FKF_IsAlignedDownTo32Bits}, 174 {"fixup_arm_thumb_bcc", 8, 8, MCFixupKindInfo::FKF_IsPCRel}, 175 // movw / movt: 16-bits immediate but scattered into two chunks 0 - 12, 16 176 // - 19. 177 {"fixup_arm_movt_hi16", 12, 20, 0}, 178 {"fixup_arm_movw_lo16", 12, 20, 0}, 179 {"fixup_t2_movt_hi16", 12, 20, 0}, 180 {"fixup_t2_movw_lo16", 12, 20, 0}, 181 {"fixup_arm_thumb_upper_8_15", 24, 8, 0}, 182 {"fixup_arm_thumb_upper_0_7", 24, 8, 0}, 183 {"fixup_arm_thumb_lower_8_15", 24, 8, 0}, 184 {"fixup_arm_thumb_lower_0_7", 24, 8, 0}, 185 {"fixup_arm_mod_imm", 20, 12, 0}, 186 {"fixup_t2_so_imm", 26, 6, 0}, 187 {"fixup_bf_branch", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 188 {"fixup_bf_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 189 {"fixup_bfl_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 190 {"fixup_bfc_target", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 191 {"fixup_bfcsel_else_target", 0, 32, 0}, 192 {"fixup_wls", 0, 32, MCFixupKindInfo::FKF_IsPCRel}, 193 {"fixup_le", 0, 32, MCFixupKindInfo::FKF_IsPCRel}}; 194 195 // Fixup kinds from .reloc directive are like R_ARM_NONE. They do not require 196 // any extra processing. 197 if (Kind >= FirstLiteralRelocationKind) 198 return MCAsmBackend::getFixupKindInfo(FK_NONE); 199 200 if (Kind < FirstTargetFixupKind) 201 return MCAsmBackend::getFixupKindInfo(Kind); 202 203 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 204 "Invalid kind!"); 205 return (Endian == llvm::endianness::little 206 ? InfosLE 207 : InfosBE)[Kind - FirstTargetFixupKind]; 208} 209 210void ARMAsmBackend::handleAssemblerFlag(MCAssemblerFlag Flag) { 211 switch (Flag) { 212 default: 213 break; 214 case MCAF_Code16: 215 setIsThumb(true); 216 break; 217 case MCAF_Code32: 218 setIsThumb(false); 219 break; 220 } 221} 222 223unsigned ARMAsmBackend::getRelaxedOpcode(unsigned Op, 224 const MCSubtargetInfo &STI) const { 225 bool HasThumb2 = STI.hasFeature(ARM::FeatureThumb2); 226 bool HasV8MBaselineOps = STI.hasFeature(ARM::HasV8MBaselineOps); 227 228 switch (Op) { 229 default: 230 return Op; 231 case ARM::tBcc: 232 return HasThumb2 ? (unsigned)ARM::t2Bcc : Op; 233 case ARM::tLDRpci: 234 return HasThumb2 ? (unsigned)ARM::t2LDRpci : Op; 235 case ARM::tADR: 236 return HasThumb2 ? (unsigned)ARM::t2ADR : Op; 237 case ARM::tB: 238 return HasV8MBaselineOps ? (unsigned)ARM::t2B : Op; 239 case ARM::tCBZ: 240 return ARM::tHINT; 241 case ARM::tCBNZ: 242 return ARM::tHINT; 243 } 244} 245 246bool ARMAsmBackend::mayNeedRelaxation(const MCInst &Inst, 247 const MCSubtargetInfo &STI) const { 248 if (getRelaxedOpcode(Inst.getOpcode(), STI) != Inst.getOpcode()) 249 return true; 250 return false; 251} 252 253static const char *checkPCRelOffset(uint64_t Value, int64_t Min, int64_t Max) { 254 int64_t Offset = int64_t(Value) - 4; 255 if (Offset < Min || Offset > Max) 256 return "out of range pc-relative fixup value"; 257 return nullptr; 258} 259 260const char *ARMAsmBackend::reasonForFixupRelaxation(const MCFixup &Fixup, 261 uint64_t Value) const { 262 switch (Fixup.getTargetKind()) { 263 case ARM::fixup_arm_thumb_br: { 264 // Relaxing tB to t2B. tB has a signed 12-bit displacement with the 265 // low bit being an implied zero. There's an implied +4 offset for the 266 // branch, so we adjust the other way here to determine what's 267 // encodable. 268 // 269 // Relax if the value is too big for a (signed) i8. 270 int64_t Offset = int64_t(Value) - 4; 271 if (Offset > 2046 || Offset < -2048) 272 return "out of range pc-relative fixup value"; 273 break; 274 } 275 case ARM::fixup_arm_thumb_bcc: { 276 // Relaxing tBcc to t2Bcc. tBcc has a signed 9-bit displacement with the 277 // low bit being an implied zero. There's an implied +4 offset for the 278 // branch, so we adjust the other way here to determine what's 279 // encodable. 280 // 281 // Relax if the value is too big for a (signed) i8. 282 int64_t Offset = int64_t(Value) - 4; 283 if (Offset > 254 || Offset < -256) 284 return "out of range pc-relative fixup value"; 285 break; 286 } 287 case ARM::fixup_thumb_adr_pcrel_10: 288 case ARM::fixup_arm_thumb_cp: { 289 // If the immediate is negative, greater than 1020, or not a multiple 290 // of four, the wide version of the instruction must be used. 291 int64_t Offset = int64_t(Value) - 4; 292 if (Offset & 3) 293 return "misaligned pc-relative fixup value"; 294 else if (Offset > 1020 || Offset < 0) 295 return "out of range pc-relative fixup value"; 296 break; 297 } 298 case ARM::fixup_arm_thumb_cb: { 299 // If we have a Thumb CBZ or CBNZ instruction and its target is the next 300 // instruction it is actually out of range for the instruction. 301 // It will be changed to a NOP. 302 int64_t Offset = (Value & ~1); 303 if (Offset == 2) 304 return "will be converted to nop"; 305 break; 306 } 307 case ARM::fixup_bf_branch: 308 return checkPCRelOffset(Value, 0, 30); 309 case ARM::fixup_bf_target: 310 return checkPCRelOffset(Value, -0x10000, +0xfffe); 311 case ARM::fixup_bfl_target: 312 return checkPCRelOffset(Value, -0x40000, +0x3fffe); 313 case ARM::fixup_bfc_target: 314 return checkPCRelOffset(Value, -0x1000, +0xffe); 315 case ARM::fixup_wls: 316 return checkPCRelOffset(Value, 0, +0xffe); 317 case ARM::fixup_le: 318 // The offset field in the LE and LETP instructions is an 11-bit 319 // value shifted left by 2 (i.e. 0,2,4,...,4094), and it is 320 // interpreted as a negative offset from the value read from pc, 321 // i.e. from instruction_address+4. 322 // 323 // So an LE instruction can in principle address the instruction 324 // immediately after itself, or (not very usefully) the address 325 // half way through the 4-byte LE. 326 return checkPCRelOffset(Value, -0xffe, 0); 327 case ARM::fixup_bfcsel_else_target: { 328 if (Value != 2 && Value != 4) 329 return "out of range label-relative fixup value"; 330 break; 331 } 332 333 default: 334 llvm_unreachable("Unexpected fixup kind in reasonForFixupRelaxation()!"); 335 } 336 return nullptr; 337} 338 339bool ARMAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup, uint64_t Value, 340 const MCRelaxableFragment *DF, 341 const MCAsmLayout &Layout) const { 342 return reasonForFixupRelaxation(Fixup, Value); 343} 344 345void ARMAsmBackend::relaxInstruction(MCInst &Inst, 346 const MCSubtargetInfo &STI) const { 347 unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode(), STI); 348 349 // Return a diagnostic if we get here w/ a bogus instruction. 350 if (RelaxedOp == Inst.getOpcode()) { 351 SmallString<256> Tmp; 352 raw_svector_ostream OS(Tmp); 353 Inst.dump_pretty(OS); 354 OS << "\n"; 355 report_fatal_error("unexpected instruction to relax: " + OS.str()); 356 } 357 358 // If we are changing Thumb CBZ or CBNZ instruction to a NOP, aka tHINT, we 359 // have to change the operands too. 360 if ((Inst.getOpcode() == ARM::tCBZ || Inst.getOpcode() == ARM::tCBNZ) && 361 RelaxedOp == ARM::tHINT) { 362 MCInst Res; 363 Res.setOpcode(RelaxedOp); 364 Res.addOperand(MCOperand::createImm(0)); 365 Res.addOperand(MCOperand::createImm(14)); 366 Res.addOperand(MCOperand::createReg(0)); 367 Inst = std::move(Res); 368 return; 369 } 370 371 // The rest of instructions we're relaxing have the same operands. 372 // We just need to update to the proper opcode. 373 Inst.setOpcode(RelaxedOp); 374} 375 376bool ARMAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count, 377 const MCSubtargetInfo *STI) const { 378 const uint16_t Thumb1_16bitNopEncoding = 0x46c0; // using MOV r8,r8 379 const uint16_t Thumb2_16bitNopEncoding = 0xbf00; // NOP 380 const uint32_t ARMv4_NopEncoding = 0xe1a00000; // using MOV r0,r0 381 const uint32_t ARMv6T2_NopEncoding = 0xe320f000; // NOP 382 if (isThumb()) { 383 const uint16_t nopEncoding = 384 hasNOP(STI) ? Thumb2_16bitNopEncoding : Thumb1_16bitNopEncoding; 385 uint64_t NumNops = Count / 2; 386 for (uint64_t i = 0; i != NumNops; ++i) 387 support::endian::write(OS, nopEncoding, Endian); 388 if (Count & 1) 389 OS << '\0'; 390 return true; 391 } 392 // ARM mode 393 const uint32_t nopEncoding = 394 hasNOP(STI) ? ARMv6T2_NopEncoding : ARMv4_NopEncoding; 395 uint64_t NumNops = Count / 4; 396 for (uint64_t i = 0; i != NumNops; ++i) 397 support::endian::write(OS, nopEncoding, Endian); 398 // FIXME: should this function return false when unable to write exactly 399 // 'Count' bytes with NOP encodings? 400 switch (Count % 4) { 401 default: 402 break; // No leftover bytes to write 403 case 1: 404 OS << '\0'; 405 break; 406 case 2: 407 OS.write("\0\0", 2); 408 break; 409 case 3: 410 OS.write("\0\0\xa0", 3); 411 break; 412 } 413 414 return true; 415} 416 417static uint32_t swapHalfWords(uint32_t Value, bool IsLittleEndian) { 418 if (IsLittleEndian) { 419 // Note that the halfwords are stored high first and low second in thumb; 420 // so we need to swap the fixup value here to map properly. 421 uint32_t Swapped = (Value & 0xFFFF0000) >> 16; 422 Swapped |= (Value & 0x0000FFFF) << 16; 423 return Swapped; 424 } else 425 return Value; 426} 427 428static uint32_t joinHalfWords(uint32_t FirstHalf, uint32_t SecondHalf, 429 bool IsLittleEndian) { 430 uint32_t Value; 431 432 if (IsLittleEndian) { 433 Value = (SecondHalf & 0xFFFF) << 16; 434 Value |= (FirstHalf & 0xFFFF); 435 } else { 436 Value = (SecondHalf & 0xFFFF); 437 Value |= (FirstHalf & 0xFFFF) << 16; 438 } 439 440 return Value; 441} 442 443unsigned ARMAsmBackend::adjustFixupValue(const MCAssembler &Asm, 444 const MCFixup &Fixup, 445 const MCValue &Target, uint64_t Value, 446 bool IsResolved, MCContext &Ctx, 447 const MCSubtargetInfo* STI) const { 448 unsigned Kind = Fixup.getKind(); 449 450 // MachO tries to make .o files that look vaguely pre-linked, so for MOVW/MOVT 451 // and .word relocations they put the Thumb bit into the addend if possible. 452 // Other relocation types don't want this bit though (branches couldn't encode 453 // it if it *was* present, and no other relocations exist) and it can 454 // interfere with checking valid expressions. 455 if (const MCSymbolRefExpr *A = Target.getSymA()) { 456 if (A->hasSubsectionsViaSymbols() && Asm.isThumbFunc(&A->getSymbol()) && 457 A->getSymbol().isExternal() && 458 (Kind == FK_Data_4 || Kind == ARM::fixup_arm_movw_lo16 || 459 Kind == ARM::fixup_arm_movt_hi16 || Kind == ARM::fixup_t2_movw_lo16 || 460 Kind == ARM::fixup_t2_movt_hi16)) 461 Value |= 1; 462 } 463 464 switch (Kind) { 465 default: 466 return 0; 467 case FK_Data_1: 468 case FK_Data_2: 469 case FK_Data_4: 470 return Value; 471 case FK_SecRel_2: 472 return Value; 473 case FK_SecRel_4: 474 return Value; 475 case ARM::fixup_arm_movt_hi16: 476 assert(STI != nullptr); 477 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF()) 478 Value >>= 16; 479 [[fallthrough]]; 480 case ARM::fixup_arm_movw_lo16: { 481 unsigned Hi4 = (Value & 0xF000) >> 12; 482 unsigned Lo12 = Value & 0x0FFF; 483 // inst{19-16} = Hi4; 484 // inst{11-0} = Lo12; 485 Value = (Hi4 << 16) | (Lo12); 486 return Value; 487 } 488 case ARM::fixup_t2_movt_hi16: 489 assert(STI != nullptr); 490 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF()) 491 Value >>= 16; 492 [[fallthrough]]; 493 case ARM::fixup_t2_movw_lo16: { 494 unsigned Hi4 = (Value & 0xF000) >> 12; 495 unsigned i = (Value & 0x800) >> 11; 496 unsigned Mid3 = (Value & 0x700) >> 8; 497 unsigned Lo8 = Value & 0x0FF; 498 // inst{19-16} = Hi4; 499 // inst{26} = i; 500 // inst{14-12} = Mid3; 501 // inst{7-0} = Lo8; 502 Value = (Hi4 << 16) | (i << 26) | (Mid3 << 12) | (Lo8); 503 return swapHalfWords(Value, Endian == llvm::endianness::little); 504 } 505 case ARM::fixup_arm_thumb_upper_8_15: 506 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF()) 507 return (Value & 0xff000000) >> 24; 508 return Value & 0xff; 509 case ARM::fixup_arm_thumb_upper_0_7: 510 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF()) 511 return (Value & 0x00ff0000) >> 16; 512 return Value & 0xff; 513 case ARM::fixup_arm_thumb_lower_8_15: 514 if (IsResolved || !STI->getTargetTriple().isOSBinFormatELF()) 515 return (Value & 0x0000ff00) >> 8; 516 return Value & 0xff; 517 case ARM::fixup_arm_thumb_lower_0_7: 518 return Value & 0x000000ff; 519 case ARM::fixup_arm_ldst_pcrel_12: 520 // ARM PC-relative values are offset by 8. 521 Value -= 4; 522 [[fallthrough]]; 523 case ARM::fixup_t2_ldst_pcrel_12: 524 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 525 Value -= 4; 526 [[fallthrough]]; 527 case ARM::fixup_arm_ldst_abs_12: { 528 bool isAdd = true; 529 if ((int64_t)Value < 0) { 530 Value = -Value; 531 isAdd = false; 532 } 533 if (Value >= 4096) { 534 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 535 return 0; 536 } 537 Value |= isAdd << 23; 538 539 // Same addressing mode as fixup_arm_pcrel_10, 540 // but with 16-bit halfwords swapped. 541 if (Kind == ARM::fixup_t2_ldst_pcrel_12) 542 return swapHalfWords(Value, Endian == llvm::endianness::little); 543 544 return Value; 545 } 546 case ARM::fixup_arm_adr_pcrel_12: { 547 // ARM PC-relative values are offset by 8. 548 Value -= 8; 549 unsigned opc = 4; // bits {24-21}. Default to add: 0b0100 550 if ((int64_t)Value < 0) { 551 Value = -Value; 552 opc = 2; // 0b0010 553 } 554 if (ARM_AM::getSOImmVal(Value) == -1) { 555 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 556 return 0; 557 } 558 // Encode the immediate and shift the opcode into place. 559 return ARM_AM::getSOImmVal(Value) | (opc << 21); 560 } 561 562 case ARM::fixup_t2_adr_pcrel_12: { 563 Value -= 4; 564 unsigned opc = 0; 565 if ((int64_t)Value < 0) { 566 Value = -Value; 567 opc = 5; 568 } 569 570 uint32_t out = (opc << 21); 571 out |= (Value & 0x800) << 15; 572 out |= (Value & 0x700) << 4; 573 out |= (Value & 0x0FF); 574 575 return swapHalfWords(out, Endian == llvm::endianness::little); 576 } 577 578 case ARM::fixup_arm_condbranch: 579 case ARM::fixup_arm_uncondbranch: 580 case ARM::fixup_arm_uncondbl: 581 case ARM::fixup_arm_condbl: 582 case ARM::fixup_arm_blx: 583 // These values don't encode the low two bits since they're always zero. 584 // Offset by 8 just as above. 585 if (const MCSymbolRefExpr *SRE = 586 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 587 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL) 588 return 0; 589 return 0xffffff & ((Value - 8) >> 2); 590 case ARM::fixup_t2_uncondbranch: { 591 Value = Value - 4; 592 if (!isInt<25>(Value)) { 593 Ctx.reportError(Fixup.getLoc(), "Relocation out of range"); 594 return 0; 595 } 596 597 Value >>= 1; // Low bit is not encoded. 598 599 uint32_t out = 0; 600 bool I = Value & 0x800000; 601 bool J1 = Value & 0x400000; 602 bool J2 = Value & 0x200000; 603 J1 ^= I; 604 J2 ^= I; 605 606 out |= I << 26; // S bit 607 out |= !J1 << 13; // J1 bit 608 out |= !J2 << 11; // J2 bit 609 out |= (Value & 0x1FF800) << 5; // imm6 field 610 out |= (Value & 0x0007FF); // imm11 field 611 612 return swapHalfWords(out, Endian == llvm::endianness::little); 613 } 614 case ARM::fixup_t2_condbranch: { 615 Value = Value - 4; 616 if (!isInt<21>(Value)) { 617 Ctx.reportError(Fixup.getLoc(), "Relocation out of range"); 618 return 0; 619 } 620 621 Value >>= 1; // Low bit is not encoded. 622 623 uint64_t out = 0; 624 out |= (Value & 0x80000) << 7; // S bit 625 out |= (Value & 0x40000) >> 7; // J2 bit 626 out |= (Value & 0x20000) >> 4; // J1 bit 627 out |= (Value & 0x1F800) << 5; // imm6 field 628 out |= (Value & 0x007FF); // imm11 field 629 630 return swapHalfWords(out, Endian == llvm::endianness::little); 631 } 632 case ARM::fixup_arm_thumb_bl: { 633 if (!isInt<25>(Value - 4) || 634 (!STI->hasFeature(ARM::FeatureThumb2) && 635 !STI->hasFeature(ARM::HasV8MBaselineOps) && 636 !STI->hasFeature(ARM::HasV6MOps) && 637 !isInt<23>(Value - 4))) { 638 Ctx.reportError(Fixup.getLoc(), "Relocation out of range"); 639 return 0; 640 } 641 642 // The value doesn't encode the low bit (always zero) and is offset by 643 // four. The 32-bit immediate value is encoded as 644 // imm32 = SignExtend(S:I1:I2:imm10:imm11:0) 645 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 646 // The value is encoded into disjoint bit positions in the destination 647 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 648 // J = either J1 or J2 bit 649 // 650 // BL: xxxxxSIIIIIIIIII xxJxJIIIIIIIIIII 651 // 652 // Note that the halfwords are stored high first, low second; so we need 653 // to transpose the fixup value here to map properly. 654 uint32_t offset = (Value - 4) >> 1; 655 uint32_t signBit = (offset & 0x800000) >> 23; 656 uint32_t I1Bit = (offset & 0x400000) >> 22; 657 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 658 uint32_t I2Bit = (offset & 0x200000) >> 21; 659 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 660 uint32_t imm10Bits = (offset & 0x1FF800) >> 11; 661 uint32_t imm11Bits = (offset & 0x000007FF); 662 663 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10Bits); 664 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 665 (uint16_t)imm11Bits); 666 return joinHalfWords(FirstHalf, SecondHalf, 667 Endian == llvm::endianness::little); 668 } 669 case ARM::fixup_arm_thumb_blx: { 670 // The value doesn't encode the low two bits (always zero) and is offset by 671 // four (see fixup_arm_thumb_cp). The 32-bit immediate value is encoded as 672 // imm32 = SignExtend(S:I1:I2:imm10H:imm10L:00) 673 // where I1 = NOT(J1 ^ S) and I2 = NOT(J2 ^ S). 674 // The value is encoded into disjoint bit positions in the destination 675 // opcode. x = unchanged, I = immediate value bit, S = sign extension bit, 676 // J = either J1 or J2 bit, 0 = zero. 677 // 678 // BLX: xxxxxSIIIIIIIIII xxJxJIIIIIIIIII0 679 // 680 // Note that the halfwords are stored high first, low second; so we need 681 // to transpose the fixup value here to map properly. 682 if (Value % 4 != 0) { 683 Ctx.reportError(Fixup.getLoc(), "misaligned ARM call destination"); 684 return 0; 685 } 686 687 uint32_t offset = (Value - 4) >> 2; 688 if (const MCSymbolRefExpr *SRE = 689 dyn_cast<MCSymbolRefExpr>(Fixup.getValue())) 690 if (SRE->getKind() == MCSymbolRefExpr::VK_TLSCALL) 691 offset = 0; 692 uint32_t signBit = (offset & 0x400000) >> 22; 693 uint32_t I1Bit = (offset & 0x200000) >> 21; 694 uint32_t J1Bit = (I1Bit ^ 0x1) ^ signBit; 695 uint32_t I2Bit = (offset & 0x100000) >> 20; 696 uint32_t J2Bit = (I2Bit ^ 0x1) ^ signBit; 697 uint32_t imm10HBits = (offset & 0xFFC00) >> 10; 698 uint32_t imm10LBits = (offset & 0x3FF); 699 700 uint32_t FirstHalf = (((uint16_t)signBit << 10) | (uint16_t)imm10HBits); 701 uint32_t SecondHalf = (((uint16_t)J1Bit << 13) | ((uint16_t)J2Bit << 11) | 702 ((uint16_t)imm10LBits) << 1); 703 return joinHalfWords(FirstHalf, SecondHalf, 704 Endian == llvm::endianness::little); 705 } 706 case ARM::fixup_thumb_adr_pcrel_10: 707 case ARM::fixup_arm_thumb_cp: 708 // On CPUs supporting Thumb2, this will be relaxed to an ldr.w, otherwise we 709 // could have an error on our hands. 710 assert(STI != nullptr); 711 if (!STI->hasFeature(ARM::FeatureThumb2) && IsResolved) { 712 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 713 if (FixupDiagnostic) { 714 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 715 return 0; 716 } 717 } 718 // Offset by 4, and don't encode the low two bits. 719 return ((Value - 4) >> 2) & 0xff; 720 case ARM::fixup_arm_thumb_cb: { 721 // CB instructions can only branch to offsets in [4, 126] in multiples of 2 722 // so ensure that the raw value LSB is zero and it lies in [2, 130]. 723 // An offset of 2 will be relaxed to a NOP. 724 if ((int64_t)Value < 2 || Value > 0x82 || Value & 1) { 725 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 726 return 0; 727 } 728 // Offset by 4 and don't encode the lower bit, which is always 0. 729 // FIXME: diagnose if no Thumb2 730 uint32_t Binary = (Value - 4) >> 1; 731 return ((Binary & 0x20) << 4) | ((Binary & 0x1f) << 3); 732 } 733 case ARM::fixup_arm_thumb_br: 734 // Offset by 4 and don't encode the lower bit, which is always 0. 735 assert(STI != nullptr); 736 if (!STI->hasFeature(ARM::FeatureThumb2) && 737 !STI->hasFeature(ARM::HasV8MBaselineOps)) { 738 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 739 if (FixupDiagnostic) { 740 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 741 return 0; 742 } 743 } 744 return ((Value - 4) >> 1) & 0x7ff; 745 case ARM::fixup_arm_thumb_bcc: 746 // Offset by 4 and don't encode the lower bit, which is always 0. 747 assert(STI != nullptr); 748 if (!STI->hasFeature(ARM::FeatureThumb2)) { 749 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 750 if (FixupDiagnostic) { 751 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 752 return 0; 753 } 754 } 755 return ((Value - 4) >> 1) & 0xff; 756 case ARM::fixup_arm_pcrel_10_unscaled: { 757 Value = Value - 8; // ARM fixups offset by an additional word and don't 758 // need to adjust for the half-word ordering. 759 bool isAdd = true; 760 if ((int64_t)Value < 0) { 761 Value = -Value; 762 isAdd = false; 763 } 764 // The value has the low 4 bits encoded in [3:0] and the high 4 in [11:8]. 765 if (Value >= 256) { 766 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 767 return 0; 768 } 769 Value = (Value & 0xf) | ((Value & 0xf0) << 4); 770 return Value | (isAdd << 23); 771 } 772 case ARM::fixup_arm_pcrel_10: 773 Value = Value - 4; // ARM fixups offset by an additional word and don't 774 // need to adjust for the half-word ordering. 775 [[fallthrough]]; 776 case ARM::fixup_t2_pcrel_10: { 777 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 778 Value = Value - 4; 779 bool isAdd = true; 780 if ((int64_t)Value < 0) { 781 Value = -Value; 782 isAdd = false; 783 } 784 // These values don't encode the low two bits since they're always zero. 785 Value >>= 2; 786 if (Value >= 256) { 787 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 788 return 0; 789 } 790 Value |= isAdd << 23; 791 792 // Same addressing mode as fixup_arm_pcrel_10, but with 16-bit halfwords 793 // swapped. 794 if (Kind == ARM::fixup_t2_pcrel_10) 795 return swapHalfWords(Value, Endian == llvm::endianness::little); 796 797 return Value; 798 } 799 case ARM::fixup_arm_pcrel_9: 800 Value = Value - 4; // ARM fixups offset by an additional word and don't 801 // need to adjust for the half-word ordering. 802 [[fallthrough]]; 803 case ARM::fixup_t2_pcrel_9: { 804 // Offset by 4, adjusted by two due to the half-word ordering of thumb. 805 Value = Value - 4; 806 bool isAdd = true; 807 if ((int64_t)Value < 0) { 808 Value = -Value; 809 isAdd = false; 810 } 811 // These values don't encode the low bit since it's always zero. 812 if (Value & 1) { 813 Ctx.reportError(Fixup.getLoc(), "invalid value for this fixup"); 814 return 0; 815 } 816 Value >>= 1; 817 if (Value >= 256) { 818 Ctx.reportError(Fixup.getLoc(), "out of range pc-relative fixup value"); 819 return 0; 820 } 821 Value |= isAdd << 23; 822 823 // Same addressing mode as fixup_arm_pcrel_9, but with 16-bit halfwords 824 // swapped. 825 if (Kind == ARM::fixup_t2_pcrel_9) 826 return swapHalfWords(Value, Endian == llvm::endianness::little); 827 828 return Value; 829 } 830 case ARM::fixup_arm_mod_imm: 831 Value = ARM_AM::getSOImmVal(Value); 832 if (Value >> 12) { 833 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value"); 834 return 0; 835 } 836 return Value; 837 case ARM::fixup_t2_so_imm: { 838 Value = ARM_AM::getT2SOImmVal(Value); 839 if ((int64_t)Value < 0) { 840 Ctx.reportError(Fixup.getLoc(), "out of range immediate fixup value"); 841 return 0; 842 } 843 // Value will contain a 12-bit value broken up into a 4-bit shift in bits 844 // 11:8 and the 8-bit immediate in 0:7. The instruction has the immediate 845 // in 0:7. The 4-bit shift is split up into i:imm3 where i is placed at bit 846 // 10 of the upper half-word and imm3 is placed at 14:12 of the lower 847 // half-word. 848 uint64_t EncValue = 0; 849 EncValue |= (Value & 0x800) << 15; 850 EncValue |= (Value & 0x700) << 4; 851 EncValue |= (Value & 0xff); 852 return swapHalfWords(EncValue, Endian == llvm::endianness::little); 853 } 854 case ARM::fixup_bf_branch: { 855 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 856 if (FixupDiagnostic) { 857 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 858 return 0; 859 } 860 uint32_t out = (((Value - 4) >> 1) & 0xf) << 23; 861 return swapHalfWords(out, Endian == llvm::endianness::little); 862 } 863 case ARM::fixup_bf_target: 864 case ARM::fixup_bfl_target: 865 case ARM::fixup_bfc_target: { 866 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 867 if (FixupDiagnostic) { 868 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 869 return 0; 870 } 871 uint32_t out = 0; 872 uint32_t HighBitMask = (Kind == ARM::fixup_bf_target ? 0xf800 : 873 Kind == ARM::fixup_bfl_target ? 0x3f800 : 0x800); 874 out |= (((Value - 4) >> 1) & 0x1) << 11; 875 out |= (((Value - 4) >> 1) & 0x7fe); 876 out |= (((Value - 4) >> 1) & HighBitMask) << 5; 877 return swapHalfWords(out, Endian == llvm::endianness::little); 878 } 879 case ARM::fixup_bfcsel_else_target: { 880 // If this is a fixup of a branch future's else target then it should be a 881 // constant MCExpr representing the distance between the branch targetted 882 // and the instruction after that same branch. 883 Value = Target.getConstant(); 884 885 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 886 if (FixupDiagnostic) { 887 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 888 return 0; 889 } 890 uint32_t out = ((Value >> 2) & 1) << 17; 891 return swapHalfWords(out, Endian == llvm::endianness::little); 892 } 893 case ARM::fixup_wls: 894 case ARM::fixup_le: { 895 const char *FixupDiagnostic = reasonForFixupRelaxation(Fixup, Value); 896 if (FixupDiagnostic) { 897 Ctx.reportError(Fixup.getLoc(), FixupDiagnostic); 898 return 0; 899 } 900 uint64_t real_value = Value - 4; 901 uint32_t out = 0; 902 if (Kind == ARM::fixup_le) 903 real_value = -real_value; 904 out |= ((real_value >> 1) & 0x1) << 11; 905 out |= ((real_value >> 1) & 0x7fe); 906 return swapHalfWords(out, Endian == llvm::endianness::little); 907 } 908 } 909} 910 911bool ARMAsmBackend::shouldForceRelocation(const MCAssembler &Asm, 912 const MCFixup &Fixup, 913 const MCValue &Target, 914 const MCSubtargetInfo *STI) { 915 const MCSymbolRefExpr *A = Target.getSymA(); 916 const MCSymbol *Sym = A ? &A->getSymbol() : nullptr; 917 const unsigned FixupKind = Fixup.getKind(); 918 if (FixupKind >= FirstLiteralRelocationKind) 919 return true; 920 if (FixupKind == ARM::fixup_arm_thumb_bl) { 921 assert(Sym && "How did we resolve this?"); 922 923 // If the symbol is external the linker will handle it. 924 // FIXME: Should we handle it as an optimization? 925 926 // If the symbol is out of range, produce a relocation and hope the 927 // linker can handle it. GNU AS produces an error in this case. 928 if (Sym->isExternal()) 929 return true; 930 } 931 // Create relocations for unconditional branches to function symbols with 932 // different execution mode in ELF binaries. 933 if (Sym && Sym->isELF()) { 934 unsigned Type = cast<MCSymbolELF>(Sym)->getType(); 935 if ((Type == ELF::STT_FUNC || Type == ELF::STT_GNU_IFUNC)) { 936 if (Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_uncondbranch)) 937 return true; 938 if (!Asm.isThumbFunc(Sym) && (FixupKind == ARM::fixup_arm_thumb_br || 939 FixupKind == ARM::fixup_arm_thumb_bl || 940 FixupKind == ARM::fixup_t2_condbranch || 941 FixupKind == ARM::fixup_t2_uncondbranch)) 942 return true; 943 } 944 } 945 // We must always generate a relocation for BL/BLX instructions if we have 946 // a symbol to reference, as the linker relies on knowing the destination 947 // symbol's thumb-ness to get interworking right. 948 if (A && (FixupKind == ARM::fixup_arm_thumb_blx || 949 FixupKind == ARM::fixup_arm_blx || 950 FixupKind == ARM::fixup_arm_uncondbl || 951 FixupKind == ARM::fixup_arm_condbl)) 952 return true; 953 return false; 954} 955 956/// getFixupKindNumBytes - The number of bytes the fixup may change. 957static unsigned getFixupKindNumBytes(unsigned Kind) { 958 switch (Kind) { 959 default: 960 llvm_unreachable("Unknown fixup kind!"); 961 962 case FK_Data_1: 963 case ARM::fixup_arm_thumb_bcc: 964 case ARM::fixup_arm_thumb_cp: 965 case ARM::fixup_thumb_adr_pcrel_10: 966 case ARM::fixup_arm_thumb_upper_8_15: 967 case ARM::fixup_arm_thumb_upper_0_7: 968 case ARM::fixup_arm_thumb_lower_8_15: 969 case ARM::fixup_arm_thumb_lower_0_7: 970 return 1; 971 972 case FK_Data_2: 973 case ARM::fixup_arm_thumb_br: 974 case ARM::fixup_arm_thumb_cb: 975 case ARM::fixup_arm_mod_imm: 976 return 2; 977 978 case ARM::fixup_arm_pcrel_10_unscaled: 979 case ARM::fixup_arm_ldst_pcrel_12: 980 case ARM::fixup_arm_pcrel_10: 981 case ARM::fixup_arm_pcrel_9: 982 case ARM::fixup_arm_ldst_abs_12: 983 case ARM::fixup_arm_adr_pcrel_12: 984 case ARM::fixup_arm_uncondbl: 985 case ARM::fixup_arm_condbl: 986 case ARM::fixup_arm_blx: 987 case ARM::fixup_arm_condbranch: 988 case ARM::fixup_arm_uncondbranch: 989 return 3; 990 991 case FK_Data_4: 992 case ARM::fixup_t2_ldst_pcrel_12: 993 case ARM::fixup_t2_condbranch: 994 case ARM::fixup_t2_uncondbranch: 995 case ARM::fixup_t2_pcrel_10: 996 case ARM::fixup_t2_pcrel_9: 997 case ARM::fixup_t2_adr_pcrel_12: 998 case ARM::fixup_arm_thumb_bl: 999 case ARM::fixup_arm_thumb_blx: 1000 case ARM::fixup_arm_movt_hi16: 1001 case ARM::fixup_arm_movw_lo16: 1002 case ARM::fixup_t2_movt_hi16: 1003 case ARM::fixup_t2_movw_lo16: 1004 case ARM::fixup_t2_so_imm: 1005 case ARM::fixup_bf_branch: 1006 case ARM::fixup_bf_target: 1007 case ARM::fixup_bfl_target: 1008 case ARM::fixup_bfc_target: 1009 case ARM::fixup_bfcsel_else_target: 1010 case ARM::fixup_wls: 1011 case ARM::fixup_le: 1012 return 4; 1013 1014 case FK_SecRel_2: 1015 return 2; 1016 case FK_SecRel_4: 1017 return 4; 1018 } 1019} 1020 1021/// getFixupKindContainerSizeBytes - The number of bytes of the 1022/// container involved in big endian. 1023static unsigned getFixupKindContainerSizeBytes(unsigned Kind) { 1024 switch (Kind) { 1025 default: 1026 llvm_unreachable("Unknown fixup kind!"); 1027 1028 case FK_Data_1: 1029 return 1; 1030 case FK_Data_2: 1031 return 2; 1032 case FK_Data_4: 1033 return 4; 1034 1035 case ARM::fixup_arm_thumb_bcc: 1036 case ARM::fixup_arm_thumb_cp: 1037 case ARM::fixup_thumb_adr_pcrel_10: 1038 case ARM::fixup_arm_thumb_br: 1039 case ARM::fixup_arm_thumb_cb: 1040 case ARM::fixup_arm_thumb_upper_8_15: 1041 case ARM::fixup_arm_thumb_upper_0_7: 1042 case ARM::fixup_arm_thumb_lower_8_15: 1043 case ARM::fixup_arm_thumb_lower_0_7: 1044 // Instruction size is 2 bytes. 1045 return 2; 1046 1047 case ARM::fixup_arm_pcrel_10_unscaled: 1048 case ARM::fixup_arm_ldst_pcrel_12: 1049 case ARM::fixup_arm_pcrel_10: 1050 case ARM::fixup_arm_pcrel_9: 1051 case ARM::fixup_arm_adr_pcrel_12: 1052 case ARM::fixup_arm_uncondbl: 1053 case ARM::fixup_arm_condbl: 1054 case ARM::fixup_arm_blx: 1055 case ARM::fixup_arm_condbranch: 1056 case ARM::fixup_arm_uncondbranch: 1057 case ARM::fixup_t2_ldst_pcrel_12: 1058 case ARM::fixup_t2_condbranch: 1059 case ARM::fixup_t2_uncondbranch: 1060 case ARM::fixup_t2_pcrel_10: 1061 case ARM::fixup_t2_pcrel_9: 1062 case ARM::fixup_t2_adr_pcrel_12: 1063 case ARM::fixup_arm_thumb_bl: 1064 case ARM::fixup_arm_thumb_blx: 1065 case ARM::fixup_arm_movt_hi16: 1066 case ARM::fixup_arm_movw_lo16: 1067 case ARM::fixup_t2_movt_hi16: 1068 case ARM::fixup_t2_movw_lo16: 1069 case ARM::fixup_arm_mod_imm: 1070 case ARM::fixup_t2_so_imm: 1071 case ARM::fixup_bf_branch: 1072 case ARM::fixup_bf_target: 1073 case ARM::fixup_bfl_target: 1074 case ARM::fixup_bfc_target: 1075 case ARM::fixup_bfcsel_else_target: 1076 case ARM::fixup_wls: 1077 case ARM::fixup_le: 1078 // Instruction size is 4 bytes. 1079 return 4; 1080 } 1081} 1082 1083void ARMAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 1084 const MCValue &Target, 1085 MutableArrayRef<char> Data, uint64_t Value, 1086 bool IsResolved, 1087 const MCSubtargetInfo* STI) const { 1088 unsigned Kind = Fixup.getKind(); 1089 if (Kind >= FirstLiteralRelocationKind) 1090 return; 1091 MCContext &Ctx = Asm.getContext(); 1092 Value = adjustFixupValue(Asm, Fixup, Target, Value, IsResolved, Ctx, STI); 1093 if (!Value) 1094 return; // Doesn't change encoding. 1095 const unsigned NumBytes = getFixupKindNumBytes(Kind); 1096 1097 unsigned Offset = Fixup.getOffset(); 1098 assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!"); 1099 1100 // Used to point to big endian bytes. 1101 unsigned FullSizeBytes; 1102 if (Endian == llvm::endianness::big) { 1103 FullSizeBytes = getFixupKindContainerSizeBytes(Kind); 1104 assert((Offset + FullSizeBytes) <= Data.size() && "Invalid fixup size!"); 1105 assert(NumBytes <= FullSizeBytes && "Invalid fixup size!"); 1106 } 1107 1108 // For each byte of the fragment that the fixup touches, mask in the bits from 1109 // the fixup value. The Value has been "split up" into the appropriate 1110 // bitfields above. 1111 for (unsigned i = 0; i != NumBytes; ++i) { 1112 unsigned Idx = 1113 Endian == llvm::endianness::little ? i : (FullSizeBytes - 1 - i); 1114 Data[Offset + Idx] |= uint8_t((Value >> (i * 8)) & 0xff); 1115 } 1116} 1117 1118namespace CU { 1119 1120/// Compact unwind encoding values. 1121enum CompactUnwindEncodings { 1122 UNWIND_ARM_MODE_MASK = 0x0F000000, 1123 UNWIND_ARM_MODE_FRAME = 0x01000000, 1124 UNWIND_ARM_MODE_FRAME_D = 0x02000000, 1125 UNWIND_ARM_MODE_DWARF = 0x04000000, 1126 1127 UNWIND_ARM_FRAME_STACK_ADJUST_MASK = 0x00C00000, 1128 1129 UNWIND_ARM_FRAME_FIRST_PUSH_R4 = 0x00000001, 1130 UNWIND_ARM_FRAME_FIRST_PUSH_R5 = 0x00000002, 1131 UNWIND_ARM_FRAME_FIRST_PUSH_R6 = 0x00000004, 1132 1133 UNWIND_ARM_FRAME_SECOND_PUSH_R8 = 0x00000008, 1134 UNWIND_ARM_FRAME_SECOND_PUSH_R9 = 0x00000010, 1135 UNWIND_ARM_FRAME_SECOND_PUSH_R10 = 0x00000020, 1136 UNWIND_ARM_FRAME_SECOND_PUSH_R11 = 0x00000040, 1137 UNWIND_ARM_FRAME_SECOND_PUSH_R12 = 0x00000080, 1138 1139 UNWIND_ARM_FRAME_D_REG_COUNT_MASK = 0x00000F00, 1140 1141 UNWIND_ARM_DWARF_SECTION_OFFSET = 0x00FFFFFF 1142}; 1143 1144} // end CU namespace 1145 1146/// Generate compact unwind encoding for the function based on the CFI 1147/// instructions. If the CFI instructions describe a frame that cannot be 1148/// encoded in compact unwind, the method returns UNWIND_ARM_MODE_DWARF which 1149/// tells the runtime to fallback and unwind using dwarf. 1150uint32_t ARMAsmBackendDarwin::generateCompactUnwindEncoding( 1151 const MCDwarfFrameInfo *FI, const MCContext *Ctxt) const { 1152 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "generateCU()\n"); 1153 // Only armv7k uses CFI based unwinding. 1154 if (Subtype != MachO::CPU_SUBTYPE_ARM_V7K) 1155 return 0; 1156 // No .cfi directives means no frame. 1157 ArrayRef<MCCFIInstruction> Instrs = FI->Instructions; 1158 if (Instrs.empty()) 1159 return 0; 1160 if (!isDarwinCanonicalPersonality(FI->Personality) && 1161 !Ctxt->emitCompactUnwindNonCanonical()) 1162 return CU::UNWIND_ARM_MODE_DWARF; 1163 1164 // Start off assuming CFA is at SP+0. 1165 unsigned CFARegister = ARM::SP; 1166 int CFARegisterOffset = 0; 1167 // Mark savable registers as initially unsaved 1168 DenseMap<unsigned, int> RegOffsets; 1169 int FloatRegCount = 0; 1170 // Process each .cfi directive and build up compact unwind info. 1171 for (const MCCFIInstruction &Inst : Instrs) { 1172 unsigned Reg; 1173 switch (Inst.getOperation()) { 1174 case MCCFIInstruction::OpDefCfa: // DW_CFA_def_cfa 1175 CFARegisterOffset = Inst.getOffset(); 1176 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); 1177 break; 1178 case MCCFIInstruction::OpDefCfaOffset: // DW_CFA_def_cfa_offset 1179 CFARegisterOffset = Inst.getOffset(); 1180 break; 1181 case MCCFIInstruction::OpDefCfaRegister: // DW_CFA_def_cfa_register 1182 CFARegister = *MRI.getLLVMRegNum(Inst.getRegister(), true); 1183 break; 1184 case MCCFIInstruction::OpOffset: // DW_CFA_offset 1185 Reg = *MRI.getLLVMRegNum(Inst.getRegister(), true); 1186 if (ARMMCRegisterClasses[ARM::GPRRegClassID].contains(Reg)) 1187 RegOffsets[Reg] = Inst.getOffset(); 1188 else if (ARMMCRegisterClasses[ARM::DPRRegClassID].contains(Reg)) { 1189 RegOffsets[Reg] = Inst.getOffset(); 1190 ++FloatRegCount; 1191 } else { 1192 DEBUG_WITH_TYPE("compact-unwind", 1193 llvm::dbgs() << ".cfi_offset on unknown register=" 1194 << Inst.getRegister() << "\n"); 1195 return CU::UNWIND_ARM_MODE_DWARF; 1196 } 1197 break; 1198 case MCCFIInstruction::OpRelOffset: // DW_CFA_advance_loc 1199 // Ignore 1200 break; 1201 default: 1202 // Directive not convertable to compact unwind, bail out. 1203 DEBUG_WITH_TYPE("compact-unwind", 1204 llvm::dbgs() 1205 << "CFI directive not compatible with compact " 1206 "unwind encoding, opcode=" << Inst.getOperation() 1207 << "\n"); 1208 return CU::UNWIND_ARM_MODE_DWARF; 1209 break; 1210 } 1211 } 1212 1213 // If no frame set up, return no unwind info. 1214 if ((CFARegister == ARM::SP) && (CFARegisterOffset == 0)) 1215 return 0; 1216 1217 // Verify standard frame (lr/r7) was used. 1218 if (CFARegister != ARM::R7) { 1219 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() << "frame register is " 1220 << CFARegister 1221 << " instead of r7\n"); 1222 return CU::UNWIND_ARM_MODE_DWARF; 1223 } 1224 int StackAdjust = CFARegisterOffset - 8; 1225 if (RegOffsets.lookup(ARM::LR) != (-4 - StackAdjust)) { 1226 DEBUG_WITH_TYPE("compact-unwind", 1227 llvm::dbgs() 1228 << "LR not saved as standard frame, StackAdjust=" 1229 << StackAdjust 1230 << ", CFARegisterOffset=" << CFARegisterOffset 1231 << ", lr save at offset=" << RegOffsets[14] << "\n"); 1232 return CU::UNWIND_ARM_MODE_DWARF; 1233 } 1234 if (RegOffsets.lookup(ARM::R7) != (-8 - StackAdjust)) { 1235 DEBUG_WITH_TYPE("compact-unwind", 1236 llvm::dbgs() << "r7 not saved as standard frame\n"); 1237 return CU::UNWIND_ARM_MODE_DWARF; 1238 } 1239 uint32_t CompactUnwindEncoding = CU::UNWIND_ARM_MODE_FRAME; 1240 1241 // If var-args are used, there may be a stack adjust required. 1242 switch (StackAdjust) { 1243 case 0: 1244 break; 1245 case 4: 1246 CompactUnwindEncoding |= 0x00400000; 1247 break; 1248 case 8: 1249 CompactUnwindEncoding |= 0x00800000; 1250 break; 1251 case 12: 1252 CompactUnwindEncoding |= 0x00C00000; 1253 break; 1254 default: 1255 DEBUG_WITH_TYPE("compact-unwind", llvm::dbgs() 1256 << ".cfi_def_cfa stack adjust (" 1257 << StackAdjust << ") out of range\n"); 1258 return CU::UNWIND_ARM_MODE_DWARF; 1259 } 1260 1261 // If r6 is saved, it must be right below r7. 1262 static struct { 1263 unsigned Reg; 1264 unsigned Encoding; 1265 } GPRCSRegs[] = {{ARM::R6, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R6}, 1266 {ARM::R5, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R5}, 1267 {ARM::R4, CU::UNWIND_ARM_FRAME_FIRST_PUSH_R4}, 1268 {ARM::R12, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R12}, 1269 {ARM::R11, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R11}, 1270 {ARM::R10, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R10}, 1271 {ARM::R9, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R9}, 1272 {ARM::R8, CU::UNWIND_ARM_FRAME_SECOND_PUSH_R8}}; 1273 1274 int CurOffset = -8 - StackAdjust; 1275 for (auto CSReg : GPRCSRegs) { 1276 auto Offset = RegOffsets.find(CSReg.Reg); 1277 if (Offset == RegOffsets.end()) 1278 continue; 1279 1280 int RegOffset = Offset->second; 1281 if (RegOffset != CurOffset - 4) { 1282 DEBUG_WITH_TYPE("compact-unwind", 1283 llvm::dbgs() << MRI.getName(CSReg.Reg) << " saved at " 1284 << RegOffset << " but only supported at " 1285 << CurOffset << "\n"); 1286 return CU::UNWIND_ARM_MODE_DWARF; 1287 } 1288 CompactUnwindEncoding |= CSReg.Encoding; 1289 CurOffset -= 4; 1290 } 1291 1292 // If no floats saved, we are done. 1293 if (FloatRegCount == 0) 1294 return CompactUnwindEncoding; 1295 1296 // Switch mode to include D register saving. 1297 CompactUnwindEncoding &= ~CU::UNWIND_ARM_MODE_MASK; 1298 CompactUnwindEncoding |= CU::UNWIND_ARM_MODE_FRAME_D; 1299 1300 // FIXME: supporting more than 4 saved D-registers compactly would be trivial, 1301 // but needs coordination with the linker and libunwind. 1302 if (FloatRegCount > 4) { 1303 DEBUG_WITH_TYPE("compact-unwind", 1304 llvm::dbgs() << "unsupported number of D registers saved (" 1305 << FloatRegCount << ")\n"); 1306 return CU::UNWIND_ARM_MODE_DWARF; 1307 } 1308 1309 // Floating point registers must either be saved sequentially, or we defer to 1310 // DWARF. No gaps allowed here so check that each saved d-register is 1311 // precisely where it should be. 1312 static unsigned FPRCSRegs[] = { ARM::D8, ARM::D10, ARM::D12, ARM::D14 }; 1313 for (int Idx = FloatRegCount - 1; Idx >= 0; --Idx) { 1314 auto Offset = RegOffsets.find(FPRCSRegs[Idx]); 1315 if (Offset == RegOffsets.end()) { 1316 DEBUG_WITH_TYPE("compact-unwind", 1317 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1318 << MRI.getName(FPRCSRegs[Idx]) 1319 << " not saved\n"); 1320 return CU::UNWIND_ARM_MODE_DWARF; 1321 } else if (Offset->second != CurOffset - 8) { 1322 DEBUG_WITH_TYPE("compact-unwind", 1323 llvm::dbgs() << FloatRegCount << " D-regs saved, but " 1324 << MRI.getName(FPRCSRegs[Idx]) 1325 << " saved at " << Offset->second 1326 << ", expected at " << CurOffset - 8 1327 << "\n"); 1328 return CU::UNWIND_ARM_MODE_DWARF; 1329 } 1330 CurOffset -= 8; 1331 } 1332 1333 return CompactUnwindEncoding | ((FloatRegCount - 1) << 8); 1334} 1335 1336static MCAsmBackend *createARMAsmBackend(const Target &T, 1337 const MCSubtargetInfo &STI, 1338 const MCRegisterInfo &MRI, 1339 const MCTargetOptions &Options, 1340 llvm::endianness Endian) { 1341 const Triple &TheTriple = STI.getTargetTriple(); 1342 switch (TheTriple.getObjectFormat()) { 1343 default: 1344 llvm_unreachable("unsupported object format"); 1345 case Triple::MachO: 1346 return new ARMAsmBackendDarwin(T, STI, MRI); 1347 case Triple::COFF: 1348 assert(TheTriple.isOSWindows() && "non-Windows ARM COFF is not supported"); 1349 return new ARMAsmBackendWinCOFF(T, STI.getTargetTriple().isThumb()); 1350 case Triple::ELF: 1351 assert(TheTriple.isOSBinFormatELF() && "using ELF for non-ELF target"); 1352 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS()); 1353 return new ARMAsmBackendELF(T, STI.getTargetTriple().isThumb(), OSABI, 1354 Endian); 1355 } 1356} 1357 1358MCAsmBackend *llvm::createARMLEAsmBackend(const Target &T, 1359 const MCSubtargetInfo &STI, 1360 const MCRegisterInfo &MRI, 1361 const MCTargetOptions &Options) { 1362 return createARMAsmBackend(T, STI, MRI, Options, llvm::endianness::little); 1363} 1364 1365MCAsmBackend *llvm::createARMBEAsmBackend(const Target &T, 1366 const MCSubtargetInfo &STI, 1367 const MCRegisterInfo &MRI, 1368 const MCTargetOptions &Options) { 1369 return createARMAsmBackend(T, STI, MRI, Options, llvm::endianness::big); 1370} 1371