1//===----------------------- DispatchStage.h --------------------*- C++ -*-===// 2// 3// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4// See https://llvm.org/LICENSE.txt for license information. 5// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6// 7//===----------------------------------------------------------------------===// 8/// \file 9/// 10/// This file models the dispatch component of an instruction pipeline. 11/// 12/// The DispatchStage is responsible for updating instruction dependencies 13/// and communicating to the simulated instruction scheduler that an instruction 14/// is ready to be scheduled for execution. 15/// 16//===----------------------------------------------------------------------===// 17 18#ifndef LLVM_MCA_STAGES_DISPATCHSTAGE_H 19#define LLVM_MCA_STAGES_DISPATCHSTAGE_H 20 21#include "llvm/MC/MCRegisterInfo.h" 22#include "llvm/MC/MCSubtargetInfo.h" 23#include "llvm/MCA/HardwareUnits/RegisterFile.h" 24#include "llvm/MCA/HardwareUnits/RetireControlUnit.h" 25#include "llvm/MCA/Instruction.h" 26#include "llvm/MCA/Stages/Stage.h" 27 28namespace llvm { 29namespace mca { 30 31// Implements the hardware dispatch logic. 32// 33// This class is responsible for the dispatch stage, in which instructions are 34// dispatched in groups to the Scheduler. An instruction can be dispatched if 35// the following conditions are met: 36// 1) There are enough entries in the reorder buffer (see class 37// RetireControlUnit) to write the opcodes associated with the instruction. 38// 2) There are enough physical registers to rename output register operands. 39// 3) There are enough entries available in the used buffered resource(s). 40// 41// The number of micro opcodes that can be dispatched in one cycle is limited by 42// the value of field 'DispatchWidth'. A "dynamic dispatch stall" occurs when 43// processor resources are not available. Dispatch stall events are counted 44// during the entire execution of the code, and displayed by the performance 45// report when flag '-dispatch-stats' is specified. 46// 47// If the number of micro opcodes exceedes DispatchWidth, then the instruction 48// is dispatched in multiple cycles. 49class DispatchStage final : public Stage { 50 unsigned DispatchWidth; 51 unsigned AvailableEntries; 52 unsigned CarryOver; 53 InstRef CarriedOver; 54 const MCSubtargetInfo &STI; 55 RetireControlUnit &RCU; 56 RegisterFile &PRF; 57 58 bool checkRCU(const InstRef &IR) const; 59 bool checkPRF(const InstRef &IR) const; 60 bool canDispatch(const InstRef &IR) const; 61 Error dispatch(InstRef IR); 62 63 void notifyInstructionDispatched(const InstRef &IR, 64 ArrayRef<unsigned> UsedPhysRegs, 65 unsigned uOps) const; 66 67public: 68 DispatchStage(const MCSubtargetInfo &Subtarget, const MCRegisterInfo &MRI, 69 unsigned MaxDispatchWidth, RetireControlUnit &R, 70 RegisterFile &F); 71 72 bool isAvailable(const InstRef &IR) const override; 73 74 // The dispatch logic internally doesn't buffer instructions. So there is 75 // never work to do at the beginning of every cycle. 76 bool hasWorkToComplete() const override { return false; } 77 Error cycleStart() override; 78 Error execute(InstRef &IR) override; 79 80#ifndef NDEBUG 81 void dump() const; 82#endif 83}; 84} // namespace mca 85} // namespace llvm 86 87#endif // LLVM_MCA_STAGES_DISPATCHSTAGE_H 88