1/*
2 * Double-precision vector sinh(x) function.
3 *
4 * Copyright (c) 2022-2023, Arm Limited.
5 * SPDX-License-Identifier: MIT OR Apache-2.0 WITH LLVM-exception
6 */
7
8#include "v_math.h"
9#include "poly_advsimd_f64.h"
10#include "pl_sig.h"
11#include "pl_test.h"
12
13static const struct data
14{
15  float64x2_t poly[11];
16  float64x2_t inv_ln2, m_ln2, shift;
17  uint64x2_t halff;
18  int64x2_t onef;
19#if WANT_SIMD_EXCEPT
20  uint64x2_t tiny_bound, thresh;
21#else
22  uint64x2_t large_bound;
23#endif
24} data = {
25  /* Generated using Remez, deg=12 in [-log(2)/2, log(2)/2].  */
26  .poly = { V2 (0x1p-1), V2 (0x1.5555555555559p-3), V2 (0x1.555555555554bp-5),
27	    V2 (0x1.111111110f663p-7), V2 (0x1.6c16c16c1b5f3p-10),
28	    V2 (0x1.a01a01affa35dp-13), V2 (0x1.a01a018b4ecbbp-16),
29	    V2 (0x1.71ddf82db5bb4p-19), V2 (0x1.27e517fc0d54bp-22),
30	    V2 (0x1.af5eedae67435p-26), V2 (0x1.1f143d060a28ap-29), },
31
32  .inv_ln2 = V2 (0x1.71547652b82fep0),
33  .m_ln2 = (float64x2_t) {-0x1.62e42fefa39efp-1, -0x1.abc9e3b39803fp-56},
34  .shift = V2 (0x1.8p52),
35
36  .halff = V2 (0x3fe0000000000000),
37  .onef = V2 (0x3ff0000000000000),
38#if WANT_SIMD_EXCEPT
39  /* 2^-26, below which sinh(x) rounds to x.  */
40  .tiny_bound = V2 (0x3e50000000000000),
41  /* asuint(large_bound) - asuint(tiny_bound).  */
42  .thresh = V2 (0x0230000000000000),
43#else
44/* 2^9. expm1 helper overflows for large input.  */
45  .large_bound = V2 (0x4080000000000000),
46#endif
47};
48
49static inline float64x2_t
50expm1_inline (float64x2_t x)
51{
52  const struct data *d = ptr_barrier (&data);
53
54  /* Reduce argument:
55     exp(x) - 1 = 2^i * (expm1(f) + 1) - 1
56     where i = round(x / ln2)
57     and   f = x - i * ln2 (f in [-ln2/2, ln2/2]).  */
58  float64x2_t j = vsubq_f64 (vfmaq_f64 (d->shift, d->inv_ln2, x), d->shift);
59  int64x2_t i = vcvtq_s64_f64 (j);
60  float64x2_t f = vfmaq_laneq_f64 (x, j, d->m_ln2, 0);
61  f = vfmaq_laneq_f64 (f, j, d->m_ln2, 1);
62  /* Approximate expm1(f) using polynomial.  */
63  float64x2_t f2 = vmulq_f64 (f, f);
64  float64x2_t f4 = vmulq_f64 (f2, f2);
65  float64x2_t f8 = vmulq_f64 (f4, f4);
66  float64x2_t p = vfmaq_f64 (f, f2, v_estrin_10_f64 (f, f2, f4, f8, d->poly));
67  /* t = 2^i.  */
68  float64x2_t t = vreinterpretq_f64_u64 (
69      vreinterpretq_u64_s64 (vaddq_s64 (vshlq_n_s64 (i, 52), d->onef)));
70  /* expm1(x) ~= p * t + (t - 1).  */
71  return vfmaq_f64 (vsubq_f64 (t, v_f64 (1.0)), p, t);
72}
73
74static float64x2_t NOINLINE VPCS_ATTR
75special_case (float64x2_t x)
76{
77  return v_call_f64 (sinh, x, x, v_u64 (-1));
78}
79
80/* Approximation for vector double-precision sinh(x) using expm1.
81   sinh(x) = (exp(x) - exp(-x)) / 2.
82   The greatest observed error is 2.57 ULP:
83   _ZGVnN2v_sinh (0x1.9fb1d49d1d58bp-2) got 0x1.ab34e59d678dcp-2
84				       want 0x1.ab34e59d678d9p-2.  */
85float64x2_t VPCS_ATTR V_NAME_D1 (sinh) (float64x2_t x)
86{
87  const struct data *d = ptr_barrier (&data);
88
89  float64x2_t ax = vabsq_f64 (x);
90  uint64x2_t sign
91      = veorq_u64 (vreinterpretq_u64_f64 (x), vreinterpretq_u64_f64 (ax));
92  float64x2_t halfsign = vreinterpretq_f64_u64 (vorrq_u64 (sign, d->halff));
93
94#if WANT_SIMD_EXCEPT
95  uint64x2_t special = vcgeq_u64 (
96      vsubq_u64 (vreinterpretq_u64_f64 (ax), d->tiny_bound), d->thresh);
97#else
98  uint64x2_t special = vcgeq_u64 (vreinterpretq_u64_f64 (ax), d->large_bound);
99#endif
100
101  /* Fall back to scalar variant for all lanes if any of them are special.  */
102  if (unlikely (v_any_u64 (special)))
103    return special_case (x);
104
105  /* Up to the point that expm1 overflows, we can use it to calculate sinh
106     using a slight rearrangement of the definition of sinh. This allows us to
107     retain acceptable accuracy for very small inputs.  */
108  float64x2_t t = expm1_inline (ax);
109  t = vaddq_f64 (t, vdivq_f64 (t, vaddq_f64 (t, v_f64 (1.0))));
110  return vmulq_f64 (t, halfsign);
111}
112
113PL_SIG (V, D, 1, sinh, -10.0, 10.0)
114PL_TEST_ULP (V_NAME_D1 (sinh), 2.08)
115PL_TEST_EXPECT_FENV (V_NAME_D1 (sinh), WANT_SIMD_EXCEPT)
116PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0, 0x1p-26, 1000)
117PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0x1p-26, 0x1p9, 500000)
118PL_TEST_SYM_INTERVAL (V_NAME_D1 (sinh), 0x1p9, inf, 1000)
119