1/*
2 * This file is _NOT_ automatically generated.  It must agree with the
3 * Virtual Function register map definitions in t4vf_defs.h in the common
4 * code.
5 */
6__FBSDID("$FreeBSD$");
7
8struct reg_info t4vf_sge_regs[] = {
9	{ "SGE_KDOORBELL",			0x000, 0 },
10		{ "QID", 15, 17 },
11		{ "Priority", 14, 1 },
12		{ "PIDX", 0, 14 },
13	{ "SGE_GTS",				0x004, 0 },
14		{ "IngressQID", 16, 16 },
15		{ "TimerReg", 13, 3 },
16		{ "SEIntArm", 12, 1 },
17		{ "CIDXInc", 0, 12 },
18
19	{ NULL, 0, 0 }
20};
21
22struct reg_info t4vf_mps_regs[] = {
23	{ "MPS_VF_CTL",	0x100, 0 },
24		{ "TxEn", 1, 1 },
25		{ "RxEn", 0, 1 },
26
27	{ "MPS_VF_STAT_TX_VF_BCAST_BYTES_L",	0x180, 0 },
28	{ "MPS_VF_STAT_TX_VF_BCAST_BYTES_H",	0x184, 0 },
29	{ "MPS_VF_STAT_TX_VF_BCAST_FRAMES_L",	0x188, 0 },
30	{ "MPS_VF_STAT_TX_VF_BCAST_FRAMES_H",	0x18c, 0 },
31
32	{ "MPS_VF_STAT_TX_VF_MCAST_BYTES_L",	0x190, 0 },
33	{ "MPS_VF_STAT_TX_VF_MCAST_BYTES_H",	0x194, 0 },
34	{ "MPS_VF_STAT_TX_VF_MCAST_FRAMES_L",	0x198, 0 },
35	{ "MPS_VF_STAT_TX_VF_MCAST_FRAMES_H",	0x19c, 0 },
36
37	{ "MPS_VF_STAT_TX_VF_UCAST_BYTES_L",	0x1a0, 0 },
38	{ "MPS_VF_STAT_TX_VF_UCAST_BYTES_H",	0x1a4, 0 },
39	{ "MPS_VF_STAT_TX_VF_UCAST_FRAMES_L",	0x1a8, 0 },
40	{ "MPS_VF_STAT_TX_VF_UCAST_FRAMES_H",	0x1ac, 0 },
41
42	{ "MPS_VF_STAT_TX_VF_DROP_FRAMES_L",	0x1b0, 0 },
43	{ "MPS_VF_STAT_TX_VF_DROP_FRAMES_H",	0x1b4, 0 },
44
45	{ "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_L",  0x1b8, 0 },
46	{ "MPS_VF_STAT_TX_VF_OFFLOAD_BYTES_H",  0x1bc, 0 },
47	{ "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_L",	0x1c0, 0 },
48	{ "MPS_VF_STAT_TX_VF_OFFLOAD_FRAMES_H",	0x1c4, 0 },
49
50	{ "MPS_VF_STAT_RX_VF_BCAST_BYTES_L",	0x1c8, 0 },
51	{ "MPS_VF_STAT_RX_VF_BCAST_BYTES_H",	0x1cc, 0 },
52	{ "MPS_VF_STAT_RX_VF_BCAST_FRAMES_L",	0x1d0, 0 },
53	{ "MPS_VF_STAT_RX_VF_BCAST_FRAMES_H",	0x1d4, 0 },
54
55	{ "MPS_VF_STAT_RX_VF_MCAST_BYTES_L",	0x1d8, 0 },
56	{ "MPS_VF_STAT_RX_VF_MCAST_BYTES_H",	0x1dc, 0 },
57	{ "MPS_VF_STAT_RX_VF_MCAST_FRAMES_L",	0x1e0, 0 },
58	{ "MPS_VF_STAT_RX_VF_MCAST_FRAMES_H",	0x1e4, 0 },
59
60	{ "MPS_VF_STAT_RX_VF_UCAST_BYTES_L",	0x1e8, 0 },
61	{ "MPS_VF_STAT_RX_VF_UCAST_BYTES_H",	0x1ec, 0 },
62	{ "MPS_VF_STAT_RX_VF_UCAST_FRAMES_L",	0x1f0, 0 },
63	{ "MPS_VF_STAT_RX_VF_UCAST_FRAMES_H",	0x1f4, 0 },
64
65	{ "MPS_VF_STAT_RX_VF_ERR_FRAMES_L",	0x1f8, 0 },
66	{ "MPS_VF_STAT_RX_VF_ERR_FRAMES_H",	0x1fc, 0 },
67
68	{ NULL, 0, 0 }
69};
70
71struct reg_info t4vf_pl_regs[] = {
72	{ "PL_VF_WHOAMI",			0x200, 0 },
73		{ "PortxMap", 5, 3 },
74		{ "SourceBus", 3, 2 },
75		{ "SourcePF", 0, 3 },
76
77	{ NULL, 0, 0 }
78};
79
80struct reg_info t4vf_cim_regs[] = {
81	/*
82	 * Note: the Mailbox Control register has read side-effects so
83	 * the driver simply returns 0xffff for this register.
84	 */
85	{ "CIM_VF_EXT_MAILBOX_CTRL",		0x300, 0 },
86		{ "MBGeneric", 4, 4 },
87		{ "MBMsgValid", 3, 1 },
88		{ "MBIntReq", 3, 1 },
89		{ "MBOwner", 0, 2 },
90	{ "CIM_VF_EXT_MAILBOX_STATUS",		0x304, 0 },
91		{ "MBVFReady", 0, 1 },
92
93	{ NULL, 0, 0 }
94};
95
96struct reg_info t4vf_mbdata_regs[] = {
97	{ "CIM_VF_EXT_MAILBOX_DATA_00",		0x240, 0 },
98		{ "Return", 8, 8 },
99		{ "Length16", 0, 8 },
100	{ "CIM_VF_EXT_MAILBOX_DATA_04",		0x244, 0 },
101		{ "OpCode", 24, 8 },
102		{ "Request", 23, 1 },
103		{ "Read", 22, 1 },
104		{ "Write", 21, 1 },
105		{ "Execute", 20, 1 },
106	{ "CIM_VF_EXT_MAILBOX_DATA_08",		0x248, 0 },
107	{ "CIM_VF_EXT_MAILBOX_DATA_0c",		0x24c, 0 },
108	{ "CIM_VF_EXT_MAILBOX_DATA_10",		0x250, 0 },
109	{ "CIM_VF_EXT_MAILBOX_DATA_14",		0x254, 0 },
110	{ "CIM_VF_EXT_MAILBOX_DATA_18",		0x258, 0 },
111	{ "CIM_VF_EXT_MAILBOX_DATA_1c",		0x25c, 0 },
112	{ "CIM_VF_EXT_MAILBOX_DATA_20",		0x260, 0 },
113	{ "CIM_VF_EXT_MAILBOX_DATA_24",		0x264, 0 },
114	{ "CIM_VF_EXT_MAILBOX_DATA_28",		0x268, 0 },
115	{ "CIM_VF_EXT_MAILBOX_DATA_2c",		0x26c, 0 },
116	{ "CIM_VF_EXT_MAILBOX_DATA_30",		0x270, 0 },
117	{ "CIM_VF_EXT_MAILBOX_DATA_34",		0x274, 0 },
118	{ "CIM_VF_EXT_MAILBOX_DATA_38",		0x278, 0 },
119	{ "CIM_VF_EXT_MAILBOX_DATA_3c",		0x27c, 0 },
120
121	{ NULL, 0, 0 }
122};
123