local_apic.c revision 210298
1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * Copyright (c) 1996, by Steve Passe 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. The name of the developer may NOT be used to endorse or promote products 12 * derived from this software without specific prior written permission. 13 * 3. Neither the name of the author nor the names of any co-contributors 14 * may be used to endorse or promote products derived from this software 15 * without specific prior written permission. 16 * 17 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27 * SUCH DAMAGE. 28 */ 29 30/* 31 * Local APIC support on Pentium and later processors. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/x86/x86/local_apic.c 210298 2010-07-20 15:48:29Z mav $"); 36 37#include "opt_hwpmc_hooks.h" 38#include "opt_kdtrace.h" 39 40#include "opt_ddb.h" 41 42#include <sys/param.h> 43#include <sys/systm.h> 44#include <sys/bus.h> 45#include <sys/kernel.h> 46#include <sys/lock.h> 47#include <sys/mutex.h> 48#include <sys/pcpu.h> 49#include <sys/proc.h> 50#include <sys/sched.h> 51#include <sys/smp.h> 52#include <sys/timeet.h> 53 54#include <vm/vm.h> 55#include <vm/pmap.h> 56 57#include <machine/apicreg.h> 58#include <machine/cpu.h> 59#include <machine/cputypes.h> 60#include <machine/frame.h> 61#include <machine/intr_machdep.h> 62#include <machine/apicvar.h> 63#include <machine/mca.h> 64#include <machine/md_var.h> 65#include <machine/smp.h> 66#include <machine/specialreg.h> 67 68#ifdef DDB 69#include <sys/interrupt.h> 70#include <ddb/ddb.h> 71#endif 72 73#ifdef __amd64__ 74#define SDT_APIC SDT_SYSIGT 75#define SDT_APICT SDT_SYSIGT 76#define GSEL_APIC 0 77#else 78#define SDT_APIC SDT_SYS386IGT 79#define SDT_APICT SDT_SYS386TGT 80#define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL) 81#endif 82 83/* Sanity checks on IDT vectors. */ 84CTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 85CTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 86CTASSERT(APIC_LOCAL_INTS == 240); 87CTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 88 89/* Magic IRQ values for the timer and syscalls. */ 90#define IRQ_TIMER (NUM_IO_INTS + 1) 91#define IRQ_SYSCALL (NUM_IO_INTS + 2) 92 93/* 94 * Support for local APICs. Local APICs manage interrupts on each 95 * individual processor as opposed to I/O APICs which receive interrupts 96 * from I/O devices and then forward them on to the local APICs. 97 * 98 * Local APICs can also send interrupts to each other thus providing the 99 * mechanism for IPIs. 100 */ 101 102struct lvt { 103 u_int lvt_edgetrigger:1; 104 u_int lvt_activehi:1; 105 u_int lvt_masked:1; 106 u_int lvt_active:1; 107 u_int lvt_mode:16; 108 u_int lvt_vector:8; 109}; 110 111struct lapic { 112 struct lvt la_lvts[LVT_MAX + 1]; 113 u_int la_id:8; 114 u_int la_cluster:4; 115 u_int la_cluster_id:2; 116 u_int la_present:1; 117 u_long *la_timer_count; 118 u_long la_timer_period; 119 u_int la_timer_mode; 120 /* Include IDT_SYSCALL to make indexing easier. */ 121 int la_ioint_irqs[APIC_NUM_IOINTS + 1]; 122} static lapics[MAX_APIC_ID + 1]; 123 124/* Global defaults for local APIC LVT entries. */ 125static struct lvt lvts[LVT_MAX + 1] = { 126 { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 127 { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 128 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 129 { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 130 { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 131 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 132 { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */ 133}; 134 135static inthand_t *ioint_handlers[] = { 136 NULL, /* 0 - 31 */ 137 IDTVEC(apic_isr1), /* 32 - 63 */ 138 IDTVEC(apic_isr2), /* 64 - 95 */ 139 IDTVEC(apic_isr3), /* 96 - 127 */ 140 IDTVEC(apic_isr4), /* 128 - 159 */ 141 IDTVEC(apic_isr5), /* 160 - 191 */ 142 IDTVEC(apic_isr6), /* 192 - 223 */ 143 IDTVEC(apic_isr7), /* 224 - 255 */ 144}; 145 146 147static u_int32_t lapic_timer_divisors[] = { 148 APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 149 APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 150}; 151 152extern inthand_t IDTVEC(rsvd); 153 154volatile lapic_t *lapic; 155vm_paddr_t lapic_paddr; 156static u_long lapic_timer_divisor; 157static struct eventtimer lapic_et; 158 159static void lapic_enable(void); 160static void lapic_resume(struct pic *pic); 161static void lapic_timer_enable_intr(void); 162static void lapic_timer_oneshot(u_int count); 163static void lapic_timer_periodic(u_int count); 164static void lapic_timer_stop(void); 165static void lapic_timer_set_divisor(u_int divisor); 166static uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 167static int lapic_et_start(struct eventtimer *et, 168 struct bintime *first, struct bintime *period); 169static int lapic_et_stop(struct eventtimer *et); 170 171struct pic lapic_pic = { .pic_resume = lapic_resume }; 172 173static uint32_t 174lvt_mode(struct lapic *la, u_int pin, uint32_t value) 175{ 176 struct lvt *lvt; 177 178 KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 179 if (la->la_lvts[pin].lvt_active) 180 lvt = &la->la_lvts[pin]; 181 else 182 lvt = &lvts[pin]; 183 184 value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 185 APIC_LVT_VECTOR); 186 if (lvt->lvt_edgetrigger == 0) 187 value |= APIC_LVT_TM; 188 if (lvt->lvt_activehi == 0) 189 value |= APIC_LVT_IIPP_INTALO; 190 if (lvt->lvt_masked) 191 value |= APIC_LVT_M; 192 value |= lvt->lvt_mode; 193 switch (lvt->lvt_mode) { 194 case APIC_LVT_DM_NMI: 195 case APIC_LVT_DM_SMI: 196 case APIC_LVT_DM_INIT: 197 case APIC_LVT_DM_EXTINT: 198 if (!lvt->lvt_edgetrigger) { 199 printf("lapic%u: Forcing LINT%u to edge trigger\n", 200 la->la_id, pin); 201 value |= APIC_LVT_TM; 202 } 203 /* Use a vector of 0. */ 204 break; 205 case APIC_LVT_DM_FIXED: 206 value |= lvt->lvt_vector; 207 break; 208 default: 209 panic("bad APIC LVT delivery mode: %#x\n", value); 210 } 211 return (value); 212} 213 214/* 215 * Map the local APIC and setup necessary interrupt vectors. 216 */ 217void 218lapic_init(vm_paddr_t addr) 219{ 220 u_int regs[4]; 221 int i, arat; 222 223 /* Map the local APIC and setup the spurious interrupt handler. */ 224 KASSERT(trunc_page(addr) == addr, 225 ("local APIC not aligned on a page boundary")); 226 lapic = pmap_mapdev(addr, sizeof(lapic_t)); 227 lapic_paddr = addr; 228 setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL, 229 GSEL_APIC); 230 231 /* Perform basic initialization of the BSP's local APIC. */ 232 lapic_enable(); 233 234 /* Set BSP's per-CPU local APIC ID. */ 235 PCPU_SET(apic_id, lapic_id()); 236 237 /* Local APIC timer interrupt. */ 238 setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC); 239 240 /* Local APIC error interrupt. */ 241 setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC); 242 243 /* XXX: Thermal interrupt */ 244 245 /* Local APIC CMCI. */ 246 setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL, GSEL_APIC); 247 248 if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) { 249 arat = 0; 250 /* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */ 251 if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) { 252 do_cpuid(0x06, regs); 253 if (regs[0] & 0x4) 254 arat = 1; 255 } 256 bzero(&lapic_et, sizeof(lapic_et)); 257 lapic_et.et_name = "LAPIC"; 258 lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | 259 ET_FLAGS_PERCPU; 260 lapic_et.et_quality = 600; 261 if (!arat) { 262 lapic_et.et_flags |= ET_FLAGS_C3STOP; 263 lapic_et.et_quality -= 100; 264 } 265 lapic_et.et_frequency = 0; 266 /* We don't know frequency yet, so trying to guess. */ 267 lapic_et.et_min_period.sec = 0; 268 lapic_et.et_min_period.frac = 0x00001000LL << 32; 269 lapic_et.et_max_period.sec = 1; 270 lapic_et.et_max_period.frac = 0; 271 lapic_et.et_start = lapic_et_start; 272 lapic_et.et_stop = lapic_et_stop; 273 lapic_et.et_priv = NULL; 274 et_register(&lapic_et); 275 } 276} 277 278/* 279 * Create a local APIC instance. 280 */ 281void 282lapic_create(u_int apic_id, int boot_cpu) 283{ 284 int i; 285 286 if (apic_id > MAX_APIC_ID) { 287 printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 288 if (boot_cpu) 289 panic("Can't ignore BSP"); 290 return; 291 } 292 KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 293 apic_id)); 294 295 /* 296 * Assume no local LVT overrides and a cluster of 0 and 297 * intra-cluster ID of 0. 298 */ 299 lapics[apic_id].la_present = 1; 300 lapics[apic_id].la_id = apic_id; 301 for (i = 0; i <= LVT_MAX; i++) { 302 lapics[apic_id].la_lvts[i] = lvts[i]; 303 lapics[apic_id].la_lvts[i].lvt_active = 0; 304 } 305 for (i = 0; i <= APIC_NUM_IOINTS; i++) 306 lapics[apic_id].la_ioint_irqs[i] = -1; 307 lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 308 lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = 309 IRQ_TIMER; 310 311#ifdef SMP 312 cpu_add(apic_id, boot_cpu); 313#endif 314} 315 316/* 317 * Dump contents of local APIC registers 318 */ 319void 320lapic_dump(const char* str) 321{ 322 323 printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 324 printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 325 lapic->id, lapic->version, lapic->ldr, lapic->dfr); 326 printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 327 lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 328 printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pmc: 0x%08x\n", 329 lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 330 lapic->lvt_pcint); 331 printf(" cmci: 0x%08x\n", lapic->lvt_cmci); 332} 333 334void 335lapic_setup(int boot) 336{ 337 struct lapic *la; 338 u_int32_t maxlvt; 339 register_t eflags; 340 char buf[MAXCOMLEN + 1]; 341 342 la = &lapics[lapic_id()]; 343 KASSERT(la->la_present, ("missing APIC structure")); 344 eflags = intr_disable(); 345 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 346 347 /* Initialize the TPR to allow all interrupts. */ 348 lapic_set_tpr(0); 349 350 /* Setup spurious vector and enable the local APIC. */ 351 lapic_enable(); 352 353 /* Program LINT[01] LVT entries. */ 354 lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 355 lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 356 357 /* Program the PMC LVT entry if present. */ 358 if (maxlvt >= LVT_PMC) 359 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 360 361 /* Program timer LVT and setup handler. */ 362 lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 363 if (boot) { 364 snprintf(buf, sizeof(buf), "cpu%d:timer", PCPU_GET(cpuid)); 365 intrcnt_add(buf, &la->la_timer_count); 366 } 367 368 /* Setup the timer if configured. */ 369 if (la->la_timer_mode != 0) { 370 KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor", 371 lapic_id())); 372 lapic_timer_set_divisor(lapic_timer_divisor); 373 if (la->la_timer_mode == 1) 374 lapic_timer_periodic(la->la_timer_period); 375 else 376 lapic_timer_oneshot(la->la_timer_period); 377 lapic_timer_enable_intr(); 378 } 379 380 /* Program error LVT and clear any existing errors. */ 381 lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error); 382 lapic->esr = 0; 383 384 /* XXX: Thermal LVT */ 385 386 /* Program the CMCI LVT entry if present. */ 387 if (maxlvt >= LVT_CMCI) 388 lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci); 389 390 intr_restore(eflags); 391} 392 393void 394lapic_reenable_pmc(void) 395{ 396#ifdef HWPMC_HOOKS 397 uint32_t value; 398 399 value = lapic->lvt_pcint; 400 value &= ~APIC_LVT_M; 401 lapic->lvt_pcint = value; 402#endif 403} 404 405#ifdef HWPMC_HOOKS 406static void 407lapic_update_pmc(void *dummy) 408{ 409 struct lapic *la; 410 411 la = &lapics[lapic_id()]; 412 lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 413} 414#endif 415 416int 417lapic_enable_pmc(void) 418{ 419#ifdef HWPMC_HOOKS 420 u_int32_t maxlvt; 421 422 /* Fail if the local APIC is not present. */ 423 if (lapic == NULL) 424 return (0); 425 426 /* Fail if the PMC LVT is not present. */ 427 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 428 if (maxlvt < LVT_PMC) 429 return (0); 430 431 lvts[LVT_PMC].lvt_masked = 0; 432 433#ifdef SMP 434 /* 435 * If hwpmc was loaded at boot time then the APs may not be 436 * started yet. In that case, don't forward the request to 437 * them as they will program the lvt when they start. 438 */ 439 if (smp_started) 440 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 441 else 442#endif 443 lapic_update_pmc(NULL); 444 return (1); 445#else 446 return (0); 447#endif 448} 449 450void 451lapic_disable_pmc(void) 452{ 453#ifdef HWPMC_HOOKS 454 u_int32_t maxlvt; 455 456 /* Fail if the local APIC is not present. */ 457 if (lapic == NULL) 458 return; 459 460 /* Fail if the PMC LVT is not present. */ 461 maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 462 if (maxlvt < LVT_PMC) 463 return; 464 465 lvts[LVT_PMC].lvt_masked = 1; 466 467#ifdef SMP 468 /* The APs should always be started when hwpmc is unloaded. */ 469 KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early")); 470#endif 471 smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 472#endif 473} 474 475static int 476lapic_et_start(struct eventtimer *et, 477 struct bintime *first, struct bintime *period) 478{ 479 struct lapic *la; 480 u_long value; 481 482 if (et->et_frequency == 0) { 483 /* Start off with a divisor of 2 (power on reset default). */ 484 lapic_timer_divisor = 2; 485 /* Try to calibrate the local APIC timer. */ 486 do { 487 lapic_timer_set_divisor(lapic_timer_divisor); 488 lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 489 DELAY(1000000); 490 value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 491 if (value != APIC_TIMER_MAX_COUNT) 492 break; 493 lapic_timer_divisor <<= 1; 494 } while (lapic_timer_divisor <= 128); 495 if (lapic_timer_divisor > 128) 496 panic("lapic: Divisor too big"); 497 if (bootverbose) 498 printf("lapic: Divisor %lu, Frequency %lu Hz\n", 499 lapic_timer_divisor, value); 500 et->et_frequency = value; 501 et->et_min_period.sec = 0; 502 et->et_min_period.frac = 503 ((0x00000002LLU << 32) / et->et_frequency) << 32; 504 et->et_max_period.sec = 0xfffffffeLLU / et->et_frequency; 505 et->et_max_period.frac = 506 ((0xfffffffeLLU << 32) / et->et_frequency) << 32; 507 } 508 la = &lapics[lapic_id()]; 509 /* 510 * Start up the timer on the BSP. The APs will kick off their 511 * timer during lapic_setup(). 512 */ 513 lapic_timer_set_divisor(lapic_timer_divisor); 514 if (period != NULL) { 515 la->la_timer_mode = 1; 516 la->la_timer_period = 517 (et->et_frequency * (period->frac >> 32)) >> 32; 518 if (period->sec != 0) 519 la->la_timer_period += et->et_frequency * period->sec; 520 lapic_timer_periodic(la->la_timer_period); 521 } else { 522 la->la_timer_mode = 2; 523 la->la_timer_period = 524 (et->et_frequency * (first->frac >> 32)) >> 32; 525 if (first->sec != 0) 526 la->la_timer_period += et->et_frequency * first->sec; 527 lapic_timer_oneshot(la->la_timer_period); 528 } 529 lapic_timer_enable_intr(); 530 return (0); 531} 532 533static int 534lapic_et_stop(struct eventtimer *et) 535{ 536 struct lapic *la = &lapics[lapic_id()]; 537 538 la->la_timer_mode = 0; 539 lapic_timer_stop(); 540 return (0); 541} 542 543void 544lapic_disable(void) 545{ 546 uint32_t value; 547 548 /* Software disable the local APIC. */ 549 value = lapic->svr; 550 value &= ~APIC_SVR_SWEN; 551 lapic->svr = value; 552} 553 554static void 555lapic_enable(void) 556{ 557 u_int32_t value; 558 559 /* Program the spurious vector to enable the local APIC. */ 560 value = lapic->svr; 561 value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 562 value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 563 lapic->svr = value; 564} 565 566/* Reset the local APIC on the BSP during resume. */ 567static void 568lapic_resume(struct pic *pic) 569{ 570 571 lapic_setup(0); 572} 573 574int 575lapic_id(void) 576{ 577 578 KASSERT(lapic != NULL, ("local APIC is not mapped")); 579 return (lapic->id >> APIC_ID_SHIFT); 580} 581 582int 583lapic_intr_pending(u_int vector) 584{ 585 volatile u_int32_t *irr; 586 587 /* 588 * The IRR registers are an array of 128-bit registers each of 589 * which only describes 32 interrupts in the low 32 bits.. Thus, 590 * we divide the vector by 32 to get the 128-bit index. We then 591 * multiply that index by 4 to get the equivalent index from 592 * treating the IRR as an array of 32-bit registers. Finally, we 593 * modulus the vector by 32 to determine the individual bit to 594 * test. 595 */ 596 irr = &lapic->irr0; 597 return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 598} 599 600void 601lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 602{ 603 struct lapic *la; 604 605 KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 606 __func__, apic_id)); 607 KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 608 __func__, cluster)); 609 KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 610 ("%s: intra cluster id %u too big", __func__, cluster_id)); 611 la = &lapics[apic_id]; 612 la->la_cluster = cluster; 613 la->la_cluster_id = cluster_id; 614} 615 616int 617lapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 618{ 619 620 if (pin > LVT_MAX) 621 return (EINVAL); 622 if (apic_id == APIC_ID_ALL) { 623 lvts[pin].lvt_masked = masked; 624 if (bootverbose) 625 printf("lapic:"); 626 } else { 627 KASSERT(lapics[apic_id].la_present, 628 ("%s: missing APIC %u", __func__, apic_id)); 629 lapics[apic_id].la_lvts[pin].lvt_masked = masked; 630 lapics[apic_id].la_lvts[pin].lvt_active = 1; 631 if (bootverbose) 632 printf("lapic%u:", apic_id); 633 } 634 if (bootverbose) 635 printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 636 return (0); 637} 638 639int 640lapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 641{ 642 struct lvt *lvt; 643 644 if (pin > LVT_MAX) 645 return (EINVAL); 646 if (apic_id == APIC_ID_ALL) { 647 lvt = &lvts[pin]; 648 if (bootverbose) 649 printf("lapic:"); 650 } else { 651 KASSERT(lapics[apic_id].la_present, 652 ("%s: missing APIC %u", __func__, apic_id)); 653 lvt = &lapics[apic_id].la_lvts[pin]; 654 lvt->lvt_active = 1; 655 if (bootverbose) 656 printf("lapic%u:", apic_id); 657 } 658 lvt->lvt_mode = mode; 659 switch (mode) { 660 case APIC_LVT_DM_NMI: 661 case APIC_LVT_DM_SMI: 662 case APIC_LVT_DM_INIT: 663 case APIC_LVT_DM_EXTINT: 664 lvt->lvt_edgetrigger = 1; 665 lvt->lvt_activehi = 1; 666 if (mode == APIC_LVT_DM_EXTINT) 667 lvt->lvt_masked = 1; 668 else 669 lvt->lvt_masked = 0; 670 break; 671 default: 672 panic("Unsupported delivery mode: 0x%x\n", mode); 673 } 674 if (bootverbose) { 675 printf(" Routing "); 676 switch (mode) { 677 case APIC_LVT_DM_NMI: 678 printf("NMI"); 679 break; 680 case APIC_LVT_DM_SMI: 681 printf("SMI"); 682 break; 683 case APIC_LVT_DM_INIT: 684 printf("INIT"); 685 break; 686 case APIC_LVT_DM_EXTINT: 687 printf("ExtINT"); 688 break; 689 } 690 printf(" -> LINT%u\n", pin); 691 } 692 return (0); 693} 694 695int 696lapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 697{ 698 699 if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 700 return (EINVAL); 701 if (apic_id == APIC_ID_ALL) { 702 lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 703 if (bootverbose) 704 printf("lapic:"); 705 } else { 706 KASSERT(lapics[apic_id].la_present, 707 ("%s: missing APIC %u", __func__, apic_id)); 708 lapics[apic_id].la_lvts[pin].lvt_active = 1; 709 lapics[apic_id].la_lvts[pin].lvt_activehi = 710 (pol == INTR_POLARITY_HIGH); 711 if (bootverbose) 712 printf("lapic%u:", apic_id); 713 } 714 if (bootverbose) 715 printf(" LINT%u polarity: %s\n", pin, 716 pol == INTR_POLARITY_HIGH ? "high" : "low"); 717 return (0); 718} 719 720int 721lapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 722{ 723 724 if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 725 return (EINVAL); 726 if (apic_id == APIC_ID_ALL) { 727 lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 728 if (bootverbose) 729 printf("lapic:"); 730 } else { 731 KASSERT(lapics[apic_id].la_present, 732 ("%s: missing APIC %u", __func__, apic_id)); 733 lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 734 (trigger == INTR_TRIGGER_EDGE); 735 lapics[apic_id].la_lvts[pin].lvt_active = 1; 736 if (bootverbose) 737 printf("lapic%u:", apic_id); 738 } 739 if (bootverbose) 740 printf(" LINT%u trigger: %s\n", pin, 741 trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 742 return (0); 743} 744 745/* 746 * Adjust the TPR of the current CPU so that it blocks all interrupts below 747 * the passed in vector. 748 */ 749void 750lapic_set_tpr(u_int vector) 751{ 752#ifdef CHEAP_TPR 753 lapic->tpr = vector; 754#else 755 u_int32_t tpr; 756 757 tpr = lapic->tpr & ~APIC_TPR_PRIO; 758 tpr |= vector; 759 lapic->tpr = tpr; 760#endif 761} 762 763void 764lapic_eoi(void) 765{ 766 767 lapic->eoi = 0; 768} 769 770void 771lapic_handle_intr(int vector, struct trapframe *frame) 772{ 773 struct intsrc *isrc; 774 775 if (vector == -1) 776 panic("Couldn't get vector from ISR!"); 777 isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id), 778 vector)); 779 intr_execute_handlers(isrc, frame); 780} 781 782void 783lapic_handle_timer(struct trapframe *frame) 784{ 785 struct lapic *la; 786 struct trapframe *oldframe; 787 struct thread *td; 788 789 /* Send EOI first thing. */ 790 lapic_eoi(); 791 792#if defined(SMP) && !defined(SCHED_ULE) 793 /* 794 * Don't do any accounting for the disabled HTT cores, since it 795 * will provide misleading numbers for the userland. 796 * 797 * No locking is necessary here, since even if we loose the race 798 * when hlt_cpus_mask changes it is not a big deal, really. 799 * 800 * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 801 * and unlike other schedulers it actually schedules threads to 802 * those CPUs. 803 */ 804 if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 805 return; 806#endif 807 808 /* Look up our local APIC structure for the tick counters. */ 809 la = &lapics[PCPU_GET(apic_id)]; 810 (*la->la_timer_count)++; 811 critical_enter(); 812 if (lapic_et.et_active) { 813 td = curthread; 814 oldframe = td->td_intr_frame; 815 td->td_intr_frame = frame; 816 lapic_et.et_event_cb(&lapic_et, lapic_et.et_arg); 817 td->td_intr_frame = oldframe; 818 } 819 critical_exit(); 820} 821 822static void 823lapic_timer_set_divisor(u_int divisor) 824{ 825 826 KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 827 KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 828 sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 829 lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 830} 831 832static void 833lapic_timer_oneshot(u_int count) 834{ 835 u_int32_t value; 836 837 value = lapic->lvt_timer; 838 value &= ~APIC_LVTT_TM; 839 value |= APIC_LVTT_TM_ONE_SHOT; 840 lapic->lvt_timer = value; 841 lapic->icr_timer = count; 842} 843 844static void 845lapic_timer_periodic(u_int count) 846{ 847 u_int32_t value; 848 849 value = lapic->lvt_timer; 850 value &= ~APIC_LVTT_TM; 851 value |= APIC_LVTT_TM_PERIODIC; 852 lapic->lvt_timer = value; 853 lapic->icr_timer = count; 854} 855 856static void 857lapic_timer_stop(void) 858{ 859 u_int32_t value; 860 861 value = lapic->lvt_timer; 862 value &= ~APIC_LVTT_TM; 863 value &= ~APIC_LVT_M; 864 lapic->lvt_timer = value; 865} 866 867static void 868lapic_timer_enable_intr(void) 869{ 870 u_int32_t value; 871 872 value = lapic->lvt_timer; 873 value &= ~APIC_LVT_M; 874 lapic->lvt_timer = value; 875} 876 877void 878lapic_handle_cmc(void) 879{ 880 881 lapic_eoi(); 882 cmc_intr(); 883} 884 885/* 886 * Called from the mca_init() to activate the CMC interrupt if this CPU is 887 * responsible for monitoring any MC banks for CMC events. Since mca_init() 888 * is called prior to lapic_setup() during boot, this just needs to unmask 889 * this CPU's LVT_CMCI entry. 890 */ 891void 892lapic_enable_cmc(void) 893{ 894 u_int apic_id; 895 896 apic_id = PCPU_GET(apic_id); 897 KASSERT(lapics[apic_id].la_present, 898 ("%s: missing APIC %u", __func__, apic_id)); 899 lapics[apic_id].la_lvts[LVT_CMCI].lvt_masked = 0; 900 lapics[apic_id].la_lvts[LVT_CMCI].lvt_active = 1; 901 if (bootverbose) 902 printf("lapic%u: CMCI unmasked\n", apic_id); 903} 904 905void 906lapic_handle_error(void) 907{ 908 u_int32_t esr; 909 910 /* 911 * Read the contents of the error status register. Write to 912 * the register first before reading from it to force the APIC 913 * to update its value to indicate any errors that have 914 * occurred since the previous write to the register. 915 */ 916 lapic->esr = 0; 917 esr = lapic->esr; 918 919 printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr); 920 lapic_eoi(); 921} 922 923u_int 924apic_cpuid(u_int apic_id) 925{ 926#ifdef SMP 927 return apic_cpuids[apic_id]; 928#else 929 return 0; 930#endif 931} 932 933/* Request a free IDT vector to be used by the specified IRQ. */ 934u_int 935apic_alloc_vector(u_int apic_id, u_int irq) 936{ 937 u_int vector; 938 939 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 940 941 /* 942 * Search for a free vector. Currently we just use a very simple 943 * algorithm to find the first free vector. 944 */ 945 mtx_lock_spin(&icu_lock); 946 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 947 if (lapics[apic_id].la_ioint_irqs[vector] != -1) 948 continue; 949 lapics[apic_id].la_ioint_irqs[vector] = irq; 950 mtx_unlock_spin(&icu_lock); 951 return (vector + APIC_IO_INTS); 952 } 953 mtx_unlock_spin(&icu_lock); 954 return (0); 955} 956 957/* 958 * Request 'count' free contiguous IDT vectors to be used by 'count' 959 * IRQs. 'count' must be a power of two and the vectors will be 960 * aligned on a boundary of 'align'. If the request cannot be 961 * satisfied, 0 is returned. 962 */ 963u_int 964apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 965{ 966 u_int first, run, vector; 967 968 KASSERT(powerof2(count), ("bad count")); 969 KASSERT(powerof2(align), ("bad align")); 970 KASSERT(align >= count, ("align < count")); 971#ifdef INVARIANTS 972 for (run = 0; run < count; run++) 973 KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 974 irqs[run], run)); 975#endif 976 977 /* 978 * Search for 'count' free vectors. As with apic_alloc_vector(), 979 * this just uses a simple first fit algorithm. 980 */ 981 run = 0; 982 first = 0; 983 mtx_lock_spin(&icu_lock); 984 for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 985 986 /* Vector is in use, end run. */ 987 if (lapics[apic_id].la_ioint_irqs[vector] != -1) { 988 run = 0; 989 first = 0; 990 continue; 991 } 992 993 /* Start a new run if run == 0 and vector is aligned. */ 994 if (run == 0) { 995 if ((vector & (align - 1)) != 0) 996 continue; 997 first = vector; 998 } 999 run++; 1000 1001 /* Keep looping if the run isn't long enough yet. */ 1002 if (run < count) 1003 continue; 1004 1005 /* Found a run, assign IRQs and return the first vector. */ 1006 for (vector = 0; vector < count; vector++) 1007 lapics[apic_id].la_ioint_irqs[first + vector] = 1008 irqs[vector]; 1009 mtx_unlock_spin(&icu_lock); 1010 return (first + APIC_IO_INTS); 1011 } 1012 mtx_unlock_spin(&icu_lock); 1013 printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 1014 return (0); 1015} 1016 1017/* 1018 * Enable a vector for a particular apic_id. Since all lapics share idt 1019 * entries and ioint_handlers this enables the vector on all lapics. lapics 1020 * which do not have the vector configured would report spurious interrupts 1021 * should it fire. 1022 */ 1023void 1024apic_enable_vector(u_int apic_id, u_int vector) 1025{ 1026 1027 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 1028 KASSERT(ioint_handlers[vector / 32] != NULL, 1029 ("No ISR handler for vector %u", vector)); 1030 setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL, 1031 GSEL_APIC); 1032} 1033 1034void 1035apic_disable_vector(u_int apic_id, u_int vector) 1036{ 1037 1038 KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 1039 KASSERT(ioint_handlers[vector / 32] != NULL, 1040 ("No ISR handler for vector %u", vector)); 1041#ifdef notyet 1042 /* 1043 * We can not currently clear the idt entry because other cpus 1044 * may have a valid vector at this offset. 1045 */ 1046 setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC); 1047#endif 1048} 1049 1050/* Release an APIC vector when it's no longer in use. */ 1051void 1052apic_free_vector(u_int apic_id, u_int vector, u_int irq) 1053{ 1054 struct thread *td; 1055 1056 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1057 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1058 ("Vector %u does not map to an IRQ line", vector)); 1059 KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 1060 KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] == 1061 irq, ("IRQ mismatch")); 1062 1063 /* 1064 * Bind us to the cpu that owned the vector before freeing it so 1065 * we don't lose an interrupt delivery race. 1066 */ 1067 td = curthread; 1068 if (!rebooting) { 1069 thread_lock(td); 1070 if (sched_is_bound(td)) 1071 panic("apic_free_vector: Thread already bound.\n"); 1072 sched_bind(td, apic_cpuid(apic_id)); 1073 thread_unlock(td); 1074 } 1075 mtx_lock_spin(&icu_lock); 1076 lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1; 1077 mtx_unlock_spin(&icu_lock); 1078 if (!rebooting) { 1079 thread_lock(td); 1080 sched_unbind(td); 1081 thread_unlock(td); 1082 } 1083} 1084 1085/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 1086u_int 1087apic_idt_to_irq(u_int apic_id, u_int vector) 1088{ 1089 int irq; 1090 1091 KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1092 vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1093 ("Vector %u does not map to an IRQ line", vector)); 1094 irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS]; 1095 if (irq < 0) 1096 irq = 0; 1097 return (irq); 1098} 1099 1100#ifdef DDB 1101/* 1102 * Dump data about APIC IDT vector mappings. 1103 */ 1104DB_SHOW_COMMAND(apic, db_show_apic) 1105{ 1106 struct intsrc *isrc; 1107 int i, verbose; 1108 u_int apic_id; 1109 u_int irq; 1110 1111 if (strcmp(modif, "vv") == 0) 1112 verbose = 2; 1113 else if (strcmp(modif, "v") == 0) 1114 verbose = 1; 1115 else 1116 verbose = 0; 1117 for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) { 1118 if (lapics[apic_id].la_present == 0) 1119 continue; 1120 db_printf("Interrupts bound to lapic %u\n", apic_id); 1121 for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 1122 irq = lapics[apic_id].la_ioint_irqs[i]; 1123 if (irq == -1 || irq == IRQ_SYSCALL) 1124 continue; 1125 db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 1126 if (irq == IRQ_TIMER) 1127 db_printf("lapic timer\n"); 1128 else if (irq < NUM_IO_INTS) { 1129 isrc = intr_lookup_source(irq); 1130 if (isrc == NULL || verbose == 0) 1131 db_printf("IRQ %u\n", irq); 1132 else 1133 db_dump_intr_event(isrc->is_event, 1134 verbose == 2); 1135 } else 1136 db_printf("IRQ %u ???\n", irq); 1137 } 1138 } 1139} 1140 1141static void 1142dump_mask(const char *prefix, uint32_t v, int base) 1143{ 1144 int i, first; 1145 1146 first = 1; 1147 for (i = 0; i < 32; i++) 1148 if (v & (1 << i)) { 1149 if (first) { 1150 db_printf("%s:", prefix); 1151 first = 0; 1152 } 1153 db_printf(" %02x", base + i); 1154 } 1155 if (!first) 1156 db_printf("\n"); 1157} 1158 1159/* Show info from the lapic regs for this CPU. */ 1160DB_SHOW_COMMAND(lapic, db_show_lapic) 1161{ 1162 uint32_t v; 1163 1164 db_printf("lapic ID = %d\n", lapic_id()); 1165 v = lapic->version; 1166 db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 1167 v & 0xf); 1168 db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 1169 v = lapic->svr; 1170 db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 1171 v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 1172 db_printf("TPR = %02x\n", lapic->tpr); 1173 1174#define dump_field(prefix, index) \ 1175 dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 1176 index * 32) 1177 1178 db_printf("In-service Interrupts:\n"); 1179 dump_field(isr, 0); 1180 dump_field(isr, 1); 1181 dump_field(isr, 2); 1182 dump_field(isr, 3); 1183 dump_field(isr, 4); 1184 dump_field(isr, 5); 1185 dump_field(isr, 6); 1186 dump_field(isr, 7); 1187 1188 db_printf("TMR Interrupts:\n"); 1189 dump_field(tmr, 0); 1190 dump_field(tmr, 1); 1191 dump_field(tmr, 2); 1192 dump_field(tmr, 3); 1193 dump_field(tmr, 4); 1194 dump_field(tmr, 5); 1195 dump_field(tmr, 6); 1196 dump_field(tmr, 7); 1197 1198 db_printf("IRR Interrupts:\n"); 1199 dump_field(irr, 0); 1200 dump_field(irr, 1); 1201 dump_field(irr, 2); 1202 dump_field(irr, 3); 1203 dump_field(irr, 4); 1204 dump_field(irr, 5); 1205 dump_field(irr, 6); 1206 dump_field(irr, 7); 1207 1208#undef dump_field 1209} 1210#endif 1211 1212/* 1213 * APIC probing support code. This includes code to manage enumerators. 1214 */ 1215 1216static SLIST_HEAD(, apic_enumerator) enumerators = 1217 SLIST_HEAD_INITIALIZER(enumerators); 1218static struct apic_enumerator *best_enum; 1219 1220void 1221apic_register_enumerator(struct apic_enumerator *enumerator) 1222{ 1223#ifdef INVARIANTS 1224 struct apic_enumerator *apic_enum; 1225 1226 SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1227 if (apic_enum == enumerator) 1228 panic("%s: Duplicate register of %s", __func__, 1229 enumerator->apic_name); 1230 } 1231#endif 1232 SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1233} 1234 1235/* 1236 * We have to look for CPU's very, very early because certain subsystems 1237 * want to know how many CPU's we have extremely early on in the boot 1238 * process. 1239 */ 1240static void 1241apic_init(void *dummy __unused) 1242{ 1243 struct apic_enumerator *enumerator; 1244#ifndef __amd64__ 1245 uint64_t apic_base; 1246#endif 1247 int retval, best; 1248 1249 /* We only support built in local APICs. */ 1250 if (!(cpu_feature & CPUID_APIC)) 1251 return; 1252 1253 /* Don't probe if APIC mode is disabled. */ 1254 if (resource_disabled("apic", 0)) 1255 return; 1256 1257 /* First, probe all the enumerators to find the best match. */ 1258 best_enum = NULL; 1259 best = 0; 1260 SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1261 retval = enumerator->apic_probe(); 1262 if (retval > 0) 1263 continue; 1264 if (best_enum == NULL || best < retval) { 1265 best_enum = enumerator; 1266 best = retval; 1267 } 1268 } 1269 if (best_enum == NULL) { 1270 if (bootverbose) 1271 printf("APIC: Could not find any APICs.\n"); 1272 return; 1273 } 1274 1275 if (bootverbose) 1276 printf("APIC: Using the %s enumerator.\n", 1277 best_enum->apic_name); 1278 1279#ifndef __amd64__ 1280 /* 1281 * To work around an errata, we disable the local APIC on some 1282 * CPUs during early startup. We need to turn the local APIC back 1283 * on on such CPUs now. 1284 */ 1285 if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL && 1286 (cpu_id & 0xff0) == 0x610) { 1287 apic_base = rdmsr(MSR_APICBASE); 1288 apic_base |= APICBASE_ENABLED; 1289 wrmsr(MSR_APICBASE, apic_base); 1290 } 1291#endif 1292 1293 /* Second, probe the CPU's in the system. */ 1294 retval = best_enum->apic_probe_cpus(); 1295 if (retval != 0) 1296 printf("%s: Failed to probe CPUs: returned %d\n", 1297 best_enum->apic_name, retval); 1298 1299#ifdef __amd64__ 1300} 1301SYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL); 1302 1303/* 1304 * Setup the local APIC. We have to do this prior to starting up the APs 1305 * in the SMP case. 1306 */ 1307static void 1308apic_setup_local(void *dummy __unused) 1309{ 1310 int retval; 1311 1312 if (best_enum == NULL) 1313 return; 1314#endif 1315 /* Third, initialize the local APIC. */ 1316 retval = best_enum->apic_setup_local(); 1317 if (retval != 0) 1318 printf("%s: Failed to setup the local APIC: returned %d\n", 1319 best_enum->apic_name, retval); 1320} 1321#ifdef __amd64__ 1322SYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, 1323 NULL); 1324#else 1325SYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL); 1326#endif 1327 1328/* 1329 * Setup the I/O APICs. 1330 */ 1331static void 1332apic_setup_io(void *dummy __unused) 1333{ 1334 int retval; 1335 1336 if (best_enum == NULL) 1337 return; 1338 retval = best_enum->apic_setup_io(); 1339 if (retval != 0) 1340 printf("%s: Failed to setup I/O APICs: returned %d\n", 1341 best_enum->apic_name, retval); 1342 1343#ifdef XEN 1344 return; 1345#endif 1346 /* 1347 * Finish setting up the local APIC on the BSP once we know how to 1348 * properly program the LINT pins. 1349 */ 1350 lapic_setup(1); 1351 intr_register_pic(&lapic_pic); 1352 if (bootverbose) 1353 lapic_dump("BSP"); 1354 1355 /* Enable the MSI "pic". */ 1356 msi_init(); 1357} 1358SYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1359 1360#ifdef SMP 1361/* 1362 * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1363 * private to the MD code. The public interface for the rest of the 1364 * kernel is defined in mp_machdep.c. 1365 */ 1366int 1367lapic_ipi_wait(int delay) 1368{ 1369 int x, incr; 1370 1371 /* 1372 * Wait delay loops for IPI to be sent. This is highly bogus 1373 * since this is sensitive to CPU clock speed. If delay is 1374 * -1, we wait forever. 1375 */ 1376 if (delay == -1) { 1377 incr = 0; 1378 delay = 1; 1379 } else 1380 incr = 1; 1381 for (x = 0; x < delay; x += incr) { 1382 if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1383 return (1); 1384 ia32_pause(); 1385 } 1386 return (0); 1387} 1388 1389void 1390lapic_ipi_raw(register_t icrlo, u_int dest) 1391{ 1392 register_t value, eflags; 1393 1394 /* XXX: Need more sanity checking of icrlo? */ 1395 KASSERT(lapic != NULL, ("%s called too early", __func__)); 1396 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1397 ("%s: invalid dest field", __func__)); 1398 KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1399 ("%s: reserved bits set in ICR LO register", __func__)); 1400 1401 /* Set destination in ICR HI register if it is being used. */ 1402 eflags = intr_disable(); 1403 if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1404 value = lapic->icr_hi; 1405 value &= ~APIC_ID_MASK; 1406 value |= dest << APIC_ID_SHIFT; 1407 lapic->icr_hi = value; 1408 } 1409 1410 /* Program the contents of the IPI and dispatch it. */ 1411 value = lapic->icr_lo; 1412 value &= APIC_ICRLO_RESV_MASK; 1413 value |= icrlo; 1414 lapic->icr_lo = value; 1415 intr_restore(eflags); 1416} 1417 1418#define BEFORE_SPIN 1000000 1419#ifdef DETECT_DEADLOCK 1420#define AFTER_SPIN 1000 1421#endif 1422 1423void 1424lapic_ipi_vectored(u_int vector, int dest) 1425{ 1426 register_t icrlo, destfield; 1427 1428 KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1429 ("%s: invalid vector %d", __func__, vector)); 1430 1431 icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE; 1432 1433 /* 1434 * IPI_STOP_HARD is just a "fake" vector used to send a NMI. 1435 * Use special rules regard NMI if passed, otherwise specify 1436 * the vector. 1437 */ 1438 if (vector == IPI_STOP_HARD) 1439 icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT; 1440 else 1441 icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT; 1442 destfield = 0; 1443 switch (dest) { 1444 case APIC_IPI_DEST_SELF: 1445 icrlo |= APIC_DEST_SELF; 1446 break; 1447 case APIC_IPI_DEST_ALL: 1448 icrlo |= APIC_DEST_ALLISELF; 1449 break; 1450 case APIC_IPI_DEST_OTHERS: 1451 icrlo |= APIC_DEST_ALLESELF; 1452 break; 1453 default: 1454 KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1455 ("%s: invalid destination 0x%x", __func__, dest)); 1456 destfield = dest; 1457 } 1458 1459 /* Wait for an earlier IPI to finish. */ 1460 if (!lapic_ipi_wait(BEFORE_SPIN)) { 1461 if (panicstr != NULL) 1462 return; 1463 else 1464 panic("APIC: Previous IPI is stuck"); 1465 } 1466 1467 lapic_ipi_raw(icrlo, destfield); 1468 1469#ifdef DETECT_DEADLOCK 1470 /* Wait for IPI to be delivered. */ 1471 if (!lapic_ipi_wait(AFTER_SPIN)) { 1472#ifdef needsattention 1473 /* 1474 * XXX FIXME: 1475 * 1476 * The above function waits for the message to actually be 1477 * delivered. It breaks out after an arbitrary timeout 1478 * since the message should eventually be delivered (at 1479 * least in theory) and that if it wasn't we would catch 1480 * the failure with the check above when the next IPI is 1481 * sent. 1482 * 1483 * We could skip this wait entirely, EXCEPT it probably 1484 * protects us from other routines that assume that the 1485 * message was delivered and acted upon when this function 1486 * returns. 1487 */ 1488 printf("APIC: IPI might be stuck\n"); 1489#else /* !needsattention */ 1490 /* Wait until mesage is sent without a timeout. */ 1491 while (lapic->icr_lo & APIC_DELSTAT_PEND) 1492 ia32_pause(); 1493#endif /* needsattention */ 1494 } 1495#endif /* DETECT_DEADLOCK */ 1496} 1497#endif /* SMP */ 1498