local_apic.c revision 209371
1121986Sjhb/*- 2121986Sjhb * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3121986Sjhb * Copyright (c) 1996, by Steve Passe 4121986Sjhb * All rights reserved. 5121986Sjhb * 6121986Sjhb * Redistribution and use in source and binary forms, with or without 7121986Sjhb * modification, are permitted provided that the following conditions 8121986Sjhb * are met: 9121986Sjhb * 1. Redistributions of source code must retain the above copyright 10121986Sjhb * notice, this list of conditions and the following disclaimer. 11121986Sjhb * 2. The name of the developer may NOT be used to endorse or promote products 12121986Sjhb * derived from this software without specific prior written permission. 13121986Sjhb * 3. Neither the name of the author nor the names of any co-contributors 14121986Sjhb * may be used to endorse or promote products derived from this software 15121986Sjhb * without specific prior written permission. 16121986Sjhb * 17121986Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18121986Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19121986Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20121986Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21121986Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22121986Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23121986Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24121986Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25121986Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26121986Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27121986Sjhb * SUCH DAMAGE. 28121986Sjhb */ 29121986Sjhb 30121986Sjhb/* 31121986Sjhb * Local APIC support on Pentium and later processors. 32121986Sjhb */ 33121986Sjhb 34121986Sjhb#include <sys/cdefs.h> 35121986Sjhb__FBSDID("$FreeBSD: head/sys/x86/x86/local_apic.c 209371 2010-06-20 21:33:29Z mav $"); 36121986Sjhb 37147565Speter#include "opt_hwpmc_hooks.h" 38179277Sjb#include "opt_kdtrace.h" 39147565Speter 40151979Sjhb#include "opt_ddb.h" 41151979Sjhb 42121986Sjhb#include <sys/param.h> 43121986Sjhb#include <sys/systm.h> 44121986Sjhb#include <sys/bus.h> 45121986Sjhb#include <sys/kernel.h> 46151979Sjhb#include <sys/lock.h> 47151979Sjhb#include <sys/mutex.h> 48121986Sjhb#include <sys/pcpu.h> 49187880Sjeff#include <sys/proc.h> 50187880Sjeff#include <sys/sched.h> 51141538Sjhb#include <sys/smp.h> 52209371Smav#include <sys/timeet.h> 53121986Sjhb 54121986Sjhb#include <vm/vm.h> 55121986Sjhb#include <vm/pmap.h> 56121986Sjhb 57121986Sjhb#include <machine/apicreg.h> 58153666Sjhb#include <machine/cpu.h> 59121986Sjhb#include <machine/cputypes.h> 60121986Sjhb#include <machine/frame.h> 61121986Sjhb#include <machine/intr_machdep.h> 62121986Sjhb#include <machine/apicvar.h> 63208507Sjhb#include <machine/mca.h> 64121986Sjhb#include <machine/md_var.h> 65121986Sjhb#include <machine/smp.h> 66121986Sjhb#include <machine/specialreg.h> 67121986Sjhb 68151979Sjhb#ifdef DDB 69151979Sjhb#include <sys/interrupt.h> 70151979Sjhb#include <ddb/ddb.h> 71151979Sjhb#endif 72151979Sjhb 73208452Smav#ifdef __amd64__ 74208452Smav#define SDT_APIC SDT_SYSIGT 75208452Smav#define SDT_APICT SDT_SYSIGT 76208452Smav#define GSEL_APIC 0 77208452Smav#else 78208452Smav#define SDT_APIC SDT_SYS386IGT 79208452Smav#define SDT_APICT SDT_SYS386TGT 80208452Smav#define GSEL_APIC GSEL(GCODE_SEL, SEL_KPL) 81208452Smav#endif 82208452Smav 83122690Sjhb/* Sanity checks on IDT vectors. */ 84139240SjhbCTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 85139240SjhbCTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 86139240SjhbCTASSERT(APIC_LOCAL_INTS == 240); 87122690SjhbCTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 88122690Sjhb 89151979Sjhb/* Magic IRQ values for the timer and syscalls. */ 90151979Sjhb#define IRQ_TIMER (NUM_IO_INTS + 1) 91151979Sjhb#define IRQ_SYSCALL (NUM_IO_INTS + 2) 92151979Sjhb 93121986Sjhb/* 94121986Sjhb * Support for local APICs. Local APICs manage interrupts on each 95121986Sjhb * individual processor as opposed to I/O APICs which receive interrupts 96121986Sjhb * from I/O devices and then forward them on to the local APICs. 97121986Sjhb * 98121986Sjhb * Local APICs can also send interrupts to each other thus providing the 99121986Sjhb * mechanism for IPIs. 100121986Sjhb */ 101121986Sjhb 102121986Sjhbstruct lvt { 103121986Sjhb u_int lvt_edgetrigger:1; 104121986Sjhb u_int lvt_activehi:1; 105121986Sjhb u_int lvt_masked:1; 106121986Sjhb u_int lvt_active:1; 107121986Sjhb u_int lvt_mode:16; 108121986Sjhb u_int lvt_vector:8; 109121986Sjhb}; 110121986Sjhb 111121986Sjhbstruct lapic { 112121986Sjhb struct lvt la_lvts[LVT_MAX + 1]; 113121986Sjhb u_int la_id:8; 114121986Sjhb u_int la_cluster:4; 115121986Sjhb u_int la_cluster_id:2; 116121986Sjhb u_int la_present:1; 117141538Sjhb u_long *la_timer_count; 118209371Smav u_long la_timer_period; 119209371Smav u_int la_timer_mode; 120187880Sjeff /* Include IDT_SYSCALL to make indexing easier. */ 121191720Smav int la_ioint_irqs[APIC_NUM_IOINTS + 1]; 122169395Sjhb} static lapics[MAX_APIC_ID + 1]; 123121986Sjhb 124121986Sjhb/* Global defaults for local APIC LVT entries. */ 125121986Sjhbstatic struct lvt lvts[LVT_MAX + 1] = { 126121986Sjhb { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 127121986Sjhb { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 128139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 129205851Sjhb { 1, 1, 0, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 130196224Sjhb { 1, 1, 1, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 131139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 132208507Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_CMC_INT }, /* CMCI */ 133121986Sjhb}; 134121986Sjhb 135121986Sjhbstatic inthand_t *ioint_handlers[] = { 136121986Sjhb NULL, /* 0 - 31 */ 137121986Sjhb IDTVEC(apic_isr1), /* 32 - 63 */ 138121986Sjhb IDTVEC(apic_isr2), /* 64 - 95 */ 139121986Sjhb IDTVEC(apic_isr3), /* 96 - 127 */ 140121986Sjhb IDTVEC(apic_isr4), /* 128 - 159 */ 141121986Sjhb IDTVEC(apic_isr5), /* 160 - 191 */ 142122690Sjhb IDTVEC(apic_isr6), /* 192 - 223 */ 143122690Sjhb IDTVEC(apic_isr7), /* 224 - 255 */ 144121986Sjhb}; 145121986Sjhb 146151979Sjhb 147195249Sjhbstatic u_int32_t lapic_timer_divisors[] = { 148141538Sjhb APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 149141538Sjhb APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 150141538Sjhb}; 151141538Sjhb 152169391Sjhbextern inthand_t IDTVEC(rsvd); 153169391Sjhb 154121986Sjhbvolatile lapic_t *lapic; 155167747Sjhbvm_paddr_t lapic_paddr; 156209371Smavstatic u_long lapic_timer_divisor; 157209371Smavstatic struct eventtimer lapic_et; 158121986Sjhb 159139245Sjhbstatic void lapic_enable(void); 160163219Sjhbstatic void lapic_resume(struct pic *pic); 161141538Sjhbstatic void lapic_timer_enable_intr(void); 162141538Sjhbstatic void lapic_timer_oneshot(u_int count); 163141538Sjhbstatic void lapic_timer_periodic(u_int count); 164209371Smavstatic void lapic_timer_stop(void); 165141538Sjhbstatic void lapic_timer_set_divisor(u_int divisor); 166139245Sjhbstatic uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 167209371Smavstatic int lapic_et_start(struct eventtimer *et, 168209371Smav struct bintime *first, struct bintime *period); 169209371Smavstatic int lapic_et_stop(struct eventtimer *et); 170139245Sjhb 171163219Sjhbstruct pic lapic_pic = { .pic_resume = lapic_resume }; 172163219Sjhb 173121986Sjhbstatic uint32_t 174121986Sjhblvt_mode(struct lapic *la, u_int pin, uint32_t value) 175121986Sjhb{ 176121986Sjhb struct lvt *lvt; 177121986Sjhb 178121986Sjhb KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 179121986Sjhb if (la->la_lvts[pin].lvt_active) 180121986Sjhb lvt = &la->la_lvts[pin]; 181121986Sjhb else 182121986Sjhb lvt = &lvts[pin]; 183121986Sjhb 184121986Sjhb value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 185121986Sjhb APIC_LVT_VECTOR); 186121986Sjhb if (lvt->lvt_edgetrigger == 0) 187121986Sjhb value |= APIC_LVT_TM; 188121986Sjhb if (lvt->lvt_activehi == 0) 189121986Sjhb value |= APIC_LVT_IIPP_INTALO; 190121986Sjhb if (lvt->lvt_masked) 191121986Sjhb value |= APIC_LVT_M; 192121986Sjhb value |= lvt->lvt_mode; 193121986Sjhb switch (lvt->lvt_mode) { 194121986Sjhb case APIC_LVT_DM_NMI: 195121986Sjhb case APIC_LVT_DM_SMI: 196121986Sjhb case APIC_LVT_DM_INIT: 197121986Sjhb case APIC_LVT_DM_EXTINT: 198121986Sjhb if (!lvt->lvt_edgetrigger) { 199121986Sjhb printf("lapic%u: Forcing LINT%u to edge trigger\n", 200121986Sjhb la->la_id, pin); 201121986Sjhb value |= APIC_LVT_TM; 202121986Sjhb } 203121986Sjhb /* Use a vector of 0. */ 204121986Sjhb break; 205121986Sjhb case APIC_LVT_DM_FIXED: 206121986Sjhb value |= lvt->lvt_vector; 207121986Sjhb break; 208121986Sjhb default: 209121986Sjhb panic("bad APIC LVT delivery mode: %#x\n", value); 210121986Sjhb } 211121986Sjhb return (value); 212121986Sjhb} 213121986Sjhb 214121986Sjhb/* 215121986Sjhb * Map the local APIC and setup necessary interrupt vectors. 216121986Sjhb */ 217121986Sjhbvoid 218167247Sjhblapic_init(vm_paddr_t addr) 219121986Sjhb{ 220209371Smav u_int regs[4]; 221209371Smav int i, arat; 222121986Sjhb 223121986Sjhb /* Map the local APIC and setup the spurious interrupt handler. */ 224121986Sjhb KASSERT(trunc_page(addr) == addr, 225121986Sjhb ("local APIC not aligned on a page boundary")); 226156920Sjhb lapic = pmap_mapdev(addr, sizeof(lapic_t)); 227167747Sjhb lapic_paddr = addr; 228208452Smav setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_APIC, SEL_KPL, 229208452Smav GSEL_APIC); 230121986Sjhb 231121986Sjhb /* Perform basic initialization of the BSP's local APIC. */ 232139245Sjhb lapic_enable(); 233121986Sjhb 234121986Sjhb /* Set BSP's per-CPU local APIC ID. */ 235121986Sjhb PCPU_SET(apic_id, lapic_id()); 236121986Sjhb 237141538Sjhb /* Local APIC timer interrupt. */ 238208452Smav setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_APIC, SEL_KPL, GSEL_APIC); 239141538Sjhb 240205851Sjhb /* Local APIC error interrupt. */ 241208452Smav setidt(APIC_ERROR_INT, IDTVEC(errorint), SDT_APIC, SEL_KPL, GSEL_APIC); 242205851Sjhb 243205851Sjhb /* XXX: Thermal interrupt */ 244208507Sjhb 245208507Sjhb /* Local APIC CMCI. */ 246208507Sjhb setidt(APIC_CMC_INT, IDTVEC(cmcint), SDT_APICT, SEL_KPL, GSEL_APIC); 247209371Smav 248209371Smav if ((resource_int_value("apic", 0, "clock", &i) != 0 || i != 0)) { 249209371Smav arat = 0; 250209371Smav /* Intel CPUID 0x06 EAX[2] set if APIC timer runs in C3. */ 251209371Smav if (cpu_vendor_id == CPU_VENDOR_INTEL && cpu_high >= 6) { 252209371Smav do_cpuid(0x06, regs); 253209371Smav if (regs[0] & 0x4) 254209371Smav arat = 1; 255209371Smav } 256209371Smav bzero(&lapic_et, sizeof(lapic_et)); 257209371Smav lapic_et.et_name = "LAPIC"; 258209371Smav lapic_et.et_flags = ET_FLAGS_PERIODIC | ET_FLAGS_ONESHOT | 259209371Smav ET_FLAGS_PERCPU; 260209371Smav lapic_et.et_quality = 600; 261209371Smav if (!arat) { 262209371Smav lapic_et.et_flags |= ET_FLAGS_C3STOP; 263209371Smav lapic_et.et_quality -= 100; 264209371Smav } 265209371Smav lapic_et.et_frequency = 0; 266209371Smav lapic_et.et_start = lapic_et_start; 267209371Smav lapic_et.et_stop = lapic_et_stop; 268209371Smav lapic_et.et_priv = NULL; 269209371Smav et_register(&lapic_et); 270209371Smav } 271121986Sjhb} 272121986Sjhb 273121986Sjhb/* 274121986Sjhb * Create a local APIC instance. 275121986Sjhb */ 276121986Sjhbvoid 277121986Sjhblapic_create(u_int apic_id, int boot_cpu) 278121986Sjhb{ 279121986Sjhb int i; 280121986Sjhb 281169395Sjhb if (apic_id > MAX_APIC_ID) { 282121986Sjhb printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 283121986Sjhb if (boot_cpu) 284121986Sjhb panic("Can't ignore BSP"); 285121986Sjhb return; 286121986Sjhb } 287121986Sjhb KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 288121986Sjhb apic_id)); 289121986Sjhb 290121986Sjhb /* 291121986Sjhb * Assume no local LVT overrides and a cluster of 0 and 292121986Sjhb * intra-cluster ID of 0. 293121986Sjhb */ 294121986Sjhb lapics[apic_id].la_present = 1; 295121986Sjhb lapics[apic_id].la_id = apic_id; 296208507Sjhb for (i = 0; i <= LVT_MAX; i++) { 297121986Sjhb lapics[apic_id].la_lvts[i] = lvts[i]; 298121986Sjhb lapics[apic_id].la_lvts[i].lvt_active = 0; 299121986Sjhb } 300191720Smav for (i = 0; i <= APIC_NUM_IOINTS; i++) 301191720Smav lapics[apic_id].la_ioint_irqs[i] = -1; 302187880Sjeff lapics[apic_id].la_ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 303187880Sjeff lapics[apic_id].la_ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = 304187880Sjeff IRQ_TIMER; 305121986Sjhb 306121986Sjhb#ifdef SMP 307121986Sjhb cpu_add(apic_id, boot_cpu); 308121986Sjhb#endif 309121986Sjhb} 310121986Sjhb 311121986Sjhb/* 312121986Sjhb * Dump contents of local APIC registers 313121986Sjhb */ 314121986Sjhbvoid 315121986Sjhblapic_dump(const char* str) 316121986Sjhb{ 317121986Sjhb 318121986Sjhb printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 319121986Sjhb printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 320121986Sjhb lapic->id, lapic->version, lapic->ldr, lapic->dfr); 321121986Sjhb printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 322121986Sjhb lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 323205851Sjhb printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pmc: 0x%08x\n", 324139245Sjhb lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 325139245Sjhb lapic->lvt_pcint); 326208507Sjhb printf(" cmci: 0x%08x\n", lapic->lvt_cmci); 327121986Sjhb} 328121986Sjhb 329121986Sjhbvoid 330163219Sjhblapic_setup(int boot) 331121986Sjhb{ 332121986Sjhb struct lapic *la; 333156124Sjhb u_int32_t maxlvt; 334121986Sjhb register_t eflags; 335141538Sjhb char buf[MAXCOMLEN + 1]; 336121986Sjhb 337121986Sjhb la = &lapics[lapic_id()]; 338121986Sjhb KASSERT(la->la_present, ("missing APIC structure")); 339121986Sjhb eflags = intr_disable(); 340121986Sjhb maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 341121986Sjhb 342139240Sjhb /* Initialize the TPR to allow all interrupts. */ 343139240Sjhb lapic_set_tpr(0); 344121986Sjhb 345121986Sjhb /* Setup spurious vector and enable the local APIC. */ 346139245Sjhb lapic_enable(); 347139245Sjhb 348139245Sjhb /* Program LINT[01] LVT entries. */ 349139245Sjhb lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 350139245Sjhb lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 351185933Sjhb 352145256Sjkoshy /* Program the PMC LVT entry if present. */ 353145256Sjkoshy if (maxlvt >= LVT_PMC) 354145256Sjkoshy lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 355139245Sjhb 356141538Sjhb /* Program timer LVT and setup handler. */ 357141538Sjhb lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 358163219Sjhb if (boot) { 359209371Smav snprintf(buf, sizeof(buf), "cpu%d:timer", PCPU_GET(cpuid)); 360163219Sjhb intrcnt_add(buf, &la->la_timer_count); 361163219Sjhb } 362163219Sjhb 363209371Smav /* Setup the timer if configured. */ 364209371Smav if (la->la_timer_mode != 0) { 365209371Smav KASSERT(la->la_timer_period != 0, ("lapic%u: zero divisor", 366141538Sjhb lapic_id())); 367141538Sjhb lapic_timer_set_divisor(lapic_timer_divisor); 368209371Smav if (la->la_timer_mode == 1) 369209371Smav lapic_timer_periodic(la->la_timer_period); 370209371Smav else 371209371Smav lapic_timer_oneshot(la->la_timer_period); 372141538Sjhb lapic_timer_enable_intr(); 373141538Sjhb } 374139245Sjhb 375205851Sjhb /* Program error LVT and clear any existing errors. */ 376205851Sjhb lapic->lvt_error = lvt_mode(la, LVT_ERROR, lapic->lvt_error); 377205851Sjhb lapic->esr = 0; 378141538Sjhb 379205851Sjhb /* XXX: Thermal LVT */ 380205851Sjhb 381208507Sjhb /* Program the CMCI LVT entry if present. */ 382208507Sjhb if (maxlvt >= LVT_CMCI) 383208507Sjhb lapic->lvt_cmci = lvt_mode(la, LVT_CMCI, lapic->lvt_cmci); 384208507Sjhb 385121986Sjhb intr_restore(eflags); 386121986Sjhb} 387121986Sjhb 388196224Sjhbvoid 389196224Sjhblapic_reenable_pmc(void) 390196224Sjhb{ 391196224Sjhb#ifdef HWPMC_HOOKS 392196224Sjhb uint32_t value; 393196224Sjhb 394196224Sjhb value = lapic->lvt_pcint; 395196224Sjhb value &= ~APIC_LVT_M; 396196224Sjhb lapic->lvt_pcint = value; 397196224Sjhb#endif 398196224Sjhb} 399196224Sjhb 400196224Sjhb#ifdef HWPMC_HOOKS 401196224Sjhbstatic void 402196224Sjhblapic_update_pmc(void *dummy) 403196224Sjhb{ 404196224Sjhb struct lapic *la; 405196224Sjhb 406196224Sjhb la = &lapics[lapic_id()]; 407196224Sjhb lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 408196224Sjhb} 409196224Sjhb#endif 410196224Sjhb 411196224Sjhbint 412196224Sjhblapic_enable_pmc(void) 413196224Sjhb{ 414196224Sjhb#ifdef HWPMC_HOOKS 415196224Sjhb u_int32_t maxlvt; 416196224Sjhb 417196224Sjhb /* Fail if the local APIC is not present. */ 418196224Sjhb if (lapic == NULL) 419196224Sjhb return (0); 420196224Sjhb 421196224Sjhb /* Fail if the PMC LVT is not present. */ 422196224Sjhb maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 423196224Sjhb if (maxlvt < LVT_PMC) 424196224Sjhb return (0); 425196224Sjhb 426196224Sjhb lvts[LVT_PMC].lvt_masked = 0; 427196224Sjhb 428196224Sjhb#ifdef SMP 429196224Sjhb /* 430196224Sjhb * If hwpmc was loaded at boot time then the APs may not be 431196224Sjhb * started yet. In that case, don't forward the request to 432196224Sjhb * them as they will program the lvt when they start. 433196224Sjhb */ 434196224Sjhb if (smp_started) 435196224Sjhb smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 436196224Sjhb else 437196224Sjhb#endif 438196224Sjhb lapic_update_pmc(NULL); 439196224Sjhb return (1); 440196224Sjhb#else 441196224Sjhb return (0); 442196224Sjhb#endif 443196224Sjhb} 444196224Sjhb 445196224Sjhbvoid 446196224Sjhblapic_disable_pmc(void) 447196224Sjhb{ 448196224Sjhb#ifdef HWPMC_HOOKS 449196224Sjhb u_int32_t maxlvt; 450196224Sjhb 451196224Sjhb /* Fail if the local APIC is not present. */ 452196224Sjhb if (lapic == NULL) 453196224Sjhb return; 454196224Sjhb 455196224Sjhb /* Fail if the PMC LVT is not present. */ 456196224Sjhb maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 457196224Sjhb if (maxlvt < LVT_PMC) 458196224Sjhb return; 459196224Sjhb 460196224Sjhb lvts[LVT_PMC].lvt_masked = 1; 461196224Sjhb 462196224Sjhb#ifdef SMP 463196224Sjhb /* The APs should always be started when hwpmc is unloaded. */ 464196224Sjhb KASSERT(mp_ncpus == 1 || smp_started, ("hwpmc unloaded too early")); 465196224Sjhb#endif 466196224Sjhb smp_rendezvous(NULL, lapic_update_pmc, NULL, NULL); 467196224Sjhb#endif 468196224Sjhb} 469196224Sjhb 470209371Smavstatic int 471209371Smavlapic_et_start(struct eventtimer *et, 472209371Smav struct bintime *first, struct bintime *period) 473141538Sjhb{ 474209371Smav struct lapic *la; 475141538Sjhb u_long value; 476141538Sjhb 477209371Smav if (et->et_frequency == 0) { 478209371Smav /* Start off with a divisor of 2 (power on reset default). */ 479209371Smav lapic_timer_divisor = 2; 480209371Smav /* Try to calibrate the local APIC timer. */ 481209371Smav do { 482209371Smav lapic_timer_set_divisor(lapic_timer_divisor); 483209371Smav lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 484209371Smav DELAY(1000000); 485209371Smav value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 486209371Smav if (value != APIC_TIMER_MAX_COUNT) 487209371Smav break; 488209371Smav lapic_timer_divisor <<= 1; 489209371Smav } while (lapic_timer_divisor <= 128); 490209371Smav if (lapic_timer_divisor > 128) 491209371Smav panic("lapic: Divisor too big"); 492209371Smav if (bootverbose) 493209371Smav printf("lapic: Divisor %lu, Frequency %lu Hz\n", 494209371Smav lapic_timer_divisor, value); 495209371Smav et->et_frequency = value; 496204641Sattilio } 497209371Smav la = &lapics[lapic_id()]; 498141538Sjhb /* 499141538Sjhb * Start up the timer on the BSP. The APs will kick off their 500141538Sjhb * timer during lapic_setup(). 501141538Sjhb */ 502209371Smav lapic_timer_set_divisor(lapic_timer_divisor); 503209371Smav if (period != NULL) { 504209371Smav la->la_timer_mode = 1; 505209371Smav la->la_timer_period = 506209371Smav (et->et_frequency * (period->frac >> 32)) >> 32; 507209371Smav if (period->sec != 0) 508209371Smav la->la_timer_period += et->et_frequency * period->sec; 509209371Smav lapic_timer_periodic(la->la_timer_period); 510209371Smav } else { 511209371Smav la->la_timer_mode = 2; 512209371Smav la->la_timer_period = 513209371Smav (et->et_frequency * (first->frac >> 32)) >> 32; 514209371Smav if (first->sec != 0) 515209371Smav la->la_timer_period += et->et_frequency * first->sec; 516209371Smav lapic_timer_oneshot(la->la_timer_period); 517209371Smav } 518141538Sjhb lapic_timer_enable_intr(); 519209371Smav return (0); 520141538Sjhb} 521141538Sjhb 522209371Smavstatic int 523209371Smavlapic_et_stop(struct eventtimer *et) 524209371Smav{ 525209371Smav struct lapic *la = &lapics[lapic_id()]; 526209371Smav 527209371Smav la->la_timer_mode = 0; 528209371Smav lapic_timer_stop(); 529209371Smav return (0); 530209371Smav} 531209371Smav 532121986Sjhbvoid 533121986Sjhblapic_disable(void) 534121986Sjhb{ 535121986Sjhb uint32_t value; 536121986Sjhb 537121986Sjhb /* Software disable the local APIC. */ 538121986Sjhb value = lapic->svr; 539121986Sjhb value &= ~APIC_SVR_SWEN; 540121986Sjhb lapic->svr = value; 541121986Sjhb} 542121986Sjhb 543139245Sjhbstatic void 544139245Sjhblapic_enable(void) 545139245Sjhb{ 546139245Sjhb u_int32_t value; 547139245Sjhb 548139245Sjhb /* Program the spurious vector to enable the local APIC. */ 549139245Sjhb value = lapic->svr; 550139245Sjhb value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 551139245Sjhb value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 552139245Sjhb lapic->svr = value; 553139245Sjhb} 554139245Sjhb 555163219Sjhb/* Reset the local APIC on the BSP during resume. */ 556163219Sjhbstatic void 557163219Sjhblapic_resume(struct pic *pic) 558163219Sjhb{ 559163219Sjhb 560163219Sjhb lapic_setup(0); 561163219Sjhb} 562163219Sjhb 563121986Sjhbint 564121986Sjhblapic_id(void) 565121986Sjhb{ 566121986Sjhb 567121986Sjhb KASSERT(lapic != NULL, ("local APIC is not mapped")); 568121986Sjhb return (lapic->id >> APIC_ID_SHIFT); 569121986Sjhb} 570121986Sjhb 571121986Sjhbint 572121986Sjhblapic_intr_pending(u_int vector) 573121986Sjhb{ 574121986Sjhb volatile u_int32_t *irr; 575121986Sjhb 576121986Sjhb /* 577121986Sjhb * The IRR registers are an array of 128-bit registers each of 578121986Sjhb * which only describes 32 interrupts in the low 32 bits.. Thus, 579121986Sjhb * we divide the vector by 32 to get the 128-bit index. We then 580121986Sjhb * multiply that index by 4 to get the equivalent index from 581121986Sjhb * treating the IRR as an array of 32-bit registers. Finally, we 582121986Sjhb * modulus the vector by 32 to determine the individual bit to 583121986Sjhb * test. 584121986Sjhb */ 585121986Sjhb irr = &lapic->irr0; 586121986Sjhb return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 587121986Sjhb} 588121986Sjhb 589121986Sjhbvoid 590121986Sjhblapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 591121986Sjhb{ 592121986Sjhb struct lapic *la; 593121986Sjhb 594121986Sjhb KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 595121986Sjhb __func__, apic_id)); 596121986Sjhb KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 597121986Sjhb __func__, cluster)); 598121986Sjhb KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 599121986Sjhb ("%s: intra cluster id %u too big", __func__, cluster_id)); 600121986Sjhb la = &lapics[apic_id]; 601121986Sjhb la->la_cluster = cluster; 602121986Sjhb la->la_cluster_id = cluster_id; 603121986Sjhb} 604121986Sjhb 605121986Sjhbint 606121986Sjhblapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 607121986Sjhb{ 608121986Sjhb 609121986Sjhb if (pin > LVT_MAX) 610121986Sjhb return (EINVAL); 611121986Sjhb if (apic_id == APIC_ID_ALL) { 612121986Sjhb lvts[pin].lvt_masked = masked; 613121986Sjhb if (bootverbose) 614121986Sjhb printf("lapic:"); 615121986Sjhb } else { 616121986Sjhb KASSERT(lapics[apic_id].la_present, 617121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 618121986Sjhb lapics[apic_id].la_lvts[pin].lvt_masked = masked; 619121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 620121986Sjhb if (bootverbose) 621121986Sjhb printf("lapic%u:", apic_id); 622121986Sjhb } 623121986Sjhb if (bootverbose) 624121986Sjhb printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 625121986Sjhb return (0); 626121986Sjhb} 627121986Sjhb 628121986Sjhbint 629121986Sjhblapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 630121986Sjhb{ 631121986Sjhb struct lvt *lvt; 632121986Sjhb 633121986Sjhb if (pin > LVT_MAX) 634121986Sjhb return (EINVAL); 635121986Sjhb if (apic_id == APIC_ID_ALL) { 636121986Sjhb lvt = &lvts[pin]; 637121986Sjhb if (bootverbose) 638121986Sjhb printf("lapic:"); 639121986Sjhb } else { 640121986Sjhb KASSERT(lapics[apic_id].la_present, 641121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 642121986Sjhb lvt = &lapics[apic_id].la_lvts[pin]; 643121986Sjhb lvt->lvt_active = 1; 644121986Sjhb if (bootverbose) 645121986Sjhb printf("lapic%u:", apic_id); 646121986Sjhb } 647121986Sjhb lvt->lvt_mode = mode; 648121986Sjhb switch (mode) { 649121986Sjhb case APIC_LVT_DM_NMI: 650121986Sjhb case APIC_LVT_DM_SMI: 651121986Sjhb case APIC_LVT_DM_INIT: 652121986Sjhb case APIC_LVT_DM_EXTINT: 653121986Sjhb lvt->lvt_edgetrigger = 1; 654121986Sjhb lvt->lvt_activehi = 1; 655121986Sjhb if (mode == APIC_LVT_DM_EXTINT) 656121986Sjhb lvt->lvt_masked = 1; 657121986Sjhb else 658121986Sjhb lvt->lvt_masked = 0; 659121986Sjhb break; 660121986Sjhb default: 661121986Sjhb panic("Unsupported delivery mode: 0x%x\n", mode); 662121986Sjhb } 663121986Sjhb if (bootverbose) { 664121986Sjhb printf(" Routing "); 665121986Sjhb switch (mode) { 666121986Sjhb case APIC_LVT_DM_NMI: 667121986Sjhb printf("NMI"); 668121986Sjhb break; 669121986Sjhb case APIC_LVT_DM_SMI: 670121986Sjhb printf("SMI"); 671121986Sjhb break; 672121986Sjhb case APIC_LVT_DM_INIT: 673121986Sjhb printf("INIT"); 674121986Sjhb break; 675121986Sjhb case APIC_LVT_DM_EXTINT: 676121986Sjhb printf("ExtINT"); 677121986Sjhb break; 678121986Sjhb } 679121986Sjhb printf(" -> LINT%u\n", pin); 680121986Sjhb } 681121986Sjhb return (0); 682121986Sjhb} 683121986Sjhb 684121986Sjhbint 685128930Sjhblapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 686121986Sjhb{ 687121986Sjhb 688128930Sjhb if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 689121986Sjhb return (EINVAL); 690121986Sjhb if (apic_id == APIC_ID_ALL) { 691128930Sjhb lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 692121986Sjhb if (bootverbose) 693121986Sjhb printf("lapic:"); 694121986Sjhb } else { 695121986Sjhb KASSERT(lapics[apic_id].la_present, 696121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 697121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 698128930Sjhb lapics[apic_id].la_lvts[pin].lvt_activehi = 699128930Sjhb (pol == INTR_POLARITY_HIGH); 700121986Sjhb if (bootverbose) 701121986Sjhb printf("lapic%u:", apic_id); 702121986Sjhb } 703121986Sjhb if (bootverbose) 704140254Sjhb printf(" LINT%u polarity: %s\n", pin, 705128930Sjhb pol == INTR_POLARITY_HIGH ? "high" : "low"); 706121986Sjhb return (0); 707121986Sjhb} 708121986Sjhb 709121986Sjhbint 710128930Sjhblapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 711121986Sjhb{ 712121986Sjhb 713128930Sjhb if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 714121986Sjhb return (EINVAL); 715121986Sjhb if (apic_id == APIC_ID_ALL) { 716128930Sjhb lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 717121986Sjhb if (bootverbose) 718121986Sjhb printf("lapic:"); 719121986Sjhb } else { 720121986Sjhb KASSERT(lapics[apic_id].la_present, 721121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 722128930Sjhb lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 723128930Sjhb (trigger == INTR_TRIGGER_EDGE); 724121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 725121986Sjhb if (bootverbose) 726121986Sjhb printf("lapic%u:", apic_id); 727121986Sjhb } 728121986Sjhb if (bootverbose) 729121986Sjhb printf(" LINT%u trigger: %s\n", pin, 730128930Sjhb trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 731121986Sjhb return (0); 732121986Sjhb} 733121986Sjhb 734139240Sjhb/* 735139240Sjhb * Adjust the TPR of the current CPU so that it blocks all interrupts below 736139240Sjhb * the passed in vector. 737139240Sjhb */ 738121986Sjhbvoid 739139240Sjhblapic_set_tpr(u_int vector) 740139240Sjhb{ 741139240Sjhb#ifdef CHEAP_TPR 742139240Sjhb lapic->tpr = vector; 743139240Sjhb#else 744139240Sjhb u_int32_t tpr; 745139240Sjhb 746139240Sjhb tpr = lapic->tpr & ~APIC_TPR_PRIO; 747139240Sjhb tpr |= vector; 748139240Sjhb lapic->tpr = tpr; 749139240Sjhb#endif 750139240Sjhb} 751139240Sjhb 752139240Sjhbvoid 753122572Sjhblapic_eoi(void) 754122572Sjhb{ 755122572Sjhb 756122572Sjhb lapic->eoi = 0; 757122572Sjhb} 758122572Sjhb 759122572Sjhbvoid 760165302Skmacylapic_handle_intr(int vector, struct trapframe *frame) 761121986Sjhb{ 762121986Sjhb struct intsrc *isrc; 763121986Sjhb 764153146Sjhb if (vector == -1) 765121986Sjhb panic("Couldn't get vector from ISR!"); 766187880Sjeff isrc = intr_lookup_source(apic_idt_to_irq(PCPU_GET(apic_id), 767187880Sjeff vector)); 768165302Skmacy intr_execute_handlers(isrc, frame); 769121986Sjhb} 770121986Sjhb 771141538Sjhbvoid 772165302Skmacylapic_handle_timer(struct trapframe *frame) 773141538Sjhb{ 774141538Sjhb struct lapic *la; 775209371Smav struct trapframe *oldframe; 776209371Smav struct thread *td; 777141538Sjhb 778153141Sjhb /* Send EOI first thing. */ 779153141Sjhb lapic_eoi(); 780153141Sjhb 781162708Ssobomax#if defined(SMP) && !defined(SCHED_ULE) 782162042Ssobomax /* 783162042Ssobomax * Don't do any accounting for the disabled HTT cores, since it 784162042Ssobomax * will provide misleading numbers for the userland. 785162042Ssobomax * 786162042Ssobomax * No locking is necessary here, since even if we loose the race 787162042Ssobomax * when hlt_cpus_mask changes it is not a big deal, really. 788162713Ssobomax * 789162713Ssobomax * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 790162713Ssobomax * and unlike other schedulers it actually schedules threads to 791162713Ssobomax * those CPUs. 792162042Ssobomax */ 793162042Ssobomax if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 794162042Ssobomax return; 795162087Ssobomax#endif 796162042Ssobomax 797153141Sjhb /* Look up our local APIC structure for the tick counters. */ 798141538Sjhb la = &lapics[PCPU_GET(apic_id)]; 799141538Sjhb (*la->la_timer_count)++; 800141538Sjhb critical_enter(); 801209371Smav if (lapic_et.et_active) { 802209371Smav td = curthread; 803209371Smav oldframe = td->td_intr_frame; 804209371Smav td->td_intr_frame = frame; 805209371Smav lapic_et.et_event_cb(&lapic_et, 806209371Smav lapic_et.et_arg ? lapic_et.et_arg : frame); 807209371Smav td->td_intr_frame = oldframe; 808209371Smav } 809141538Sjhb critical_exit(); 810141538Sjhb} 811141538Sjhb 812141538Sjhbstatic void 813141538Sjhblapic_timer_set_divisor(u_int divisor) 814141538Sjhb{ 815141538Sjhb 816141538Sjhb KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 817141538Sjhb KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 818141538Sjhb sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 819141538Sjhb lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 820141538Sjhb} 821141538Sjhb 822141538Sjhbstatic void 823141538Sjhblapic_timer_oneshot(u_int count) 824141538Sjhb{ 825141538Sjhb u_int32_t value; 826141538Sjhb 827141538Sjhb value = lapic->lvt_timer; 828141538Sjhb value &= ~APIC_LVTT_TM; 829141538Sjhb value |= APIC_LVTT_TM_ONE_SHOT; 830141538Sjhb lapic->lvt_timer = value; 831141538Sjhb lapic->icr_timer = count; 832141538Sjhb} 833141538Sjhb 834141538Sjhbstatic void 835141538Sjhblapic_timer_periodic(u_int count) 836141538Sjhb{ 837141538Sjhb u_int32_t value; 838141538Sjhb 839141538Sjhb value = lapic->lvt_timer; 840141538Sjhb value &= ~APIC_LVTT_TM; 841141538Sjhb value |= APIC_LVTT_TM_PERIODIC; 842141538Sjhb lapic->lvt_timer = value; 843141538Sjhb lapic->icr_timer = count; 844141538Sjhb} 845141538Sjhb 846141538Sjhbstatic void 847209371Smavlapic_timer_stop(void) 848209371Smav{ 849209371Smav u_int32_t value; 850209371Smav 851209371Smav value = lapic->lvt_timer; 852209371Smav value &= ~APIC_LVTT_TM; 853209371Smav value &= ~APIC_LVT_M; 854209371Smav lapic->lvt_timer = value; 855209371Smav} 856209371Smav 857209371Smavstatic void 858141538Sjhblapic_timer_enable_intr(void) 859141538Sjhb{ 860141538Sjhb u_int32_t value; 861141538Sjhb 862141538Sjhb value = lapic->lvt_timer; 863141538Sjhb value &= ~APIC_LVT_M; 864141538Sjhb lapic->lvt_timer = value; 865141538Sjhb} 866141538Sjhb 867205851Sjhbvoid 868208507Sjhblapic_handle_cmc(void) 869208507Sjhb{ 870208507Sjhb 871208507Sjhb lapic_eoi(); 872208507Sjhb cmc_intr(); 873208507Sjhb} 874208507Sjhb 875208507Sjhb/* 876208507Sjhb * Called from the mca_init() to activate the CMC interrupt if this CPU is 877208507Sjhb * responsible for monitoring any MC banks for CMC events. Since mca_init() 878208507Sjhb * is called prior to lapic_setup() during boot, this just needs to unmask 879208507Sjhb * this CPU's LVT_CMCI entry. 880208507Sjhb */ 881208507Sjhbvoid 882208507Sjhblapic_enable_cmc(void) 883208507Sjhb{ 884208507Sjhb u_int apic_id; 885208507Sjhb 886208507Sjhb apic_id = PCPU_GET(apic_id); 887208507Sjhb KASSERT(lapics[apic_id].la_present, 888208507Sjhb ("%s: missing APIC %u", __func__, apic_id)); 889208507Sjhb lapics[apic_id].la_lvts[LVT_CMCI].lvt_masked = 0; 890208507Sjhb lapics[apic_id].la_lvts[LVT_CMCI].lvt_active = 1; 891208507Sjhb if (bootverbose) 892208507Sjhb printf("lapic%u: CMCI unmasked\n", apic_id); 893208507Sjhb} 894208507Sjhb 895208507Sjhbvoid 896205851Sjhblapic_handle_error(void) 897205851Sjhb{ 898205851Sjhb u_int32_t esr; 899205851Sjhb 900205851Sjhb /* 901205851Sjhb * Read the contents of the error status register. Write to 902205851Sjhb * the register first before reading from it to force the APIC 903205851Sjhb * to update its value to indicate any errors that have 904205851Sjhb * occurred since the previous write to the register. 905205851Sjhb */ 906205851Sjhb lapic->esr = 0; 907205851Sjhb esr = lapic->esr; 908205851Sjhb 909205851Sjhb printf("CPU%d: local APIC error 0x%x\n", PCPU_GET(cpuid), esr); 910205851Sjhb lapic_eoi(); 911205851Sjhb} 912205851Sjhb 913187880Sjeffu_int 914187880Sjeffapic_cpuid(u_int apic_id) 915187880Sjeff{ 916187880Sjeff#ifdef SMP 917187880Sjeff return apic_cpuids[apic_id]; 918187880Sjeff#else 919187880Sjeff return 0; 920187880Sjeff#endif 921187880Sjeff} 922187880Sjeff 923151979Sjhb/* Request a free IDT vector to be used by the specified IRQ. */ 924121986Sjhbu_int 925187880Sjeffapic_alloc_vector(u_int apic_id, u_int irq) 926121986Sjhb{ 927121986Sjhb u_int vector; 928121986Sjhb 929121986Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 930151979Sjhb 931151979Sjhb /* 932151979Sjhb * Search for a free vector. Currently we just use a very simple 933151979Sjhb * algorithm to find the first free vector. 934151979Sjhb */ 935151979Sjhb mtx_lock_spin(&icu_lock); 936151979Sjhb for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 937191720Smav if (lapics[apic_id].la_ioint_irqs[vector] != -1) 938151979Sjhb continue; 939187880Sjeff lapics[apic_id].la_ioint_irqs[vector] = irq; 940151979Sjhb mtx_unlock_spin(&icu_lock); 941151979Sjhb return (vector + APIC_IO_INTS); 942151979Sjhb } 943151979Sjhb mtx_unlock_spin(&icu_lock); 944195249Sjhb return (0); 945121986Sjhb} 946121986Sjhb 947164265Sjhb/* 948164265Sjhb * Request 'count' free contiguous IDT vectors to be used by 'count' 949164265Sjhb * IRQs. 'count' must be a power of two and the vectors will be 950164265Sjhb * aligned on a boundary of 'align'. If the request cannot be 951164265Sjhb * satisfied, 0 is returned. 952164265Sjhb */ 953164265Sjhbu_int 954187880Sjeffapic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, u_int align) 955164265Sjhb{ 956164265Sjhb u_int first, run, vector; 957164265Sjhb 958164265Sjhb KASSERT(powerof2(count), ("bad count")); 959164265Sjhb KASSERT(powerof2(align), ("bad align")); 960164265Sjhb KASSERT(align >= count, ("align < count")); 961164265Sjhb#ifdef INVARIANTS 962164265Sjhb for (run = 0; run < count; run++) 963164265Sjhb KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 964164265Sjhb irqs[run], run)); 965164265Sjhb#endif 966164265Sjhb 967164265Sjhb /* 968164265Sjhb * Search for 'count' free vectors. As with apic_alloc_vector(), 969164265Sjhb * this just uses a simple first fit algorithm. 970164265Sjhb */ 971164265Sjhb run = 0; 972164265Sjhb first = 0; 973164265Sjhb mtx_lock_spin(&icu_lock); 974164265Sjhb for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 975164265Sjhb 976164265Sjhb /* Vector is in use, end run. */ 977191720Smav if (lapics[apic_id].la_ioint_irqs[vector] != -1) { 978164265Sjhb run = 0; 979164265Sjhb first = 0; 980164265Sjhb continue; 981164265Sjhb } 982164265Sjhb 983164265Sjhb /* Start a new run if run == 0 and vector is aligned. */ 984164265Sjhb if (run == 0) { 985164265Sjhb if ((vector & (align - 1)) != 0) 986164265Sjhb continue; 987164265Sjhb first = vector; 988164265Sjhb } 989164265Sjhb run++; 990164265Sjhb 991164265Sjhb /* Keep looping if the run isn't long enough yet. */ 992164265Sjhb if (run < count) 993164265Sjhb continue; 994164265Sjhb 995164265Sjhb /* Found a run, assign IRQs and return the first vector. */ 996164265Sjhb for (vector = 0; vector < count; vector++) 997187880Sjeff lapics[apic_id].la_ioint_irqs[first + vector] = 998187880Sjeff irqs[vector]; 999164265Sjhb mtx_unlock_spin(&icu_lock); 1000164265Sjhb return (first + APIC_IO_INTS); 1001164265Sjhb } 1002164265Sjhb mtx_unlock_spin(&icu_lock); 1003164265Sjhb printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 1004164265Sjhb return (0); 1005164265Sjhb} 1006164265Sjhb 1007187880Sjeff/* 1008187880Sjeff * Enable a vector for a particular apic_id. Since all lapics share idt 1009187880Sjeff * entries and ioint_handlers this enables the vector on all lapics. lapics 1010187880Sjeff * which do not have the vector configured would report spurious interrupts 1011187880Sjeff * should it fire. 1012187880Sjeff */ 1013151979Sjhbvoid 1014187880Sjeffapic_enable_vector(u_int apic_id, u_int vector) 1015151979Sjhb{ 1016151979Sjhb 1017151979Sjhb KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 1018151979Sjhb KASSERT(ioint_handlers[vector / 32] != NULL, 1019151979Sjhb ("No ISR handler for vector %u", vector)); 1020208452Smav setidt(vector, ioint_handlers[vector / 32], SDT_APIC, SEL_KPL, 1021208452Smav GSEL_APIC); 1022151979Sjhb} 1023151979Sjhb 1024169391Sjhbvoid 1025187880Sjeffapic_disable_vector(u_int apic_id, u_int vector) 1026169391Sjhb{ 1027169391Sjhb 1028169391Sjhb KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 1029169391Sjhb KASSERT(ioint_handlers[vector / 32] != NULL, 1030169391Sjhb ("No ISR handler for vector %u", vector)); 1031188904Sjeff#ifdef notyet 1032188904Sjeff /* 1033188904Sjeff * We can not currently clear the idt entry because other cpus 1034188904Sjeff * may have a valid vector at this offset. 1035188904Sjeff */ 1036208452Smav setidt(vector, &IDTVEC(rsvd), SDT_APICT, SEL_KPL, GSEL_APIC); 1037188904Sjeff#endif 1038169391Sjhb} 1039169391Sjhb 1040151979Sjhb/* Release an APIC vector when it's no longer in use. */ 1041151979Sjhbvoid 1042187880Sjeffapic_free_vector(u_int apic_id, u_int vector, u_int irq) 1043151979Sjhb{ 1044187880Sjeff struct thread *td; 1045194889Sjhb 1046151979Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1047151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1048151979Sjhb ("Vector %u does not map to an IRQ line", vector)); 1049151979Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 1050187880Sjeff KASSERT(lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] == 1051187880Sjeff irq, ("IRQ mismatch")); 1052187880Sjeff 1053187880Sjeff /* 1054187880Sjeff * Bind us to the cpu that owned the vector before freeing it so 1055187880Sjeff * we don't lose an interrupt delivery race. 1056187880Sjeff */ 1057187880Sjeff td = curthread; 1058196745Sjhb if (!rebooting) { 1059196745Sjhb thread_lock(td); 1060196745Sjhb if (sched_is_bound(td)) 1061196745Sjhb panic("apic_free_vector: Thread already bound.\n"); 1062196745Sjhb sched_bind(td, apic_cpuid(apic_id)); 1063196745Sjhb thread_unlock(td); 1064196745Sjhb } 1065151979Sjhb mtx_lock_spin(&icu_lock); 1066191720Smav lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS] = -1; 1067151979Sjhb mtx_unlock_spin(&icu_lock); 1068196745Sjhb if (!rebooting) { 1069196745Sjhb thread_lock(td); 1070196745Sjhb sched_unbind(td); 1071196745Sjhb thread_unlock(td); 1072196745Sjhb } 1073151979Sjhb} 1074151979Sjhb 1075151979Sjhb/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 1076121986Sjhbu_int 1077187880Sjeffapic_idt_to_irq(u_int apic_id, u_int vector) 1078121986Sjhb{ 1079191730Smav int irq; 1080121986Sjhb 1081122690Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 1082151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 1083121986Sjhb ("Vector %u does not map to an IRQ line", vector)); 1084191730Smav irq = lapics[apic_id].la_ioint_irqs[vector - APIC_IO_INTS]; 1085191730Smav if (irq < 0) 1086191730Smav irq = 0; 1087191730Smav return (irq); 1088121986Sjhb} 1089121986Sjhb 1090151979Sjhb#ifdef DDB 1091121986Sjhb/* 1092151979Sjhb * Dump data about APIC IDT vector mappings. 1093151979Sjhb */ 1094151979SjhbDB_SHOW_COMMAND(apic, db_show_apic) 1095151979Sjhb{ 1096151979Sjhb struct intsrc *isrc; 1097160312Sjhb int i, verbose; 1098187880Sjeff u_int apic_id; 1099151979Sjhb u_int irq; 1100151979Sjhb 1101151979Sjhb if (strcmp(modif, "vv") == 0) 1102151979Sjhb verbose = 2; 1103151979Sjhb else if (strcmp(modif, "v") == 0) 1104151979Sjhb verbose = 1; 1105151979Sjhb else 1106151979Sjhb verbose = 0; 1107187880Sjeff for (apic_id = 0; apic_id <= MAX_APIC_ID; apic_id++) { 1108187880Sjeff if (lapics[apic_id].la_present == 0) 1109187880Sjeff continue; 1110187880Sjeff db_printf("Interrupts bound to lapic %u\n", apic_id); 1111187880Sjeff for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 1112187880Sjeff irq = lapics[apic_id].la_ioint_irqs[i]; 1113191720Smav if (irq == -1 || irq == IRQ_SYSCALL) 1114187880Sjeff continue; 1115151979Sjhb db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 1116151979Sjhb if (irq == IRQ_TIMER) 1117151979Sjhb db_printf("lapic timer\n"); 1118151979Sjhb else if (irq < NUM_IO_INTS) { 1119151979Sjhb isrc = intr_lookup_source(irq); 1120151979Sjhb if (isrc == NULL || verbose == 0) 1121151979Sjhb db_printf("IRQ %u\n", irq); 1122151979Sjhb else 1123151979Sjhb db_dump_intr_event(isrc->is_event, 1124151979Sjhb verbose == 2); 1125151979Sjhb } else 1126151979Sjhb db_printf("IRQ %u ???\n", irq); 1127151979Sjhb } 1128151979Sjhb } 1129151979Sjhb} 1130162233Sjhb 1131162233Sjhbstatic void 1132162233Sjhbdump_mask(const char *prefix, uint32_t v, int base) 1133162233Sjhb{ 1134162233Sjhb int i, first; 1135162233Sjhb 1136162233Sjhb first = 1; 1137162233Sjhb for (i = 0; i < 32; i++) 1138162233Sjhb if (v & (1 << i)) { 1139162233Sjhb if (first) { 1140162233Sjhb db_printf("%s:", prefix); 1141162233Sjhb first = 0; 1142162233Sjhb } 1143162233Sjhb db_printf(" %02x", base + i); 1144162233Sjhb } 1145162233Sjhb if (!first) 1146162233Sjhb db_printf("\n"); 1147162233Sjhb} 1148162233Sjhb 1149162233Sjhb/* Show info from the lapic regs for this CPU. */ 1150162233SjhbDB_SHOW_COMMAND(lapic, db_show_lapic) 1151162233Sjhb{ 1152162233Sjhb uint32_t v; 1153162233Sjhb 1154162233Sjhb db_printf("lapic ID = %d\n", lapic_id()); 1155162233Sjhb v = lapic->version; 1156162233Sjhb db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 1157162233Sjhb v & 0xf); 1158162233Sjhb db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 1159162233Sjhb v = lapic->svr; 1160162233Sjhb db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 1161162233Sjhb v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 1162162233Sjhb db_printf("TPR = %02x\n", lapic->tpr); 1163162233Sjhb 1164162233Sjhb#define dump_field(prefix, index) \ 1165162233Sjhb dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 1166162233Sjhb index * 32) 1167162233Sjhb 1168162233Sjhb db_printf("In-service Interrupts:\n"); 1169162233Sjhb dump_field(isr, 0); 1170162233Sjhb dump_field(isr, 1); 1171162233Sjhb dump_field(isr, 2); 1172162233Sjhb dump_field(isr, 3); 1173162233Sjhb dump_field(isr, 4); 1174162233Sjhb dump_field(isr, 5); 1175162233Sjhb dump_field(isr, 6); 1176162233Sjhb dump_field(isr, 7); 1177162233Sjhb 1178162233Sjhb db_printf("TMR Interrupts:\n"); 1179162233Sjhb dump_field(tmr, 0); 1180162233Sjhb dump_field(tmr, 1); 1181162233Sjhb dump_field(tmr, 2); 1182162233Sjhb dump_field(tmr, 3); 1183162233Sjhb dump_field(tmr, 4); 1184162233Sjhb dump_field(tmr, 5); 1185162233Sjhb dump_field(tmr, 6); 1186162233Sjhb dump_field(tmr, 7); 1187162233Sjhb 1188162233Sjhb db_printf("IRR Interrupts:\n"); 1189162233Sjhb dump_field(irr, 0); 1190162233Sjhb dump_field(irr, 1); 1191162233Sjhb dump_field(irr, 2); 1192162233Sjhb dump_field(irr, 3); 1193162233Sjhb dump_field(irr, 4); 1194162233Sjhb dump_field(irr, 5); 1195162233Sjhb dump_field(irr, 6); 1196162233Sjhb dump_field(irr, 7); 1197162233Sjhb 1198162233Sjhb#undef dump_field 1199162233Sjhb} 1200151979Sjhb#endif 1201151979Sjhb 1202151979Sjhb/* 1203121986Sjhb * APIC probing support code. This includes code to manage enumerators. 1204121986Sjhb */ 1205121986Sjhb 1206121986Sjhbstatic SLIST_HEAD(, apic_enumerator) enumerators = 1207121986Sjhb SLIST_HEAD_INITIALIZER(enumerators); 1208121986Sjhbstatic struct apic_enumerator *best_enum; 1209195249Sjhb 1210121986Sjhbvoid 1211121986Sjhbapic_register_enumerator(struct apic_enumerator *enumerator) 1212121986Sjhb{ 1213121986Sjhb#ifdef INVARIANTS 1214121986Sjhb struct apic_enumerator *apic_enum; 1215121986Sjhb 1216121986Sjhb SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1217121986Sjhb if (apic_enum == enumerator) 1218121986Sjhb panic("%s: Duplicate register of %s", __func__, 1219121986Sjhb enumerator->apic_name); 1220121986Sjhb } 1221121986Sjhb#endif 1222121986Sjhb SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1223121986Sjhb} 1224121986Sjhb 1225121986Sjhb/* 1226208479Smav * We have to look for CPU's very, very early because certain subsystems 1227208479Smav * want to know how many CPU's we have extremely early on in the boot 1228208479Smav * process. 1229121986Sjhb */ 1230121986Sjhbstatic void 1231121986Sjhbapic_init(void *dummy __unused) 1232121986Sjhb{ 1233121986Sjhb struct apic_enumerator *enumerator; 1234208452Smav#ifndef __amd64__ 1235123133Sjhb uint64_t apic_base; 1236208452Smav#endif 1237121986Sjhb int retval, best; 1238121986Sjhb 1239153383Sjhb /* We only support built in local APICs. */ 1240153383Sjhb if (!(cpu_feature & CPUID_APIC)) 1241121986Sjhb return; 1242121986Sjhb 1243123133Sjhb /* Don't probe if APIC mode is disabled. */ 1244123133Sjhb if (resource_disabled("apic", 0)) 1245123133Sjhb return; 1246123133Sjhb 1247121986Sjhb /* First, probe all the enumerators to find the best match. */ 1248121986Sjhb best_enum = NULL; 1249121986Sjhb best = 0; 1250121986Sjhb SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1251121986Sjhb retval = enumerator->apic_probe(); 1252121986Sjhb if (retval > 0) 1253121986Sjhb continue; 1254121986Sjhb if (best_enum == NULL || best < retval) { 1255121986Sjhb best_enum = enumerator; 1256121986Sjhb best = retval; 1257121986Sjhb } 1258121986Sjhb } 1259121986Sjhb if (best_enum == NULL) { 1260121986Sjhb if (bootverbose) 1261121986Sjhb printf("APIC: Could not find any APICs.\n"); 1262121986Sjhb return; 1263121986Sjhb } 1264121986Sjhb 1265121986Sjhb if (bootverbose) 1266121986Sjhb printf("APIC: Using the %s enumerator.\n", 1267121986Sjhb best_enum->apic_name); 1268121986Sjhb 1269208452Smav#ifndef __amd64__ 1270121986Sjhb /* 1271121986Sjhb * To work around an errata, we disable the local APIC on some 1272121986Sjhb * CPUs during early startup. We need to turn the local APIC back 1273121986Sjhb * on on such CPUs now. 1274121986Sjhb */ 1275185341Sjkim if (cpu == CPU_686 && cpu_vendor_id == CPU_VENDOR_INTEL && 1276121986Sjhb (cpu_id & 0xff0) == 0x610) { 1277121986Sjhb apic_base = rdmsr(MSR_APICBASE); 1278121986Sjhb apic_base |= APICBASE_ENABLED; 1279121986Sjhb wrmsr(MSR_APICBASE, apic_base); 1280121986Sjhb } 1281208452Smav#endif 1282123133Sjhb 1283123133Sjhb /* Second, probe the CPU's in the system. */ 1284123133Sjhb retval = best_enum->apic_probe_cpus(); 1285123133Sjhb if (retval != 0) 1286123133Sjhb printf("%s: Failed to probe CPUs: returned %d\n", 1287123133Sjhb best_enum->apic_name, retval); 1288123133Sjhb 1289208479Smav#ifdef __amd64__ 1290208479Smav} 1291208479SmavSYSINIT(apic_init, SI_SUB_TUNABLES - 1, SI_ORDER_SECOND, apic_init, NULL); 1292208479Smav 1293208479Smav/* 1294208479Smav * Setup the local APIC. We have to do this prior to starting up the APs 1295208479Smav * in the SMP case. 1296208479Smav */ 1297208479Smavstatic void 1298208479Smavapic_setup_local(void *dummy __unused) 1299208479Smav{ 1300208479Smav int retval; 1301208479Smav 1302208479Smav if (best_enum == NULL) 1303208479Smav return; 1304208479Smav#endif 1305123133Sjhb /* Third, initialize the local APIC. */ 1306121986Sjhb retval = best_enum->apic_setup_local(); 1307121986Sjhb if (retval != 0) 1308121986Sjhb printf("%s: Failed to setup the local APIC: returned %d\n", 1309121986Sjhb best_enum->apic_name, retval); 1310121986Sjhb} 1311208479Smav#ifdef __amd64__ 1312208479SmavSYSINIT(apic_setup_local, SI_SUB_CPU, SI_ORDER_SECOND, apic_setup_local, 1313208479Smav NULL); 1314208479Smav#else 1315177253SrwatsonSYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_SECOND, apic_init, NULL); 1316208479Smav#endif 1317121986Sjhb 1318121986Sjhb/* 1319121986Sjhb * Setup the I/O APICs. 1320121986Sjhb */ 1321121986Sjhbstatic void 1322121986Sjhbapic_setup_io(void *dummy __unused) 1323121986Sjhb{ 1324121986Sjhb int retval; 1325121986Sjhb 1326121986Sjhb if (best_enum == NULL) 1327121986Sjhb return; 1328121986Sjhb retval = best_enum->apic_setup_io(); 1329121986Sjhb if (retval != 0) 1330121986Sjhb printf("%s: Failed to setup I/O APICs: returned %d\n", 1331121986Sjhb best_enum->apic_name, retval); 1332121986Sjhb 1333182902Skmacy#ifdef XEN 1334182902Skmacy return; 1335182902Skmacy#endif 1336121986Sjhb /* 1337121986Sjhb * Finish setting up the local APIC on the BSP once we know how to 1338121986Sjhb * properly program the LINT pins. 1339121986Sjhb */ 1340163219Sjhb lapic_setup(1); 1341163219Sjhb intr_register_pic(&lapic_pic); 1342121986Sjhb if (bootverbose) 1343121986Sjhb lapic_dump("BSP"); 1344164265Sjhb 1345164265Sjhb /* Enable the MSI "pic". */ 1346164265Sjhb msi_init(); 1347121986Sjhb} 1348177253SrwatsonSYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL); 1349121986Sjhb 1350121986Sjhb#ifdef SMP 1351121986Sjhb/* 1352121986Sjhb * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1353208452Smav * private to the MD code. The public interface for the rest of the 1354121986Sjhb * kernel is defined in mp_machdep.c. 1355121986Sjhb */ 1356121986Sjhbint 1357121986Sjhblapic_ipi_wait(int delay) 1358121986Sjhb{ 1359121986Sjhb int x, incr; 1360121986Sjhb 1361121986Sjhb /* 1362121986Sjhb * Wait delay loops for IPI to be sent. This is highly bogus 1363121986Sjhb * since this is sensitive to CPU clock speed. If delay is 1364121986Sjhb * -1, we wait forever. 1365121986Sjhb */ 1366121986Sjhb if (delay == -1) { 1367121986Sjhb incr = 0; 1368121986Sjhb delay = 1; 1369121986Sjhb } else 1370121986Sjhb incr = 1; 1371121986Sjhb for (x = 0; x < delay; x += incr) { 1372121986Sjhb if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1373121986Sjhb return (1); 1374121986Sjhb ia32_pause(); 1375121986Sjhb } 1376121986Sjhb return (0); 1377121986Sjhb} 1378121986Sjhb 1379121986Sjhbvoid 1380121986Sjhblapic_ipi_raw(register_t icrlo, u_int dest) 1381121986Sjhb{ 1382121986Sjhb register_t value, eflags; 1383121986Sjhb 1384121986Sjhb /* XXX: Need more sanity checking of icrlo? */ 1385121986Sjhb KASSERT(lapic != NULL, ("%s called too early", __func__)); 1386121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1387121986Sjhb ("%s: invalid dest field", __func__)); 1388121986Sjhb KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1389121986Sjhb ("%s: reserved bits set in ICR LO register", __func__)); 1390121986Sjhb 1391121986Sjhb /* Set destination in ICR HI register if it is being used. */ 1392121986Sjhb eflags = intr_disable(); 1393121986Sjhb if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1394121986Sjhb value = lapic->icr_hi; 1395121986Sjhb value &= ~APIC_ID_MASK; 1396121986Sjhb value |= dest << APIC_ID_SHIFT; 1397121986Sjhb lapic->icr_hi = value; 1398121986Sjhb } 1399121986Sjhb 1400121986Sjhb /* Program the contents of the IPI and dispatch it. */ 1401121986Sjhb value = lapic->icr_lo; 1402121986Sjhb value &= APIC_ICRLO_RESV_MASK; 1403121986Sjhb value |= icrlo; 1404121986Sjhb lapic->icr_lo = value; 1405121986Sjhb intr_restore(eflags); 1406121986Sjhb} 1407121986Sjhb 1408125317Sjeff#define BEFORE_SPIN 1000000 1409121986Sjhb#ifdef DETECT_DEADLOCK 1410121986Sjhb#define AFTER_SPIN 1000 1411121986Sjhb#endif 1412121986Sjhb 1413121986Sjhbvoid 1414121986Sjhblapic_ipi_vectored(u_int vector, int dest) 1415121986Sjhb{ 1416121986Sjhb register_t icrlo, destfield; 1417121986Sjhb 1418121986Sjhb KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1419121986Sjhb ("%s: invalid vector %d", __func__, vector)); 1420121986Sjhb 1421196196Sattilio icrlo = APIC_DESTMODE_PHY | APIC_TRIGMOD_EDGE; 1422196196Sattilio 1423196196Sattilio /* 1424196196Sattilio * IPI_STOP_HARD is just a "fake" vector used to send a NMI. 1425196196Sattilio * Use special rules regard NMI if passed, otherwise specify 1426196196Sattilio * the vector. 1427196196Sattilio */ 1428196196Sattilio if (vector == IPI_STOP_HARD) 1429196196Sattilio icrlo |= APIC_DELMODE_NMI | APIC_LEVEL_ASSERT; 1430196196Sattilio else 1431196196Sattilio icrlo |= vector | APIC_DELMODE_FIXED | APIC_LEVEL_DEASSERT; 1432121986Sjhb destfield = 0; 1433121986Sjhb switch (dest) { 1434121986Sjhb case APIC_IPI_DEST_SELF: 1435121986Sjhb icrlo |= APIC_DEST_SELF; 1436121986Sjhb break; 1437121986Sjhb case APIC_IPI_DEST_ALL: 1438121986Sjhb icrlo |= APIC_DEST_ALLISELF; 1439121986Sjhb break; 1440121986Sjhb case APIC_IPI_DEST_OTHERS: 1441121986Sjhb icrlo |= APIC_DEST_ALLESELF; 1442121986Sjhb break; 1443121986Sjhb default: 1444121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1445121986Sjhb ("%s: invalid destination 0x%x", __func__, dest)); 1446121986Sjhb destfield = dest; 1447121986Sjhb } 1448121986Sjhb 1449125317Sjeff /* Wait for an earlier IPI to finish. */ 1450150176Sjhb if (!lapic_ipi_wait(BEFORE_SPIN)) { 1451150176Sjhb if (panicstr != NULL) 1452150176Sjhb return; 1453150176Sjhb else 1454150176Sjhb panic("APIC: Previous IPI is stuck"); 1455150176Sjhb } 1456121986Sjhb 1457121986Sjhb lapic_ipi_raw(icrlo, destfield); 1458121986Sjhb 1459121986Sjhb#ifdef DETECT_DEADLOCK 1460121986Sjhb /* Wait for IPI to be delivered. */ 1461121986Sjhb if (!lapic_ipi_wait(AFTER_SPIN)) { 1462121986Sjhb#ifdef needsattention 1463121986Sjhb /* 1464121986Sjhb * XXX FIXME: 1465121986Sjhb * 1466121986Sjhb * The above function waits for the message to actually be 1467121986Sjhb * delivered. It breaks out after an arbitrary timeout 1468121986Sjhb * since the message should eventually be delivered (at 1469121986Sjhb * least in theory) and that if it wasn't we would catch 1470121986Sjhb * the failure with the check above when the next IPI is 1471121986Sjhb * sent. 1472121986Sjhb * 1473139240Sjhb * We could skip this wait entirely, EXCEPT it probably 1474121986Sjhb * protects us from other routines that assume that the 1475121986Sjhb * message was delivered and acted upon when this function 1476121986Sjhb * returns. 1477121986Sjhb */ 1478121986Sjhb printf("APIC: IPI might be stuck\n"); 1479121986Sjhb#else /* !needsattention */ 1480121986Sjhb /* Wait until mesage is sent without a timeout. */ 1481121986Sjhb while (lapic->icr_lo & APIC_DELSTAT_PEND) 1482121986Sjhb ia32_pause(); 1483121986Sjhb#endif /* needsattention */ 1484121986Sjhb } 1485121986Sjhb#endif /* DETECT_DEADLOCK */ 1486121986Sjhb} 1487121986Sjhb#endif /* SMP */ 1488