local_apic.c revision 169391
1121986Sjhb/*- 2121986Sjhb * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3121986Sjhb * Copyright (c) 1996, by Steve Passe 4121986Sjhb * All rights reserved. 5121986Sjhb * 6121986Sjhb * Redistribution and use in source and binary forms, with or without 7121986Sjhb * modification, are permitted provided that the following conditions 8121986Sjhb * are met: 9121986Sjhb * 1. Redistributions of source code must retain the above copyright 10121986Sjhb * notice, this list of conditions and the following disclaimer. 11121986Sjhb * 2. The name of the developer may NOT be used to endorse or promote products 12121986Sjhb * derived from this software without specific prior written permission. 13121986Sjhb * 3. Neither the name of the author nor the names of any co-contributors 14121986Sjhb * may be used to endorse or promote products derived from this software 15121986Sjhb * without specific prior written permission. 16121986Sjhb * 17121986Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18121986Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19121986Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20121986Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21121986Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22121986Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23121986Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24121986Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25121986Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26121986Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27121986Sjhb * SUCH DAMAGE. 28121986Sjhb */ 29121986Sjhb 30121986Sjhb/* 31121986Sjhb * Local APIC support on Pentium and later processors. 32121986Sjhb */ 33121986Sjhb 34121986Sjhb#include <sys/cdefs.h> 35121986Sjhb__FBSDID("$FreeBSD: head/sys/i386/i386/local_apic.c 169391 2007-05-08 21:29:14Z jhb $"); 36121986Sjhb 37147565Speter#include "opt_hwpmc_hooks.h" 38147565Speter 39151979Sjhb#include "opt_ddb.h" 40151979Sjhb 41121986Sjhb#include <sys/param.h> 42121986Sjhb#include <sys/systm.h> 43121986Sjhb#include <sys/bus.h> 44121986Sjhb#include <sys/kernel.h> 45151979Sjhb#include <sys/lock.h> 46151979Sjhb#include <sys/mutex.h> 47121986Sjhb#include <sys/pcpu.h> 48141538Sjhb#include <sys/smp.h> 49121986Sjhb 50121986Sjhb#include <vm/vm.h> 51121986Sjhb#include <vm/pmap.h> 52121986Sjhb 53121986Sjhb#include <machine/apicreg.h> 54153666Sjhb#include <machine/cpu.h> 55121986Sjhb#include <machine/cputypes.h> 56121986Sjhb#include <machine/frame.h> 57121986Sjhb#include <machine/intr_machdep.h> 58121986Sjhb#include <machine/apicvar.h> 59121986Sjhb#include <machine/md_var.h> 60121986Sjhb#include <machine/smp.h> 61121986Sjhb#include <machine/specialreg.h> 62121986Sjhb 63151979Sjhb#ifdef DDB 64151979Sjhb#include <sys/interrupt.h> 65151979Sjhb#include <ddb/ddb.h> 66151979Sjhb#endif 67151979Sjhb 68121986Sjhb/* 69121986Sjhb * We can handle up to 60 APICs via our logical cluster IDs, but currently 70121986Sjhb * the physical IDs on Intel processors up to the Pentium 4 are limited to 71121986Sjhb * 16. 72121986Sjhb */ 73121986Sjhb#define MAX_APICID 16 74121986Sjhb 75122690Sjhb/* Sanity checks on IDT vectors. */ 76139240SjhbCTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 77139240SjhbCTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 78139240SjhbCTASSERT(APIC_LOCAL_INTS == 240); 79122690SjhbCTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 80122690Sjhb 81143034Sjhb#define LAPIC_TIMER_HZ_DIVIDER 2 82143034Sjhb#define LAPIC_TIMER_STATHZ_DIVIDER 15 83143034Sjhb#define LAPIC_TIMER_PROFHZ_DIVIDER 3 84141538Sjhb 85151979Sjhb/* Magic IRQ values for the timer and syscalls. */ 86151979Sjhb#define IRQ_TIMER (NUM_IO_INTS + 1) 87151979Sjhb#define IRQ_SYSCALL (NUM_IO_INTS + 2) 88151979Sjhb 89121986Sjhb/* 90121986Sjhb * Support for local APICs. Local APICs manage interrupts on each 91121986Sjhb * individual processor as opposed to I/O APICs which receive interrupts 92121986Sjhb * from I/O devices and then forward them on to the local APICs. 93121986Sjhb * 94121986Sjhb * Local APICs can also send interrupts to each other thus providing the 95121986Sjhb * mechanism for IPIs. 96121986Sjhb */ 97121986Sjhb 98121986Sjhbstruct lvt { 99121986Sjhb u_int lvt_edgetrigger:1; 100121986Sjhb u_int lvt_activehi:1; 101121986Sjhb u_int lvt_masked:1; 102121986Sjhb u_int lvt_active:1; 103121986Sjhb u_int lvt_mode:16; 104121986Sjhb u_int lvt_vector:8; 105121986Sjhb}; 106121986Sjhb 107121986Sjhbstruct lapic { 108121986Sjhb struct lvt la_lvts[LVT_MAX + 1]; 109121986Sjhb u_int la_id:8; 110121986Sjhb u_int la_cluster:4; 111121986Sjhb u_int la_cluster_id:2; 112121986Sjhb u_int la_present:1; 113141538Sjhb u_long *la_timer_count; 114141538Sjhb u_long la_hard_ticks; 115141538Sjhb u_long la_stat_ticks; 116141538Sjhb u_long la_prof_ticks; 117121986Sjhb} static lapics[MAX_APICID]; 118121986Sjhb 119121986Sjhb/* XXX: should thermal be an NMI? */ 120121986Sjhb 121121986Sjhb/* Global defaults for local APIC LVT entries. */ 122121986Sjhbstatic struct lvt lvts[LVT_MAX + 1] = { 123121986Sjhb { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 124121986Sjhb { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 125139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 126139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 127145256Sjkoshy { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 128139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 129121986Sjhb}; 130121986Sjhb 131121986Sjhbstatic inthand_t *ioint_handlers[] = { 132121986Sjhb NULL, /* 0 - 31 */ 133121986Sjhb IDTVEC(apic_isr1), /* 32 - 63 */ 134121986Sjhb IDTVEC(apic_isr2), /* 64 - 95 */ 135121986Sjhb IDTVEC(apic_isr3), /* 96 - 127 */ 136121986Sjhb IDTVEC(apic_isr4), /* 128 - 159 */ 137121986Sjhb IDTVEC(apic_isr5), /* 160 - 191 */ 138122690Sjhb IDTVEC(apic_isr6), /* 192 - 223 */ 139122690Sjhb IDTVEC(apic_isr7), /* 224 - 255 */ 140121986Sjhb}; 141121986Sjhb 142151979Sjhb/* Include IDT_SYSCALL to make indexing easier. */ 143151979Sjhbstatic u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 144151979Sjhb 145141538Sjhbstatic u_int32_t lapic_timer_divisors[] = { 146141538Sjhb APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 147141538Sjhb APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 148141538Sjhb}; 149141538Sjhb 150169391Sjhbextern inthand_t IDTVEC(rsvd); 151169391Sjhb 152121986Sjhbvolatile lapic_t *lapic; 153167747Sjhbvm_paddr_t lapic_paddr; 154141538Sjhbstatic u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 155121986Sjhb 156139245Sjhbstatic void lapic_enable(void); 157163219Sjhbstatic void lapic_resume(struct pic *pic); 158141538Sjhbstatic void lapic_timer_enable_intr(void); 159141538Sjhbstatic void lapic_timer_oneshot(u_int count); 160141538Sjhbstatic void lapic_timer_periodic(u_int count); 161141538Sjhbstatic void lapic_timer_set_divisor(u_int divisor); 162139245Sjhbstatic uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 163139245Sjhb 164163219Sjhbstruct pic lapic_pic = { .pic_resume = lapic_resume }; 165163219Sjhb 166121986Sjhbstatic uint32_t 167121986Sjhblvt_mode(struct lapic *la, u_int pin, uint32_t value) 168121986Sjhb{ 169121986Sjhb struct lvt *lvt; 170121986Sjhb 171121986Sjhb KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 172121986Sjhb if (la->la_lvts[pin].lvt_active) 173121986Sjhb lvt = &la->la_lvts[pin]; 174121986Sjhb else 175121986Sjhb lvt = &lvts[pin]; 176121986Sjhb 177121986Sjhb value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 178121986Sjhb APIC_LVT_VECTOR); 179121986Sjhb if (lvt->lvt_edgetrigger == 0) 180121986Sjhb value |= APIC_LVT_TM; 181121986Sjhb if (lvt->lvt_activehi == 0) 182121986Sjhb value |= APIC_LVT_IIPP_INTALO; 183121986Sjhb if (lvt->lvt_masked) 184121986Sjhb value |= APIC_LVT_M; 185121986Sjhb value |= lvt->lvt_mode; 186121986Sjhb switch (lvt->lvt_mode) { 187121986Sjhb case APIC_LVT_DM_NMI: 188121986Sjhb case APIC_LVT_DM_SMI: 189121986Sjhb case APIC_LVT_DM_INIT: 190121986Sjhb case APIC_LVT_DM_EXTINT: 191121986Sjhb if (!lvt->lvt_edgetrigger) { 192121986Sjhb printf("lapic%u: Forcing LINT%u to edge trigger\n", 193121986Sjhb la->la_id, pin); 194121986Sjhb value |= APIC_LVT_TM; 195121986Sjhb } 196121986Sjhb /* Use a vector of 0. */ 197121986Sjhb break; 198121986Sjhb case APIC_LVT_DM_FIXED: 199121986Sjhb value |= lvt->lvt_vector; 200121986Sjhb break; 201121986Sjhb default: 202121986Sjhb panic("bad APIC LVT delivery mode: %#x\n", value); 203121986Sjhb } 204121986Sjhb return (value); 205121986Sjhb} 206121986Sjhb 207121986Sjhb/* 208121986Sjhb * Map the local APIC and setup necessary interrupt vectors. 209121986Sjhb */ 210121986Sjhbvoid 211167247Sjhblapic_init(vm_paddr_t addr) 212121986Sjhb{ 213121986Sjhb 214121986Sjhb /* Map the local APIC and setup the spurious interrupt handler. */ 215121986Sjhb KASSERT(trunc_page(addr) == addr, 216121986Sjhb ("local APIC not aligned on a page boundary")); 217156920Sjhb lapic = pmap_mapdev(addr, sizeof(lapic_t)); 218167747Sjhb lapic_paddr = addr; 219121986Sjhb setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 220121986Sjhb GSEL(GCODE_SEL, SEL_KPL)); 221121986Sjhb 222121986Sjhb /* Perform basic initialization of the BSP's local APIC. */ 223139245Sjhb lapic_enable(); 224151979Sjhb ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 225121986Sjhb 226121986Sjhb /* Set BSP's per-CPU local APIC ID. */ 227121986Sjhb PCPU_SET(apic_id, lapic_id()); 228121986Sjhb 229141538Sjhb /* Local APIC timer interrupt. */ 230141538Sjhb setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 231141538Sjhb GSEL(GCODE_SEL, SEL_KPL)); 232151979Sjhb ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 233141538Sjhb 234141538Sjhb /* XXX: error/thermal interrupts */ 235121986Sjhb} 236121986Sjhb 237121986Sjhb/* 238121986Sjhb * Create a local APIC instance. 239121986Sjhb */ 240121986Sjhbvoid 241121986Sjhblapic_create(u_int apic_id, int boot_cpu) 242121986Sjhb{ 243121986Sjhb int i; 244121986Sjhb 245132156Sjhb if (apic_id >= MAX_APICID) { 246121986Sjhb printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 247121986Sjhb if (boot_cpu) 248121986Sjhb panic("Can't ignore BSP"); 249121986Sjhb return; 250121986Sjhb } 251121986Sjhb KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 252121986Sjhb apic_id)); 253121986Sjhb 254121986Sjhb /* 255121986Sjhb * Assume no local LVT overrides and a cluster of 0 and 256121986Sjhb * intra-cluster ID of 0. 257121986Sjhb */ 258121986Sjhb lapics[apic_id].la_present = 1; 259121986Sjhb lapics[apic_id].la_id = apic_id; 260121986Sjhb for (i = 0; i < LVT_MAX; i++) { 261121986Sjhb lapics[apic_id].la_lvts[i] = lvts[i]; 262121986Sjhb lapics[apic_id].la_lvts[i].lvt_active = 0; 263121986Sjhb } 264121986Sjhb 265121986Sjhb#ifdef SMP 266121986Sjhb cpu_add(apic_id, boot_cpu); 267121986Sjhb#endif 268121986Sjhb} 269121986Sjhb 270121986Sjhb/* 271121986Sjhb * Dump contents of local APIC registers 272121986Sjhb */ 273121986Sjhbvoid 274121986Sjhblapic_dump(const char* str) 275121986Sjhb{ 276121986Sjhb 277121986Sjhb printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 278121986Sjhb printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 279121986Sjhb lapic->id, lapic->version, lapic->ldr, lapic->dfr); 280121986Sjhb printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 281121986Sjhb lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 282139245Sjhb printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 283139245Sjhb lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 284139245Sjhb lapic->lvt_pcint); 285121986Sjhb} 286121986Sjhb 287121986Sjhbvoid 288163219Sjhblapic_setup(int boot) 289121986Sjhb{ 290121986Sjhb struct lapic *la; 291156124Sjhb u_int32_t maxlvt; 292121986Sjhb register_t eflags; 293141538Sjhb char buf[MAXCOMLEN + 1]; 294121986Sjhb 295121986Sjhb la = &lapics[lapic_id()]; 296121986Sjhb KASSERT(la->la_present, ("missing APIC structure")); 297121986Sjhb eflags = intr_disable(); 298121986Sjhb maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 299121986Sjhb 300139240Sjhb /* Initialize the TPR to allow all interrupts. */ 301139240Sjhb lapic_set_tpr(0); 302121986Sjhb 303121986Sjhb /* Setup spurious vector and enable the local APIC. */ 304139245Sjhb lapic_enable(); 305139245Sjhb 306139245Sjhb /* Program LINT[01] LVT entries. */ 307139245Sjhb lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 308139245Sjhb lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 309145256Sjkoshy#ifdef HWPMC_HOOKS 310145256Sjkoshy /* Program the PMC LVT entry if present. */ 311145256Sjkoshy if (maxlvt >= LVT_PMC) 312145256Sjkoshy lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 313145256Sjkoshy#endif 314139245Sjhb 315141538Sjhb /* Program timer LVT and setup handler. */ 316141538Sjhb lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 317163219Sjhb if (boot) { 318163219Sjhb snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 319163219Sjhb intrcnt_add(buf, &la->la_timer_count); 320163219Sjhb } 321163219Sjhb 322163219Sjhb /* We don't setup the timer during boot on the BSP until later. */ 323163219Sjhb if (!(boot && PCPU_GET(cpuid) == 0)) { 324141538Sjhb KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 325141538Sjhb lapic_id())); 326141538Sjhb lapic_timer_set_divisor(lapic_timer_divisor); 327141538Sjhb lapic_timer_periodic(lapic_timer_period); 328141538Sjhb lapic_timer_enable_intr(); 329141538Sjhb } 330139245Sjhb 331150176Sjhb /* XXX: Error and thermal LVTs */ 332141538Sjhb 333169042Sariff if (strcmp(cpu_vendor, "AuthenticAMD") == 0) { 334169042Sariff /* 335169042Sariff * Detect the presence of C1E capability mostly on latest 336169042Sariff * dual-cores (or future) k8 family. This feature renders 337169042Sariff * the local APIC timer dead, so we disable it by reading 338169042Sariff * the Interrupt Pending Message register and clearing both 339169042Sariff * C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27). 340169042Sariff * 341169042Sariff * Reference: 342169042Sariff * "BIOS and Kernel Developer's Guide for AMD NPT 343169042Sariff * Family 0Fh Processors" 344169042Sariff * #32559 revision 3.00 345169042Sariff */ 346169042Sariff if ((cpu_id & 0x00000f00) == 0x00000f00 && 347169042Sariff (cpu_id & 0x0fff0000) >= 0x00040000) { 348169042Sariff uint64_t msr; 349169042Sariff 350169042Sariff msr = rdmsr(0xc0010055); 351169042Sariff if (msr & 0x18000000) 352169042Sariff wrmsr(0xc0010055, msr & ~0x18000000ULL); 353169042Sariff } 354169042Sariff } 355169042Sariff 356121986Sjhb intr_restore(eflags); 357121986Sjhb} 358121986Sjhb 359141538Sjhb/* 360141538Sjhb * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 361141538Sjhb * that it can drive hardclock, statclock, and profclock. This function 362141538Sjhb * returns true if it is able to use the local APIC timer to drive the 363141538Sjhb * clocks and false if it is not able. 364141538Sjhb */ 365141538Sjhbint 366141538Sjhblapic_setup_clock(void) 367141538Sjhb{ 368141538Sjhb u_long value; 369141538Sjhb 370141538Sjhb /* Can't drive the timer without a local APIC. */ 371141538Sjhb if (lapic == NULL) 372141538Sjhb return (0); 373141538Sjhb 374141538Sjhb /* Start off with a divisor of 2 (power on reset default). */ 375141538Sjhb lapic_timer_divisor = 2; 376141538Sjhb 377141538Sjhb /* Try to calibrate the local APIC timer. */ 378141538Sjhb do { 379141538Sjhb lapic_timer_set_divisor(lapic_timer_divisor); 380141538Sjhb lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 381141538Sjhb DELAY(2000000); 382141538Sjhb value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 383141538Sjhb if (value != APIC_TIMER_MAX_COUNT) 384141538Sjhb break; 385141538Sjhb lapic_timer_divisor <<= 1; 386141538Sjhb } while (lapic_timer_divisor <= 128); 387141538Sjhb if (lapic_timer_divisor > 128) 388141538Sjhb panic("lapic: Divisor too big"); 389141538Sjhb value /= 2; 390141538Sjhb if (bootverbose) 391141538Sjhb printf("lapic: Divisor %lu, Frequency %lu hz\n", 392141538Sjhb lapic_timer_divisor, value); 393141538Sjhb 394141538Sjhb /* 395141538Sjhb * We will drive the timer at a small multiple of hz and drive 396141538Sjhb * both of the other timers with similarly small but relatively 397141538Sjhb * prime divisors. 398141538Sjhb */ 399141538Sjhb lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 400141538Sjhb stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 401141538Sjhb profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 402141538Sjhb lapic_timer_period = value / lapic_timer_hz; 403141538Sjhb 404141538Sjhb /* 405141538Sjhb * Start up the timer on the BSP. The APs will kick off their 406141538Sjhb * timer during lapic_setup(). 407141538Sjhb */ 408141538Sjhb lapic_timer_periodic(lapic_timer_period); 409141538Sjhb lapic_timer_enable_intr(); 410141538Sjhb return (1); 411141538Sjhb} 412141538Sjhb 413121986Sjhbvoid 414121986Sjhblapic_disable(void) 415121986Sjhb{ 416121986Sjhb uint32_t value; 417121986Sjhb 418121986Sjhb /* Software disable the local APIC. */ 419121986Sjhb value = lapic->svr; 420121986Sjhb value &= ~APIC_SVR_SWEN; 421121986Sjhb lapic->svr = value; 422121986Sjhb} 423121986Sjhb 424139245Sjhbstatic void 425139245Sjhblapic_enable(void) 426139245Sjhb{ 427139245Sjhb u_int32_t value; 428139245Sjhb 429139245Sjhb /* Program the spurious vector to enable the local APIC. */ 430139245Sjhb value = lapic->svr; 431139245Sjhb value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 432139245Sjhb value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 433139245Sjhb lapic->svr = value; 434139245Sjhb} 435139245Sjhb 436163219Sjhb/* Reset the local APIC on the BSP during resume. */ 437163219Sjhbstatic void 438163219Sjhblapic_resume(struct pic *pic) 439163219Sjhb{ 440163219Sjhb 441163219Sjhb lapic_setup(0); 442163219Sjhb} 443163219Sjhb 444121986Sjhbint 445121986Sjhblapic_id(void) 446121986Sjhb{ 447121986Sjhb 448121986Sjhb KASSERT(lapic != NULL, ("local APIC is not mapped")); 449121986Sjhb return (lapic->id >> APIC_ID_SHIFT); 450121986Sjhb} 451121986Sjhb 452121986Sjhbint 453121986Sjhblapic_intr_pending(u_int vector) 454121986Sjhb{ 455121986Sjhb volatile u_int32_t *irr; 456121986Sjhb 457121986Sjhb /* 458121986Sjhb * The IRR registers are an array of 128-bit registers each of 459121986Sjhb * which only describes 32 interrupts in the low 32 bits.. Thus, 460121986Sjhb * we divide the vector by 32 to get the 128-bit index. We then 461121986Sjhb * multiply that index by 4 to get the equivalent index from 462121986Sjhb * treating the IRR as an array of 32-bit registers. Finally, we 463121986Sjhb * modulus the vector by 32 to determine the individual bit to 464121986Sjhb * test. 465121986Sjhb */ 466121986Sjhb irr = &lapic->irr0; 467121986Sjhb return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 468121986Sjhb} 469121986Sjhb 470121986Sjhbvoid 471121986Sjhblapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 472121986Sjhb{ 473121986Sjhb struct lapic *la; 474121986Sjhb 475121986Sjhb KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 476121986Sjhb __func__, apic_id)); 477121986Sjhb KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 478121986Sjhb __func__, cluster)); 479121986Sjhb KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 480121986Sjhb ("%s: intra cluster id %u too big", __func__, cluster_id)); 481121986Sjhb la = &lapics[apic_id]; 482121986Sjhb la->la_cluster = cluster; 483121986Sjhb la->la_cluster_id = cluster_id; 484121986Sjhb} 485121986Sjhb 486121986Sjhbint 487121986Sjhblapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 488121986Sjhb{ 489121986Sjhb 490121986Sjhb if (pin > LVT_MAX) 491121986Sjhb return (EINVAL); 492121986Sjhb if (apic_id == APIC_ID_ALL) { 493121986Sjhb lvts[pin].lvt_masked = masked; 494121986Sjhb if (bootverbose) 495121986Sjhb printf("lapic:"); 496121986Sjhb } else { 497121986Sjhb KASSERT(lapics[apic_id].la_present, 498121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 499121986Sjhb lapics[apic_id].la_lvts[pin].lvt_masked = masked; 500121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 501121986Sjhb if (bootverbose) 502121986Sjhb printf("lapic%u:", apic_id); 503121986Sjhb } 504121986Sjhb if (bootverbose) 505121986Sjhb printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 506121986Sjhb return (0); 507121986Sjhb} 508121986Sjhb 509121986Sjhbint 510121986Sjhblapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 511121986Sjhb{ 512121986Sjhb struct lvt *lvt; 513121986Sjhb 514121986Sjhb if (pin > LVT_MAX) 515121986Sjhb return (EINVAL); 516121986Sjhb if (apic_id == APIC_ID_ALL) { 517121986Sjhb lvt = &lvts[pin]; 518121986Sjhb if (bootverbose) 519121986Sjhb printf("lapic:"); 520121986Sjhb } else { 521121986Sjhb KASSERT(lapics[apic_id].la_present, 522121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 523121986Sjhb lvt = &lapics[apic_id].la_lvts[pin]; 524121986Sjhb lvt->lvt_active = 1; 525121986Sjhb if (bootverbose) 526121986Sjhb printf("lapic%u:", apic_id); 527121986Sjhb } 528121986Sjhb lvt->lvt_mode = mode; 529121986Sjhb switch (mode) { 530121986Sjhb case APIC_LVT_DM_NMI: 531121986Sjhb case APIC_LVT_DM_SMI: 532121986Sjhb case APIC_LVT_DM_INIT: 533121986Sjhb case APIC_LVT_DM_EXTINT: 534121986Sjhb lvt->lvt_edgetrigger = 1; 535121986Sjhb lvt->lvt_activehi = 1; 536121986Sjhb if (mode == APIC_LVT_DM_EXTINT) 537121986Sjhb lvt->lvt_masked = 1; 538121986Sjhb else 539121986Sjhb lvt->lvt_masked = 0; 540121986Sjhb break; 541121986Sjhb default: 542121986Sjhb panic("Unsupported delivery mode: 0x%x\n", mode); 543121986Sjhb } 544121986Sjhb if (bootverbose) { 545121986Sjhb printf(" Routing "); 546121986Sjhb switch (mode) { 547121986Sjhb case APIC_LVT_DM_NMI: 548121986Sjhb printf("NMI"); 549121986Sjhb break; 550121986Sjhb case APIC_LVT_DM_SMI: 551121986Sjhb printf("SMI"); 552121986Sjhb break; 553121986Sjhb case APIC_LVT_DM_INIT: 554121986Sjhb printf("INIT"); 555121986Sjhb break; 556121986Sjhb case APIC_LVT_DM_EXTINT: 557121986Sjhb printf("ExtINT"); 558121986Sjhb break; 559121986Sjhb } 560121986Sjhb printf(" -> LINT%u\n", pin); 561121986Sjhb } 562121986Sjhb return (0); 563121986Sjhb} 564121986Sjhb 565121986Sjhbint 566128930Sjhblapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 567121986Sjhb{ 568121986Sjhb 569128930Sjhb if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 570121986Sjhb return (EINVAL); 571121986Sjhb if (apic_id == APIC_ID_ALL) { 572128930Sjhb lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 573121986Sjhb if (bootverbose) 574121986Sjhb printf("lapic:"); 575121986Sjhb } else { 576121986Sjhb KASSERT(lapics[apic_id].la_present, 577121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 578121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 579128930Sjhb lapics[apic_id].la_lvts[pin].lvt_activehi = 580128930Sjhb (pol == INTR_POLARITY_HIGH); 581121986Sjhb if (bootverbose) 582121986Sjhb printf("lapic%u:", apic_id); 583121986Sjhb } 584121986Sjhb if (bootverbose) 585140254Sjhb printf(" LINT%u polarity: %s\n", pin, 586128930Sjhb pol == INTR_POLARITY_HIGH ? "high" : "low"); 587121986Sjhb return (0); 588121986Sjhb} 589121986Sjhb 590121986Sjhbint 591128930Sjhblapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 592121986Sjhb{ 593121986Sjhb 594128930Sjhb if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 595121986Sjhb return (EINVAL); 596121986Sjhb if (apic_id == APIC_ID_ALL) { 597128930Sjhb lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 598121986Sjhb if (bootverbose) 599121986Sjhb printf("lapic:"); 600121986Sjhb } else { 601121986Sjhb KASSERT(lapics[apic_id].la_present, 602121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 603128930Sjhb lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 604128930Sjhb (trigger == INTR_TRIGGER_EDGE); 605121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 606121986Sjhb if (bootverbose) 607121986Sjhb printf("lapic%u:", apic_id); 608121986Sjhb } 609121986Sjhb if (bootverbose) 610121986Sjhb printf(" LINT%u trigger: %s\n", pin, 611128930Sjhb trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 612121986Sjhb return (0); 613121986Sjhb} 614121986Sjhb 615139240Sjhb/* 616139240Sjhb * Adjust the TPR of the current CPU so that it blocks all interrupts below 617139240Sjhb * the passed in vector. 618139240Sjhb */ 619121986Sjhbvoid 620139240Sjhblapic_set_tpr(u_int vector) 621139240Sjhb{ 622139240Sjhb#ifdef CHEAP_TPR 623139240Sjhb lapic->tpr = vector; 624139240Sjhb#else 625139240Sjhb u_int32_t tpr; 626139240Sjhb 627139240Sjhb tpr = lapic->tpr & ~APIC_TPR_PRIO; 628139240Sjhb tpr |= vector; 629139240Sjhb lapic->tpr = tpr; 630139240Sjhb#endif 631139240Sjhb} 632139240Sjhb 633139240Sjhbvoid 634122572Sjhblapic_eoi(void) 635122572Sjhb{ 636122572Sjhb 637122572Sjhb lapic->eoi = 0; 638122572Sjhb} 639122572Sjhb 640122572Sjhbvoid 641165302Skmacylapic_handle_intr(int vector, struct trapframe *frame) 642121986Sjhb{ 643121986Sjhb struct intsrc *isrc; 644121986Sjhb 645153146Sjhb if (vector == -1) 646121986Sjhb panic("Couldn't get vector from ISR!"); 647153146Sjhb isrc = intr_lookup_source(apic_idt_to_irq(vector)); 648165302Skmacy intr_execute_handlers(isrc, frame); 649121986Sjhb} 650121986Sjhb 651141538Sjhbvoid 652165302Skmacylapic_handle_timer(struct trapframe *frame) 653141538Sjhb{ 654141538Sjhb struct lapic *la; 655141538Sjhb 656153141Sjhb /* Send EOI first thing. */ 657153141Sjhb lapic_eoi(); 658153141Sjhb 659162708Ssobomax#if defined(SMP) && !defined(SCHED_ULE) 660162042Ssobomax /* 661162042Ssobomax * Don't do any accounting for the disabled HTT cores, since it 662162042Ssobomax * will provide misleading numbers for the userland. 663162042Ssobomax * 664162042Ssobomax * No locking is necessary here, since even if we loose the race 665162042Ssobomax * when hlt_cpus_mask changes it is not a big deal, really. 666162713Ssobomax * 667162713Ssobomax * Don't do that for ULE, since ULE doesn't consider hlt_cpus_mask 668162713Ssobomax * and unlike other schedulers it actually schedules threads to 669162713Ssobomax * those CPUs. 670162042Ssobomax */ 671162042Ssobomax if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 672162042Ssobomax return; 673162087Ssobomax#endif 674162042Ssobomax 675153141Sjhb /* Look up our local APIC structure for the tick counters. */ 676141538Sjhb la = &lapics[PCPU_GET(apic_id)]; 677141538Sjhb (*la->la_timer_count)++; 678141538Sjhb critical_enter(); 679141538Sjhb 680141538Sjhb /* Fire hardclock at hz. */ 681141538Sjhb la->la_hard_ticks += hz; 682141538Sjhb if (la->la_hard_ticks >= lapic_timer_hz) { 683141538Sjhb la->la_hard_ticks -= lapic_timer_hz; 684143034Sjhb if (PCPU_GET(cpuid) == 0) 685165302Skmacy hardclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 686143034Sjhb else 687165302Skmacy hardclock_cpu(TRAPF_USERMODE(frame)); 688141538Sjhb } 689141538Sjhb 690141538Sjhb /* Fire statclock at stathz. */ 691141538Sjhb la->la_stat_ticks += stathz; 692141538Sjhb if (la->la_stat_ticks >= lapic_timer_hz) { 693141538Sjhb la->la_stat_ticks -= lapic_timer_hz; 694165302Skmacy statclock(TRAPF_USERMODE(frame)); 695141538Sjhb } 696141538Sjhb 697141538Sjhb /* Fire profclock at profhz, but only when needed. */ 698141538Sjhb la->la_prof_ticks += profhz; 699141538Sjhb if (la->la_prof_ticks >= lapic_timer_hz) { 700141538Sjhb la->la_prof_ticks -= lapic_timer_hz; 701141538Sjhb if (profprocs != 0) 702165302Skmacy profclock(TRAPF_USERMODE(frame), TRAPF_PC(frame)); 703141538Sjhb } 704141538Sjhb critical_exit(); 705141538Sjhb} 706141538Sjhb 707141538Sjhbstatic void 708141538Sjhblapic_timer_set_divisor(u_int divisor) 709141538Sjhb{ 710141538Sjhb 711141538Sjhb KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 712141538Sjhb KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 713141538Sjhb sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 714141538Sjhb lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 715141538Sjhb} 716141538Sjhb 717141538Sjhbstatic void 718141538Sjhblapic_timer_oneshot(u_int count) 719141538Sjhb{ 720141538Sjhb u_int32_t value; 721141538Sjhb 722141538Sjhb value = lapic->lvt_timer; 723141538Sjhb value &= ~APIC_LVTT_TM; 724141538Sjhb value |= APIC_LVTT_TM_ONE_SHOT; 725141538Sjhb lapic->lvt_timer = value; 726141538Sjhb lapic->icr_timer = count; 727141538Sjhb} 728141538Sjhb 729141538Sjhbstatic void 730141538Sjhblapic_timer_periodic(u_int count) 731141538Sjhb{ 732141538Sjhb u_int32_t value; 733141538Sjhb 734141538Sjhb value = lapic->lvt_timer; 735141538Sjhb value &= ~APIC_LVTT_TM; 736141538Sjhb value |= APIC_LVTT_TM_PERIODIC; 737141538Sjhb lapic->lvt_timer = value; 738141538Sjhb lapic->icr_timer = count; 739141538Sjhb} 740141538Sjhb 741141538Sjhbstatic void 742141538Sjhblapic_timer_enable_intr(void) 743141538Sjhb{ 744141538Sjhb u_int32_t value; 745141538Sjhb 746141538Sjhb value = lapic->lvt_timer; 747141538Sjhb value &= ~APIC_LVT_M; 748141538Sjhb lapic->lvt_timer = value; 749141538Sjhb} 750141538Sjhb 751151979Sjhb/* Request a free IDT vector to be used by the specified IRQ. */ 752121986Sjhbu_int 753151979Sjhbapic_alloc_vector(u_int irq) 754121986Sjhb{ 755121986Sjhb u_int vector; 756121986Sjhb 757121986Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 758151979Sjhb 759151979Sjhb /* 760151979Sjhb * Search for a free vector. Currently we just use a very simple 761151979Sjhb * algorithm to find the first free vector. 762151979Sjhb */ 763151979Sjhb mtx_lock_spin(&icu_lock); 764151979Sjhb for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 765151979Sjhb if (ioint_irqs[vector] != 0) 766151979Sjhb continue; 767151979Sjhb ioint_irqs[vector] = irq; 768151979Sjhb mtx_unlock_spin(&icu_lock); 769151979Sjhb return (vector + APIC_IO_INTS); 770151979Sjhb } 771151979Sjhb mtx_unlock_spin(&icu_lock); 772151979Sjhb panic("Couldn't find an APIC vector for IRQ %u", irq); 773121986Sjhb} 774121986Sjhb 775164265Sjhb/* 776164265Sjhb * Request 'count' free contiguous IDT vectors to be used by 'count' 777164265Sjhb * IRQs. 'count' must be a power of two and the vectors will be 778164265Sjhb * aligned on a boundary of 'align'. If the request cannot be 779164265Sjhb * satisfied, 0 is returned. 780164265Sjhb */ 781164265Sjhbu_int 782164265Sjhbapic_alloc_vectors(u_int *irqs, u_int count, u_int align) 783164265Sjhb{ 784164265Sjhb u_int first, run, vector; 785164265Sjhb 786164265Sjhb KASSERT(powerof2(count), ("bad count")); 787164265Sjhb KASSERT(powerof2(align), ("bad align")); 788164265Sjhb KASSERT(align >= count, ("align < count")); 789164265Sjhb#ifdef INVARIANTS 790164265Sjhb for (run = 0; run < count; run++) 791164265Sjhb KASSERT(irqs[run] < NUM_IO_INTS, ("Invalid IRQ %u at index %u", 792164265Sjhb irqs[run], run)); 793164265Sjhb#endif 794164265Sjhb 795164265Sjhb /* 796164265Sjhb * Search for 'count' free vectors. As with apic_alloc_vector(), 797164265Sjhb * this just uses a simple first fit algorithm. 798164265Sjhb */ 799164265Sjhb run = 0; 800164265Sjhb first = 0; 801164265Sjhb mtx_lock_spin(&icu_lock); 802164265Sjhb for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 803164265Sjhb 804164265Sjhb /* Vector is in use, end run. */ 805164265Sjhb if (ioint_irqs[vector] != 0) { 806164265Sjhb run = 0; 807164265Sjhb first = 0; 808164265Sjhb continue; 809164265Sjhb } 810164265Sjhb 811164265Sjhb /* Start a new run if run == 0 and vector is aligned. */ 812164265Sjhb if (run == 0) { 813164265Sjhb if ((vector & (align - 1)) != 0) 814164265Sjhb continue; 815164265Sjhb first = vector; 816164265Sjhb } 817164265Sjhb run++; 818164265Sjhb 819164265Sjhb /* Keep looping if the run isn't long enough yet. */ 820164265Sjhb if (run < count) 821164265Sjhb continue; 822164265Sjhb 823164265Sjhb /* Found a run, assign IRQs and return the first vector. */ 824164265Sjhb for (vector = 0; vector < count; vector++) 825164265Sjhb ioint_irqs[first + vector] = irqs[vector]; 826164265Sjhb mtx_unlock_spin(&icu_lock); 827164265Sjhb return (first + APIC_IO_INTS); 828164265Sjhb } 829164265Sjhb mtx_unlock_spin(&icu_lock); 830164265Sjhb printf("APIC: Couldn't find APIC vectors for %u IRQs\n", count); 831164265Sjhb return (0); 832164265Sjhb} 833164265Sjhb 834151979Sjhbvoid 835151979Sjhbapic_enable_vector(u_int vector) 836151979Sjhb{ 837151979Sjhb 838151979Sjhb KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 839151979Sjhb KASSERT(ioint_handlers[vector / 32] != NULL, 840151979Sjhb ("No ISR handler for vector %u", vector)); 841151979Sjhb setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 842151979Sjhb GSEL(GCODE_SEL, SEL_KPL)); 843151979Sjhb} 844151979Sjhb 845169391Sjhbvoid 846169391Sjhbapic_disable_vector(u_int vector) 847169391Sjhb{ 848169391Sjhb 849169391Sjhb KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 850169391Sjhb KASSERT(ioint_handlers[vector / 32] != NULL, 851169391Sjhb ("No ISR handler for vector %u", vector)); 852169391Sjhb setidt(vector, &IDTVEC(rsvd), SDT_SYS386TGT, SEL_KPL, 853169391Sjhb GSEL(GCODE_SEL, SEL_KPL)); 854169391Sjhb} 855169391Sjhb 856151979Sjhb/* Release an APIC vector when it's no longer in use. */ 857151979Sjhbvoid 858151979Sjhbapic_free_vector(u_int vector, u_int irq) 859151979Sjhb{ 860151979Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 861151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 862151979Sjhb ("Vector %u does not map to an IRQ line", vector)); 863151979Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 864151979Sjhb KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 865151979Sjhb mtx_lock_spin(&icu_lock); 866151979Sjhb ioint_irqs[vector - APIC_IO_INTS] = 0; 867151979Sjhb mtx_unlock_spin(&icu_lock); 868151979Sjhb} 869151979Sjhb 870151979Sjhb/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 871121986Sjhbu_int 872121986Sjhbapic_idt_to_irq(u_int vector) 873121986Sjhb{ 874121986Sjhb 875122690Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 876151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 877121986Sjhb ("Vector %u does not map to an IRQ line", vector)); 878151979Sjhb return (ioint_irqs[vector - APIC_IO_INTS]); 879121986Sjhb} 880121986Sjhb 881151979Sjhb#ifdef DDB 882121986Sjhb/* 883151979Sjhb * Dump data about APIC IDT vector mappings. 884151979Sjhb */ 885151979SjhbDB_SHOW_COMMAND(apic, db_show_apic) 886151979Sjhb{ 887151979Sjhb struct intsrc *isrc; 888160312Sjhb int i, verbose; 889151979Sjhb u_int irq; 890151979Sjhb 891151979Sjhb if (strcmp(modif, "vv") == 0) 892151979Sjhb verbose = 2; 893151979Sjhb else if (strcmp(modif, "v") == 0) 894151979Sjhb verbose = 1; 895151979Sjhb else 896151979Sjhb verbose = 0; 897160312Sjhb for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 898151979Sjhb irq = ioint_irqs[i]; 899151979Sjhb if (irq != 0 && irq != IRQ_SYSCALL) { 900151979Sjhb db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 901151979Sjhb if (irq == IRQ_TIMER) 902151979Sjhb db_printf("lapic timer\n"); 903151979Sjhb else if (irq < NUM_IO_INTS) { 904151979Sjhb isrc = intr_lookup_source(irq); 905151979Sjhb if (isrc == NULL || verbose == 0) 906151979Sjhb db_printf("IRQ %u\n", irq); 907151979Sjhb else 908151979Sjhb db_dump_intr_event(isrc->is_event, 909151979Sjhb verbose == 2); 910151979Sjhb } else 911151979Sjhb db_printf("IRQ %u ???\n", irq); 912151979Sjhb } 913151979Sjhb } 914151979Sjhb} 915162233Sjhb 916162233Sjhbstatic void 917162233Sjhbdump_mask(const char *prefix, uint32_t v, int base) 918162233Sjhb{ 919162233Sjhb int i, first; 920162233Sjhb 921162233Sjhb first = 1; 922162233Sjhb for (i = 0; i < 32; i++) 923162233Sjhb if (v & (1 << i)) { 924162233Sjhb if (first) { 925162233Sjhb db_printf("%s:", prefix); 926162233Sjhb first = 0; 927162233Sjhb } 928162233Sjhb db_printf(" %02x", base + i); 929162233Sjhb } 930162233Sjhb if (!first) 931162233Sjhb db_printf("\n"); 932162233Sjhb} 933162233Sjhb 934162233Sjhb/* Show info from the lapic regs for this CPU. */ 935162233SjhbDB_SHOW_COMMAND(lapic, db_show_lapic) 936162233Sjhb{ 937162233Sjhb uint32_t v; 938162233Sjhb 939162233Sjhb db_printf("lapic ID = %d\n", lapic_id()); 940162233Sjhb v = lapic->version; 941162233Sjhb db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 942162233Sjhb v & 0xf); 943162233Sjhb db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 944162233Sjhb v = lapic->svr; 945162233Sjhb db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 946162233Sjhb v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 947162233Sjhb db_printf("TPR = %02x\n", lapic->tpr); 948162233Sjhb 949162233Sjhb#define dump_field(prefix, index) \ 950162233Sjhb dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 951162233Sjhb index * 32) 952162233Sjhb 953162233Sjhb db_printf("In-service Interrupts:\n"); 954162233Sjhb dump_field(isr, 0); 955162233Sjhb dump_field(isr, 1); 956162233Sjhb dump_field(isr, 2); 957162233Sjhb dump_field(isr, 3); 958162233Sjhb dump_field(isr, 4); 959162233Sjhb dump_field(isr, 5); 960162233Sjhb dump_field(isr, 6); 961162233Sjhb dump_field(isr, 7); 962162233Sjhb 963162233Sjhb db_printf("TMR Interrupts:\n"); 964162233Sjhb dump_field(tmr, 0); 965162233Sjhb dump_field(tmr, 1); 966162233Sjhb dump_field(tmr, 2); 967162233Sjhb dump_field(tmr, 3); 968162233Sjhb dump_field(tmr, 4); 969162233Sjhb dump_field(tmr, 5); 970162233Sjhb dump_field(tmr, 6); 971162233Sjhb dump_field(tmr, 7); 972162233Sjhb 973162233Sjhb db_printf("IRR Interrupts:\n"); 974162233Sjhb dump_field(irr, 0); 975162233Sjhb dump_field(irr, 1); 976162233Sjhb dump_field(irr, 2); 977162233Sjhb dump_field(irr, 3); 978162233Sjhb dump_field(irr, 4); 979162233Sjhb dump_field(irr, 5); 980162233Sjhb dump_field(irr, 6); 981162233Sjhb dump_field(irr, 7); 982162233Sjhb 983162233Sjhb#undef dump_field 984162233Sjhb} 985151979Sjhb#endif 986151979Sjhb 987151979Sjhb/* 988121986Sjhb * APIC probing support code. This includes code to manage enumerators. 989121986Sjhb */ 990121986Sjhb 991121986Sjhbstatic SLIST_HEAD(, apic_enumerator) enumerators = 992121986Sjhb SLIST_HEAD_INITIALIZER(enumerators); 993121986Sjhbstatic struct apic_enumerator *best_enum; 994121986Sjhb 995121986Sjhbvoid 996121986Sjhbapic_register_enumerator(struct apic_enumerator *enumerator) 997121986Sjhb{ 998121986Sjhb#ifdef INVARIANTS 999121986Sjhb struct apic_enumerator *apic_enum; 1000121986Sjhb 1001121986Sjhb SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 1002121986Sjhb if (apic_enum == enumerator) 1003121986Sjhb panic("%s: Duplicate register of %s", __func__, 1004121986Sjhb enumerator->apic_name); 1005121986Sjhb } 1006121986Sjhb#endif 1007121986Sjhb SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 1008121986Sjhb} 1009121986Sjhb 1010121986Sjhb/* 1011123133Sjhb * Probe the APIC enumerators, enumerate CPUs, and initialize the 1012123133Sjhb * local APIC. 1013121986Sjhb */ 1014121986Sjhbstatic void 1015121986Sjhbapic_init(void *dummy __unused) 1016121986Sjhb{ 1017121986Sjhb struct apic_enumerator *enumerator; 1018123133Sjhb uint64_t apic_base; 1019121986Sjhb int retval, best; 1020121986Sjhb 1021153383Sjhb /* We only support built in local APICs. */ 1022153383Sjhb if (!(cpu_feature & CPUID_APIC)) 1023121986Sjhb return; 1024121986Sjhb 1025123133Sjhb /* Don't probe if APIC mode is disabled. */ 1026123133Sjhb if (resource_disabled("apic", 0)) 1027123133Sjhb return; 1028123133Sjhb 1029121986Sjhb /* First, probe all the enumerators to find the best match. */ 1030121986Sjhb best_enum = NULL; 1031121986Sjhb best = 0; 1032121986Sjhb SLIST_FOREACH(enumerator, &enumerators, apic_next) { 1033121986Sjhb retval = enumerator->apic_probe(); 1034121986Sjhb if (retval > 0) 1035121986Sjhb continue; 1036121986Sjhb if (best_enum == NULL || best < retval) { 1037121986Sjhb best_enum = enumerator; 1038121986Sjhb best = retval; 1039121986Sjhb } 1040121986Sjhb } 1041121986Sjhb if (best_enum == NULL) { 1042121986Sjhb if (bootverbose) 1043121986Sjhb printf("APIC: Could not find any APICs.\n"); 1044121986Sjhb return; 1045121986Sjhb } 1046121986Sjhb 1047121986Sjhb if (bootverbose) 1048121986Sjhb printf("APIC: Using the %s enumerator.\n", 1049121986Sjhb best_enum->apic_name); 1050121986Sjhb 1051121986Sjhb /* 1052121986Sjhb * To work around an errata, we disable the local APIC on some 1053121986Sjhb * CPUs during early startup. We need to turn the local APIC back 1054121986Sjhb * on on such CPUs now. 1055121986Sjhb */ 1056121986Sjhb if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && 1057121986Sjhb (cpu_id & 0xff0) == 0x610) { 1058121986Sjhb apic_base = rdmsr(MSR_APICBASE); 1059121986Sjhb apic_base |= APICBASE_ENABLED; 1060121986Sjhb wrmsr(MSR_APICBASE, apic_base); 1061121986Sjhb } 1062123133Sjhb 1063123133Sjhb /* Second, probe the CPU's in the system. */ 1064123133Sjhb retval = best_enum->apic_probe_cpus(); 1065123133Sjhb if (retval != 0) 1066123133Sjhb printf("%s: Failed to probe CPUs: returned %d\n", 1067123133Sjhb best_enum->apic_name, retval); 1068123133Sjhb 1069123133Sjhb /* Third, initialize the local APIC. */ 1070121986Sjhb retval = best_enum->apic_setup_local(); 1071121986Sjhb if (retval != 0) 1072121986Sjhb printf("%s: Failed to setup the local APIC: returned %d\n", 1073121986Sjhb best_enum->apic_name, retval); 1074123432Sjeff#ifdef SMP 1075123432Sjeff /* Last, setup the cpu topology now that we have probed CPUs */ 1076123432Sjeff mp_topology(); 1077123432Sjeff#endif 1078121986Sjhb} 1079123133SjhbSYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL) 1080121986Sjhb 1081121986Sjhb/* 1082121986Sjhb * Setup the I/O APICs. 1083121986Sjhb */ 1084121986Sjhbstatic void 1085121986Sjhbapic_setup_io(void *dummy __unused) 1086121986Sjhb{ 1087121986Sjhb int retval; 1088121986Sjhb 1089121986Sjhb if (best_enum == NULL) 1090121986Sjhb return; 1091121986Sjhb retval = best_enum->apic_setup_io(); 1092121986Sjhb if (retval != 0) 1093121986Sjhb printf("%s: Failed to setup I/O APICs: returned %d\n", 1094121986Sjhb best_enum->apic_name, retval); 1095121986Sjhb 1096121986Sjhb /* 1097121986Sjhb * Finish setting up the local APIC on the BSP once we know how to 1098121986Sjhb * properly program the LINT pins. 1099121986Sjhb */ 1100163219Sjhb lapic_setup(1); 1101163219Sjhb intr_register_pic(&lapic_pic); 1102121986Sjhb if (bootverbose) 1103121986Sjhb lapic_dump("BSP"); 1104164265Sjhb 1105164265Sjhb /* Enable the MSI "pic". */ 1106164265Sjhb msi_init(); 1107121986Sjhb} 1108121986SjhbSYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 1109121986Sjhb 1110121986Sjhb#ifdef SMP 1111121986Sjhb/* 1112121986Sjhb * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 1113139240Sjhb * private to the sys/i386 code. The public interface for the rest of the 1114121986Sjhb * kernel is defined in mp_machdep.c. 1115121986Sjhb */ 1116121986Sjhbint 1117121986Sjhblapic_ipi_wait(int delay) 1118121986Sjhb{ 1119121986Sjhb int x, incr; 1120121986Sjhb 1121121986Sjhb /* 1122121986Sjhb * Wait delay loops for IPI to be sent. This is highly bogus 1123121986Sjhb * since this is sensitive to CPU clock speed. If delay is 1124121986Sjhb * -1, we wait forever. 1125121986Sjhb */ 1126121986Sjhb if (delay == -1) { 1127121986Sjhb incr = 0; 1128121986Sjhb delay = 1; 1129121986Sjhb } else 1130121986Sjhb incr = 1; 1131121986Sjhb for (x = 0; x < delay; x += incr) { 1132121986Sjhb if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1133121986Sjhb return (1); 1134121986Sjhb ia32_pause(); 1135121986Sjhb } 1136121986Sjhb return (0); 1137121986Sjhb} 1138121986Sjhb 1139121986Sjhbvoid 1140121986Sjhblapic_ipi_raw(register_t icrlo, u_int dest) 1141121986Sjhb{ 1142121986Sjhb register_t value, eflags; 1143121986Sjhb 1144121986Sjhb /* XXX: Need more sanity checking of icrlo? */ 1145121986Sjhb KASSERT(lapic != NULL, ("%s called too early", __func__)); 1146121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1147121986Sjhb ("%s: invalid dest field", __func__)); 1148121986Sjhb KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1149121986Sjhb ("%s: reserved bits set in ICR LO register", __func__)); 1150121986Sjhb 1151121986Sjhb /* Set destination in ICR HI register if it is being used. */ 1152121986Sjhb eflags = intr_disable(); 1153121986Sjhb if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1154121986Sjhb value = lapic->icr_hi; 1155121986Sjhb value &= ~APIC_ID_MASK; 1156121986Sjhb value |= dest << APIC_ID_SHIFT; 1157121986Sjhb lapic->icr_hi = value; 1158121986Sjhb } 1159121986Sjhb 1160121986Sjhb /* Program the contents of the IPI and dispatch it. */ 1161121986Sjhb value = lapic->icr_lo; 1162121986Sjhb value &= APIC_ICRLO_RESV_MASK; 1163121986Sjhb value |= icrlo; 1164121986Sjhb lapic->icr_lo = value; 1165121986Sjhb intr_restore(eflags); 1166121986Sjhb} 1167121986Sjhb 1168125317Sjeff#define BEFORE_SPIN 1000000 1169121986Sjhb#ifdef DETECT_DEADLOCK 1170121986Sjhb#define AFTER_SPIN 1000 1171121986Sjhb#endif 1172121986Sjhb 1173121986Sjhbvoid 1174121986Sjhblapic_ipi_vectored(u_int vector, int dest) 1175121986Sjhb{ 1176121986Sjhb register_t icrlo, destfield; 1177121986Sjhb 1178121986Sjhb KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1179121986Sjhb ("%s: invalid vector %d", __func__, vector)); 1180121986Sjhb 1181121986Sjhb icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1182121986Sjhb APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1183121986Sjhb destfield = 0; 1184121986Sjhb switch (dest) { 1185121986Sjhb case APIC_IPI_DEST_SELF: 1186121986Sjhb icrlo |= APIC_DEST_SELF; 1187121986Sjhb break; 1188121986Sjhb case APIC_IPI_DEST_ALL: 1189121986Sjhb icrlo |= APIC_DEST_ALLISELF; 1190121986Sjhb break; 1191121986Sjhb case APIC_IPI_DEST_OTHERS: 1192121986Sjhb icrlo |= APIC_DEST_ALLESELF; 1193121986Sjhb break; 1194121986Sjhb default: 1195121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1196121986Sjhb ("%s: invalid destination 0x%x", __func__, dest)); 1197121986Sjhb destfield = dest; 1198121986Sjhb } 1199121986Sjhb 1200125317Sjeff /* Wait for an earlier IPI to finish. */ 1201150176Sjhb if (!lapic_ipi_wait(BEFORE_SPIN)) { 1202150176Sjhb if (panicstr != NULL) 1203150176Sjhb return; 1204150176Sjhb else 1205150176Sjhb panic("APIC: Previous IPI is stuck"); 1206150176Sjhb } 1207121986Sjhb 1208121986Sjhb lapic_ipi_raw(icrlo, destfield); 1209121986Sjhb 1210121986Sjhb#ifdef DETECT_DEADLOCK 1211121986Sjhb /* Wait for IPI to be delivered. */ 1212121986Sjhb if (!lapic_ipi_wait(AFTER_SPIN)) { 1213121986Sjhb#ifdef needsattention 1214121986Sjhb /* 1215121986Sjhb * XXX FIXME: 1216121986Sjhb * 1217121986Sjhb * The above function waits for the message to actually be 1218121986Sjhb * delivered. It breaks out after an arbitrary timeout 1219121986Sjhb * since the message should eventually be delivered (at 1220121986Sjhb * least in theory) and that if it wasn't we would catch 1221121986Sjhb * the failure with the check above when the next IPI is 1222121986Sjhb * sent. 1223121986Sjhb * 1224139240Sjhb * We could skip this wait entirely, EXCEPT it probably 1225121986Sjhb * protects us from other routines that assume that the 1226121986Sjhb * message was delivered and acted upon when this function 1227121986Sjhb * returns. 1228121986Sjhb */ 1229121986Sjhb printf("APIC: IPI might be stuck\n"); 1230121986Sjhb#else /* !needsattention */ 1231121986Sjhb /* Wait until mesage is sent without a timeout. */ 1232121986Sjhb while (lapic->icr_lo & APIC_DELSTAT_PEND) 1233121986Sjhb ia32_pause(); 1234121986Sjhb#endif /* needsattention */ 1235121986Sjhb } 1236121986Sjhb#endif /* DETECT_DEADLOCK */ 1237121986Sjhb} 1238121986Sjhb#endif /* SMP */ 1239