local_apic.c revision 162708
1121986Sjhb/*- 2121986Sjhb * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3121986Sjhb * Copyright (c) 1996, by Steve Passe 4121986Sjhb * All rights reserved. 5121986Sjhb * 6121986Sjhb * Redistribution and use in source and binary forms, with or without 7121986Sjhb * modification, are permitted provided that the following conditions 8121986Sjhb * are met: 9121986Sjhb * 1. Redistributions of source code must retain the above copyright 10121986Sjhb * notice, this list of conditions and the following disclaimer. 11121986Sjhb * 2. The name of the developer may NOT be used to endorse or promote products 12121986Sjhb * derived from this software without specific prior written permission. 13121986Sjhb * 3. Neither the name of the author nor the names of any co-contributors 14121986Sjhb * may be used to endorse or promote products derived from this software 15121986Sjhb * without specific prior written permission. 16121986Sjhb * 17121986Sjhb * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 18121986Sjhb * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 19121986Sjhb * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 20121986Sjhb * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 21121986Sjhb * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 22121986Sjhb * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 23121986Sjhb * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 24121986Sjhb * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 25121986Sjhb * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 26121986Sjhb * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 27121986Sjhb * SUCH DAMAGE. 28121986Sjhb */ 29121986Sjhb 30121986Sjhb/* 31121986Sjhb * Local APIC support on Pentium and later processors. 32121986Sjhb */ 33121986Sjhb 34121986Sjhb#include <sys/cdefs.h> 35121986Sjhb__FBSDID("$FreeBSD: head/sys/i386/i386/local_apic.c 162708 2006-09-27 18:51:19Z sobomax $"); 36121986Sjhb 37147565Speter#include "opt_hwpmc_hooks.h" 38147565Speter 39151979Sjhb#include "opt_ddb.h" 40151979Sjhb 41121986Sjhb#include <sys/param.h> 42121986Sjhb#include <sys/systm.h> 43121986Sjhb#include <sys/bus.h> 44121986Sjhb#include <sys/kernel.h> 45151979Sjhb#include <sys/lock.h> 46151979Sjhb#include <sys/mutex.h> 47121986Sjhb#include <sys/pcpu.h> 48141538Sjhb#include <sys/smp.h> 49121986Sjhb 50121986Sjhb#include <vm/vm.h> 51121986Sjhb#include <vm/pmap.h> 52121986Sjhb 53121986Sjhb#include <machine/apicreg.h> 54153666Sjhb#include <machine/cpu.h> 55121986Sjhb#include <machine/cputypes.h> 56121986Sjhb#include <machine/frame.h> 57121986Sjhb#include <machine/intr_machdep.h> 58121986Sjhb#include <machine/apicvar.h> 59121986Sjhb#include <machine/md_var.h> 60121986Sjhb#include <machine/smp.h> 61121986Sjhb#include <machine/specialreg.h> 62121986Sjhb 63151979Sjhb#ifdef DDB 64151979Sjhb#include <sys/interrupt.h> 65151979Sjhb#include <ddb/ddb.h> 66151979Sjhb#endif 67151979Sjhb 68121986Sjhb/* 69121986Sjhb * We can handle up to 60 APICs via our logical cluster IDs, but currently 70121986Sjhb * the physical IDs on Intel processors up to the Pentium 4 are limited to 71121986Sjhb * 16. 72121986Sjhb */ 73121986Sjhb#define MAX_APICID 16 74121986Sjhb 75122690Sjhb/* Sanity checks on IDT vectors. */ 76139240SjhbCTASSERT(APIC_IO_INTS + APIC_NUM_IOINTS == APIC_TIMER_INT); 77139240SjhbCTASSERT(APIC_TIMER_INT < APIC_LOCAL_INTS); 78139240SjhbCTASSERT(APIC_LOCAL_INTS == 240); 79122690SjhbCTASSERT(IPI_STOP < APIC_SPURIOUS_INT); 80122690Sjhb 81143034Sjhb#define LAPIC_TIMER_HZ_DIVIDER 2 82143034Sjhb#define LAPIC_TIMER_STATHZ_DIVIDER 15 83143034Sjhb#define LAPIC_TIMER_PROFHZ_DIVIDER 3 84141538Sjhb 85151979Sjhb/* Magic IRQ values for the timer and syscalls. */ 86151979Sjhb#define IRQ_TIMER (NUM_IO_INTS + 1) 87151979Sjhb#define IRQ_SYSCALL (NUM_IO_INTS + 2) 88151979Sjhb 89121986Sjhb/* 90121986Sjhb * Support for local APICs. Local APICs manage interrupts on each 91121986Sjhb * individual processor as opposed to I/O APICs which receive interrupts 92121986Sjhb * from I/O devices and then forward them on to the local APICs. 93121986Sjhb * 94121986Sjhb * Local APICs can also send interrupts to each other thus providing the 95121986Sjhb * mechanism for IPIs. 96121986Sjhb */ 97121986Sjhb 98121986Sjhbstruct lvt { 99121986Sjhb u_int lvt_edgetrigger:1; 100121986Sjhb u_int lvt_activehi:1; 101121986Sjhb u_int lvt_masked:1; 102121986Sjhb u_int lvt_active:1; 103121986Sjhb u_int lvt_mode:16; 104121986Sjhb u_int lvt_vector:8; 105121986Sjhb}; 106121986Sjhb 107121986Sjhbstruct lapic { 108121986Sjhb struct lvt la_lvts[LVT_MAX + 1]; 109121986Sjhb u_int la_id:8; 110121986Sjhb u_int la_cluster:4; 111121986Sjhb u_int la_cluster_id:2; 112121986Sjhb u_int la_present:1; 113141538Sjhb u_long *la_timer_count; 114141538Sjhb u_long la_hard_ticks; 115141538Sjhb u_long la_stat_ticks; 116141538Sjhb u_long la_prof_ticks; 117121986Sjhb} static lapics[MAX_APICID]; 118121986Sjhb 119121986Sjhb/* XXX: should thermal be an NMI? */ 120121986Sjhb 121121986Sjhb/* Global defaults for local APIC LVT entries. */ 122121986Sjhbstatic struct lvt lvts[LVT_MAX + 1] = { 123121986Sjhb { 1, 1, 1, 1, APIC_LVT_DM_EXTINT, 0 }, /* LINT0: masked ExtINT */ 124121986Sjhb { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* LINT1: NMI */ 125139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_TIMER_INT }, /* Timer */ 126139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_ERROR_INT }, /* Error */ 127145256Sjkoshy { 1, 1, 0, 1, APIC_LVT_DM_NMI, 0 }, /* PMC */ 128139245Sjhb { 1, 1, 1, 1, APIC_LVT_DM_FIXED, APIC_THERMAL_INT }, /* Thermal */ 129121986Sjhb}; 130121986Sjhb 131121986Sjhbstatic inthand_t *ioint_handlers[] = { 132121986Sjhb NULL, /* 0 - 31 */ 133121986Sjhb IDTVEC(apic_isr1), /* 32 - 63 */ 134121986Sjhb IDTVEC(apic_isr2), /* 64 - 95 */ 135121986Sjhb IDTVEC(apic_isr3), /* 96 - 127 */ 136121986Sjhb IDTVEC(apic_isr4), /* 128 - 159 */ 137121986Sjhb IDTVEC(apic_isr5), /* 160 - 191 */ 138122690Sjhb IDTVEC(apic_isr6), /* 192 - 223 */ 139122690Sjhb IDTVEC(apic_isr7), /* 224 - 255 */ 140121986Sjhb}; 141121986Sjhb 142151979Sjhb/* Include IDT_SYSCALL to make indexing easier. */ 143151979Sjhbstatic u_int ioint_irqs[APIC_NUM_IOINTS + 1]; 144151979Sjhb 145141538Sjhbstatic u_int32_t lapic_timer_divisors[] = { 146141538Sjhb APIC_TDCR_1, APIC_TDCR_2, APIC_TDCR_4, APIC_TDCR_8, APIC_TDCR_16, 147141538Sjhb APIC_TDCR_32, APIC_TDCR_64, APIC_TDCR_128 148141538Sjhb}; 149141538Sjhb 150121986Sjhbvolatile lapic_t *lapic; 151141538Sjhbstatic u_long lapic_timer_divisor, lapic_timer_period, lapic_timer_hz; 152121986Sjhb 153139245Sjhbstatic void lapic_enable(void); 154141538Sjhbstatic void lapic_timer_enable_intr(void); 155141538Sjhbstatic void lapic_timer_oneshot(u_int count); 156141538Sjhbstatic void lapic_timer_periodic(u_int count); 157141538Sjhbstatic void lapic_timer_set_divisor(u_int divisor); 158139245Sjhbstatic uint32_t lvt_mode(struct lapic *la, u_int pin, uint32_t value); 159139245Sjhb 160121986Sjhbstatic uint32_t 161121986Sjhblvt_mode(struct lapic *la, u_int pin, uint32_t value) 162121986Sjhb{ 163121986Sjhb struct lvt *lvt; 164121986Sjhb 165121986Sjhb KASSERT(pin <= LVT_MAX, ("%s: pin %u out of range", __func__, pin)); 166121986Sjhb if (la->la_lvts[pin].lvt_active) 167121986Sjhb lvt = &la->la_lvts[pin]; 168121986Sjhb else 169121986Sjhb lvt = &lvts[pin]; 170121986Sjhb 171121986Sjhb value &= ~(APIC_LVT_M | APIC_LVT_TM | APIC_LVT_IIPP | APIC_LVT_DM | 172121986Sjhb APIC_LVT_VECTOR); 173121986Sjhb if (lvt->lvt_edgetrigger == 0) 174121986Sjhb value |= APIC_LVT_TM; 175121986Sjhb if (lvt->lvt_activehi == 0) 176121986Sjhb value |= APIC_LVT_IIPP_INTALO; 177121986Sjhb if (lvt->lvt_masked) 178121986Sjhb value |= APIC_LVT_M; 179121986Sjhb value |= lvt->lvt_mode; 180121986Sjhb switch (lvt->lvt_mode) { 181121986Sjhb case APIC_LVT_DM_NMI: 182121986Sjhb case APIC_LVT_DM_SMI: 183121986Sjhb case APIC_LVT_DM_INIT: 184121986Sjhb case APIC_LVT_DM_EXTINT: 185121986Sjhb if (!lvt->lvt_edgetrigger) { 186121986Sjhb printf("lapic%u: Forcing LINT%u to edge trigger\n", 187121986Sjhb la->la_id, pin); 188121986Sjhb value |= APIC_LVT_TM; 189121986Sjhb } 190121986Sjhb /* Use a vector of 0. */ 191121986Sjhb break; 192121986Sjhb case APIC_LVT_DM_FIXED: 193121986Sjhb value |= lvt->lvt_vector; 194121986Sjhb break; 195121986Sjhb default: 196121986Sjhb panic("bad APIC LVT delivery mode: %#x\n", value); 197121986Sjhb } 198121986Sjhb return (value); 199121986Sjhb} 200121986Sjhb 201121986Sjhb/* 202121986Sjhb * Map the local APIC and setup necessary interrupt vectors. 203121986Sjhb */ 204121986Sjhbvoid 205121986Sjhblapic_init(uintptr_t addr) 206121986Sjhb{ 207121986Sjhb 208121986Sjhb /* Map the local APIC and setup the spurious interrupt handler. */ 209121986Sjhb KASSERT(trunc_page(addr) == addr, 210121986Sjhb ("local APIC not aligned on a page boundary")); 211156920Sjhb lapic = pmap_mapdev(addr, sizeof(lapic_t)); 212121986Sjhb setidt(APIC_SPURIOUS_INT, IDTVEC(spuriousint), SDT_SYS386IGT, SEL_KPL, 213121986Sjhb GSEL(GCODE_SEL, SEL_KPL)); 214121986Sjhb 215121986Sjhb /* Perform basic initialization of the BSP's local APIC. */ 216139245Sjhb lapic_enable(); 217151979Sjhb ioint_irqs[IDT_SYSCALL - APIC_IO_INTS] = IRQ_SYSCALL; 218121986Sjhb 219121986Sjhb /* Set BSP's per-CPU local APIC ID. */ 220121986Sjhb PCPU_SET(apic_id, lapic_id()); 221156124Sjhb intr_add_cpu(PCPU_GET(apic_id)); 222121986Sjhb 223141538Sjhb /* Local APIC timer interrupt. */ 224141538Sjhb setidt(APIC_TIMER_INT, IDTVEC(timerint), SDT_SYS386IGT, SEL_KPL, 225141538Sjhb GSEL(GCODE_SEL, SEL_KPL)); 226151979Sjhb ioint_irqs[APIC_TIMER_INT - APIC_IO_INTS] = IRQ_TIMER; 227141538Sjhb 228141538Sjhb /* XXX: error/thermal interrupts */ 229121986Sjhb} 230121986Sjhb 231121986Sjhb/* 232121986Sjhb * Create a local APIC instance. 233121986Sjhb */ 234121986Sjhbvoid 235121986Sjhblapic_create(u_int apic_id, int boot_cpu) 236121986Sjhb{ 237121986Sjhb int i; 238121986Sjhb 239132156Sjhb if (apic_id >= MAX_APICID) { 240121986Sjhb printf("APIC: Ignoring local APIC with ID %d\n", apic_id); 241121986Sjhb if (boot_cpu) 242121986Sjhb panic("Can't ignore BSP"); 243121986Sjhb return; 244121986Sjhb } 245121986Sjhb KASSERT(!lapics[apic_id].la_present, ("duplicate local APIC %u", 246121986Sjhb apic_id)); 247121986Sjhb 248121986Sjhb /* 249121986Sjhb * Assume no local LVT overrides and a cluster of 0 and 250121986Sjhb * intra-cluster ID of 0. 251121986Sjhb */ 252121986Sjhb lapics[apic_id].la_present = 1; 253121986Sjhb lapics[apic_id].la_id = apic_id; 254121986Sjhb for (i = 0; i < LVT_MAX; i++) { 255121986Sjhb lapics[apic_id].la_lvts[i] = lvts[i]; 256121986Sjhb lapics[apic_id].la_lvts[i].lvt_active = 0; 257121986Sjhb } 258121986Sjhb 259121986Sjhb#ifdef SMP 260121986Sjhb cpu_add(apic_id, boot_cpu); 261121986Sjhb#endif 262121986Sjhb} 263121986Sjhb 264121986Sjhb/* 265121986Sjhb * Dump contents of local APIC registers 266121986Sjhb */ 267121986Sjhbvoid 268121986Sjhblapic_dump(const char* str) 269121986Sjhb{ 270121986Sjhb 271121986Sjhb printf("cpu%d %s:\n", PCPU_GET(cpuid), str); 272121986Sjhb printf(" ID: 0x%08x VER: 0x%08x LDR: 0x%08x DFR: 0x%08x\n", 273121986Sjhb lapic->id, lapic->version, lapic->ldr, lapic->dfr); 274121986Sjhb printf(" lint0: 0x%08x lint1: 0x%08x TPR: 0x%08x SVR: 0x%08x\n", 275121986Sjhb lapic->lvt_lint0, lapic->lvt_lint1, lapic->tpr, lapic->svr); 276139245Sjhb printf(" timer: 0x%08x therm: 0x%08x err: 0x%08x pcm: 0x%08x\n", 277139245Sjhb lapic->lvt_timer, lapic->lvt_thermal, lapic->lvt_error, 278139245Sjhb lapic->lvt_pcint); 279121986Sjhb} 280121986Sjhb 281121986Sjhbvoid 282121986Sjhblapic_setup(void) 283121986Sjhb{ 284121986Sjhb struct lapic *la; 285156124Sjhb u_int32_t maxlvt; 286121986Sjhb register_t eflags; 287141538Sjhb char buf[MAXCOMLEN + 1]; 288121986Sjhb 289121986Sjhb la = &lapics[lapic_id()]; 290121986Sjhb KASSERT(la->la_present, ("missing APIC structure")); 291121986Sjhb eflags = intr_disable(); 292121986Sjhb maxlvt = (lapic->version & APIC_VER_MAXLVT) >> MAXLVTSHIFT; 293121986Sjhb 294139240Sjhb /* Initialize the TPR to allow all interrupts. */ 295139240Sjhb lapic_set_tpr(0); 296121986Sjhb 297121986Sjhb /* Setup spurious vector and enable the local APIC. */ 298139245Sjhb lapic_enable(); 299139245Sjhb 300139245Sjhb /* Program LINT[01] LVT entries. */ 301139245Sjhb lapic->lvt_lint0 = lvt_mode(la, LVT_LINT0, lapic->lvt_lint0); 302139245Sjhb lapic->lvt_lint1 = lvt_mode(la, LVT_LINT1, lapic->lvt_lint1); 303145256Sjkoshy#ifdef HWPMC_HOOKS 304145256Sjkoshy /* Program the PMC LVT entry if present. */ 305145256Sjkoshy if (maxlvt >= LVT_PMC) 306145256Sjkoshy lapic->lvt_pcint = lvt_mode(la, LVT_PMC, lapic->lvt_pcint); 307145256Sjkoshy#endif 308139245Sjhb 309141538Sjhb /* Program timer LVT and setup handler. */ 310141538Sjhb lapic->lvt_timer = lvt_mode(la, LVT_TIMER, lapic->lvt_timer); 311150696Sjhb snprintf(buf, sizeof(buf), "cpu%d: timer", PCPU_GET(cpuid)); 312141538Sjhb intrcnt_add(buf, &la->la_timer_count); 313141538Sjhb if (PCPU_GET(cpuid) != 0) { 314141538Sjhb KASSERT(lapic_timer_period != 0, ("lapic%u: zero divisor", 315141538Sjhb lapic_id())); 316141538Sjhb lapic_timer_set_divisor(lapic_timer_divisor); 317141538Sjhb lapic_timer_periodic(lapic_timer_period); 318141538Sjhb lapic_timer_enable_intr(); 319141538Sjhb } 320139245Sjhb 321150176Sjhb /* XXX: Error and thermal LVTs */ 322141538Sjhb 323121986Sjhb intr_restore(eflags); 324121986Sjhb} 325121986Sjhb 326141538Sjhb/* 327141538Sjhb * Called by cpu_initclocks() on the BSP to setup the local APIC timer so 328141538Sjhb * that it can drive hardclock, statclock, and profclock. This function 329141538Sjhb * returns true if it is able to use the local APIC timer to drive the 330141538Sjhb * clocks and false if it is not able. 331141538Sjhb */ 332141538Sjhbint 333141538Sjhblapic_setup_clock(void) 334141538Sjhb{ 335141538Sjhb u_long value; 336141538Sjhb 337141538Sjhb /* Can't drive the timer without a local APIC. */ 338141538Sjhb if (lapic == NULL) 339141538Sjhb return (0); 340141538Sjhb 341141538Sjhb /* Start off with a divisor of 2 (power on reset default). */ 342141538Sjhb lapic_timer_divisor = 2; 343141538Sjhb 344141538Sjhb /* Try to calibrate the local APIC timer. */ 345141538Sjhb do { 346141538Sjhb lapic_timer_set_divisor(lapic_timer_divisor); 347141538Sjhb lapic_timer_oneshot(APIC_TIMER_MAX_COUNT); 348141538Sjhb DELAY(2000000); 349141538Sjhb value = APIC_TIMER_MAX_COUNT - lapic->ccr_timer; 350141538Sjhb if (value != APIC_TIMER_MAX_COUNT) 351141538Sjhb break; 352141538Sjhb lapic_timer_divisor <<= 1; 353141538Sjhb } while (lapic_timer_divisor <= 128); 354141538Sjhb if (lapic_timer_divisor > 128) 355141538Sjhb panic("lapic: Divisor too big"); 356141538Sjhb value /= 2; 357141538Sjhb if (bootverbose) 358141538Sjhb printf("lapic: Divisor %lu, Frequency %lu hz\n", 359141538Sjhb lapic_timer_divisor, value); 360141538Sjhb 361141538Sjhb /* 362141538Sjhb * We will drive the timer at a small multiple of hz and drive 363141538Sjhb * both of the other timers with similarly small but relatively 364141538Sjhb * prime divisors. 365141538Sjhb */ 366141538Sjhb lapic_timer_hz = hz * LAPIC_TIMER_HZ_DIVIDER; 367141538Sjhb stathz = lapic_timer_hz / LAPIC_TIMER_STATHZ_DIVIDER; 368141538Sjhb profhz = lapic_timer_hz / LAPIC_TIMER_PROFHZ_DIVIDER; 369141538Sjhb lapic_timer_period = value / lapic_timer_hz; 370141538Sjhb 371141538Sjhb /* 372141538Sjhb * Start up the timer on the BSP. The APs will kick off their 373141538Sjhb * timer during lapic_setup(). 374141538Sjhb */ 375141538Sjhb lapic_timer_periodic(lapic_timer_period); 376141538Sjhb lapic_timer_enable_intr(); 377141538Sjhb return (1); 378141538Sjhb} 379141538Sjhb 380121986Sjhbvoid 381121986Sjhblapic_disable(void) 382121986Sjhb{ 383121986Sjhb uint32_t value; 384121986Sjhb 385121986Sjhb /* Software disable the local APIC. */ 386121986Sjhb value = lapic->svr; 387121986Sjhb value &= ~APIC_SVR_SWEN; 388121986Sjhb lapic->svr = value; 389121986Sjhb} 390121986Sjhb 391139245Sjhbstatic void 392139245Sjhblapic_enable(void) 393139245Sjhb{ 394139245Sjhb u_int32_t value; 395139245Sjhb 396139245Sjhb /* Program the spurious vector to enable the local APIC. */ 397139245Sjhb value = lapic->svr; 398139245Sjhb value &= ~(APIC_SVR_VECTOR | APIC_SVR_FOCUS); 399139245Sjhb value |= (APIC_SVR_FEN | APIC_SVR_SWEN | APIC_SPURIOUS_INT); 400139245Sjhb lapic->svr = value; 401139245Sjhb} 402139245Sjhb 403121986Sjhbint 404121986Sjhblapic_id(void) 405121986Sjhb{ 406121986Sjhb 407121986Sjhb KASSERT(lapic != NULL, ("local APIC is not mapped")); 408121986Sjhb return (lapic->id >> APIC_ID_SHIFT); 409121986Sjhb} 410121986Sjhb 411121986Sjhbint 412121986Sjhblapic_intr_pending(u_int vector) 413121986Sjhb{ 414121986Sjhb volatile u_int32_t *irr; 415121986Sjhb 416121986Sjhb /* 417121986Sjhb * The IRR registers are an array of 128-bit registers each of 418121986Sjhb * which only describes 32 interrupts in the low 32 bits.. Thus, 419121986Sjhb * we divide the vector by 32 to get the 128-bit index. We then 420121986Sjhb * multiply that index by 4 to get the equivalent index from 421121986Sjhb * treating the IRR as an array of 32-bit registers. Finally, we 422121986Sjhb * modulus the vector by 32 to determine the individual bit to 423121986Sjhb * test. 424121986Sjhb */ 425121986Sjhb irr = &lapic->irr0; 426121986Sjhb return (irr[(vector / 32) * 4] & 1 << (vector % 32)); 427121986Sjhb} 428121986Sjhb 429121986Sjhbvoid 430121986Sjhblapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id) 431121986Sjhb{ 432121986Sjhb struct lapic *la; 433121986Sjhb 434121986Sjhb KASSERT(lapics[apic_id].la_present, ("%s: APIC %u doesn't exist", 435121986Sjhb __func__, apic_id)); 436121986Sjhb KASSERT(cluster <= APIC_MAX_CLUSTER, ("%s: cluster %u too big", 437121986Sjhb __func__, cluster)); 438121986Sjhb KASSERT(cluster_id <= APIC_MAX_INTRACLUSTER_ID, 439121986Sjhb ("%s: intra cluster id %u too big", __func__, cluster_id)); 440121986Sjhb la = &lapics[apic_id]; 441121986Sjhb la->la_cluster = cluster; 442121986Sjhb la->la_cluster_id = cluster_id; 443121986Sjhb} 444121986Sjhb 445121986Sjhbint 446121986Sjhblapic_set_lvt_mask(u_int apic_id, u_int pin, u_char masked) 447121986Sjhb{ 448121986Sjhb 449121986Sjhb if (pin > LVT_MAX) 450121986Sjhb return (EINVAL); 451121986Sjhb if (apic_id == APIC_ID_ALL) { 452121986Sjhb lvts[pin].lvt_masked = masked; 453121986Sjhb if (bootverbose) 454121986Sjhb printf("lapic:"); 455121986Sjhb } else { 456121986Sjhb KASSERT(lapics[apic_id].la_present, 457121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 458121986Sjhb lapics[apic_id].la_lvts[pin].lvt_masked = masked; 459121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 460121986Sjhb if (bootverbose) 461121986Sjhb printf("lapic%u:", apic_id); 462121986Sjhb } 463121986Sjhb if (bootverbose) 464121986Sjhb printf(" LINT%u %s\n", pin, masked ? "masked" : "unmasked"); 465121986Sjhb return (0); 466121986Sjhb} 467121986Sjhb 468121986Sjhbint 469121986Sjhblapic_set_lvt_mode(u_int apic_id, u_int pin, u_int32_t mode) 470121986Sjhb{ 471121986Sjhb struct lvt *lvt; 472121986Sjhb 473121986Sjhb if (pin > LVT_MAX) 474121986Sjhb return (EINVAL); 475121986Sjhb if (apic_id == APIC_ID_ALL) { 476121986Sjhb lvt = &lvts[pin]; 477121986Sjhb if (bootverbose) 478121986Sjhb printf("lapic:"); 479121986Sjhb } else { 480121986Sjhb KASSERT(lapics[apic_id].la_present, 481121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 482121986Sjhb lvt = &lapics[apic_id].la_lvts[pin]; 483121986Sjhb lvt->lvt_active = 1; 484121986Sjhb if (bootverbose) 485121986Sjhb printf("lapic%u:", apic_id); 486121986Sjhb } 487121986Sjhb lvt->lvt_mode = mode; 488121986Sjhb switch (mode) { 489121986Sjhb case APIC_LVT_DM_NMI: 490121986Sjhb case APIC_LVT_DM_SMI: 491121986Sjhb case APIC_LVT_DM_INIT: 492121986Sjhb case APIC_LVT_DM_EXTINT: 493121986Sjhb lvt->lvt_edgetrigger = 1; 494121986Sjhb lvt->lvt_activehi = 1; 495121986Sjhb if (mode == APIC_LVT_DM_EXTINT) 496121986Sjhb lvt->lvt_masked = 1; 497121986Sjhb else 498121986Sjhb lvt->lvt_masked = 0; 499121986Sjhb break; 500121986Sjhb default: 501121986Sjhb panic("Unsupported delivery mode: 0x%x\n", mode); 502121986Sjhb } 503121986Sjhb if (bootverbose) { 504121986Sjhb printf(" Routing "); 505121986Sjhb switch (mode) { 506121986Sjhb case APIC_LVT_DM_NMI: 507121986Sjhb printf("NMI"); 508121986Sjhb break; 509121986Sjhb case APIC_LVT_DM_SMI: 510121986Sjhb printf("SMI"); 511121986Sjhb break; 512121986Sjhb case APIC_LVT_DM_INIT: 513121986Sjhb printf("INIT"); 514121986Sjhb break; 515121986Sjhb case APIC_LVT_DM_EXTINT: 516121986Sjhb printf("ExtINT"); 517121986Sjhb break; 518121986Sjhb } 519121986Sjhb printf(" -> LINT%u\n", pin); 520121986Sjhb } 521121986Sjhb return (0); 522121986Sjhb} 523121986Sjhb 524121986Sjhbint 525128930Sjhblapic_set_lvt_polarity(u_int apic_id, u_int pin, enum intr_polarity pol) 526121986Sjhb{ 527121986Sjhb 528128930Sjhb if (pin > LVT_MAX || pol == INTR_POLARITY_CONFORM) 529121986Sjhb return (EINVAL); 530121986Sjhb if (apic_id == APIC_ID_ALL) { 531128930Sjhb lvts[pin].lvt_activehi = (pol == INTR_POLARITY_HIGH); 532121986Sjhb if (bootverbose) 533121986Sjhb printf("lapic:"); 534121986Sjhb } else { 535121986Sjhb KASSERT(lapics[apic_id].la_present, 536121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 537121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 538128930Sjhb lapics[apic_id].la_lvts[pin].lvt_activehi = 539128930Sjhb (pol == INTR_POLARITY_HIGH); 540121986Sjhb if (bootverbose) 541121986Sjhb printf("lapic%u:", apic_id); 542121986Sjhb } 543121986Sjhb if (bootverbose) 544140254Sjhb printf(" LINT%u polarity: %s\n", pin, 545128930Sjhb pol == INTR_POLARITY_HIGH ? "high" : "low"); 546121986Sjhb return (0); 547121986Sjhb} 548121986Sjhb 549121986Sjhbint 550128930Sjhblapic_set_lvt_triggermode(u_int apic_id, u_int pin, enum intr_trigger trigger) 551121986Sjhb{ 552121986Sjhb 553128930Sjhb if (pin > LVT_MAX || trigger == INTR_TRIGGER_CONFORM) 554121986Sjhb return (EINVAL); 555121986Sjhb if (apic_id == APIC_ID_ALL) { 556128930Sjhb lvts[pin].lvt_edgetrigger = (trigger == INTR_TRIGGER_EDGE); 557121986Sjhb if (bootverbose) 558121986Sjhb printf("lapic:"); 559121986Sjhb } else { 560121986Sjhb KASSERT(lapics[apic_id].la_present, 561121986Sjhb ("%s: missing APIC %u", __func__, apic_id)); 562128930Sjhb lapics[apic_id].la_lvts[pin].lvt_edgetrigger = 563128930Sjhb (trigger == INTR_TRIGGER_EDGE); 564121986Sjhb lapics[apic_id].la_lvts[pin].lvt_active = 1; 565121986Sjhb if (bootverbose) 566121986Sjhb printf("lapic%u:", apic_id); 567121986Sjhb } 568121986Sjhb if (bootverbose) 569121986Sjhb printf(" LINT%u trigger: %s\n", pin, 570128930Sjhb trigger == INTR_TRIGGER_EDGE ? "edge" : "level"); 571121986Sjhb return (0); 572121986Sjhb} 573121986Sjhb 574139240Sjhb/* 575139240Sjhb * Adjust the TPR of the current CPU so that it blocks all interrupts below 576139240Sjhb * the passed in vector. 577139240Sjhb */ 578121986Sjhbvoid 579139240Sjhblapic_set_tpr(u_int vector) 580139240Sjhb{ 581139240Sjhb#ifdef CHEAP_TPR 582139240Sjhb lapic->tpr = vector; 583139240Sjhb#else 584139240Sjhb u_int32_t tpr; 585139240Sjhb 586139240Sjhb tpr = lapic->tpr & ~APIC_TPR_PRIO; 587139240Sjhb tpr |= vector; 588139240Sjhb lapic->tpr = tpr; 589139240Sjhb#endif 590139240Sjhb} 591139240Sjhb 592139240Sjhbvoid 593122572Sjhblapic_eoi(void) 594122572Sjhb{ 595122572Sjhb 596122572Sjhb lapic->eoi = 0; 597122572Sjhb} 598122572Sjhb 599122572Sjhbvoid 600153146Sjhblapic_handle_intr(int vector, struct trapframe frame) 601121986Sjhb{ 602121986Sjhb struct intsrc *isrc; 603121986Sjhb 604153146Sjhb if (vector == -1) 605121986Sjhb panic("Couldn't get vector from ISR!"); 606153146Sjhb isrc = intr_lookup_source(apic_idt_to_irq(vector)); 607121986Sjhb intr_execute_handlers(isrc, &frame); 608121986Sjhb} 609121986Sjhb 610141538Sjhbvoid 611153666Sjhblapic_handle_timer(struct trapframe frame) 612141538Sjhb{ 613141538Sjhb struct lapic *la; 614141538Sjhb 615153141Sjhb /* Send EOI first thing. */ 616153141Sjhb lapic_eoi(); 617153141Sjhb 618162708Ssobomax#if defined(SMP) && !defined(SCHED_ULE) 619162042Ssobomax /* 620162042Ssobomax * Don't do any accounting for the disabled HTT cores, since it 621162042Ssobomax * will provide misleading numbers for the userland. 622162042Ssobomax * 623162042Ssobomax * No locking is necessary here, since even if we loose the race 624162042Ssobomax * when hlt_cpus_mask changes it is not a big deal, really. 625162042Ssobomax */ 626162042Ssobomax if ((hlt_cpus_mask & (1 << PCPU_GET(cpuid))) != 0) 627162042Ssobomax return; 628162087Ssobomax#endif 629162042Ssobomax 630153141Sjhb /* Look up our local APIC structure for the tick counters. */ 631141538Sjhb la = &lapics[PCPU_GET(apic_id)]; 632141538Sjhb (*la->la_timer_count)++; 633141538Sjhb critical_enter(); 634141538Sjhb 635141538Sjhb /* Fire hardclock at hz. */ 636141538Sjhb la->la_hard_ticks += hz; 637141538Sjhb if (la->la_hard_ticks >= lapic_timer_hz) { 638141538Sjhb la->la_hard_ticks -= lapic_timer_hz; 639143034Sjhb if (PCPU_GET(cpuid) == 0) 640153666Sjhb hardclock(TRAPF_USERMODE(&frame), TRAPF_PC(&frame)); 641143034Sjhb else 642153666Sjhb hardclock_cpu(TRAPF_USERMODE(&frame)); 643141538Sjhb } 644141538Sjhb 645141538Sjhb /* Fire statclock at stathz. */ 646141538Sjhb la->la_stat_ticks += stathz; 647141538Sjhb if (la->la_stat_ticks >= lapic_timer_hz) { 648141538Sjhb la->la_stat_ticks -= lapic_timer_hz; 649153666Sjhb statclock(TRAPF_USERMODE(&frame)); 650141538Sjhb } 651141538Sjhb 652141538Sjhb /* Fire profclock at profhz, but only when needed. */ 653141538Sjhb la->la_prof_ticks += profhz; 654141538Sjhb if (la->la_prof_ticks >= lapic_timer_hz) { 655141538Sjhb la->la_prof_ticks -= lapic_timer_hz; 656141538Sjhb if (profprocs != 0) 657153666Sjhb profclock(TRAPF_USERMODE(&frame), TRAPF_PC(&frame)); 658141538Sjhb } 659141538Sjhb critical_exit(); 660141538Sjhb} 661141538Sjhb 662141538Sjhbstatic void 663141538Sjhblapic_timer_set_divisor(u_int divisor) 664141538Sjhb{ 665141538Sjhb 666141538Sjhb KASSERT(powerof2(divisor), ("lapic: invalid divisor %u", divisor)); 667141538Sjhb KASSERT(ffs(divisor) <= sizeof(lapic_timer_divisors) / 668141538Sjhb sizeof(u_int32_t), ("lapic: invalid divisor %u", divisor)); 669141538Sjhb lapic->dcr_timer = lapic_timer_divisors[ffs(divisor) - 1]; 670141538Sjhb} 671141538Sjhb 672141538Sjhbstatic void 673141538Sjhblapic_timer_oneshot(u_int count) 674141538Sjhb{ 675141538Sjhb u_int32_t value; 676141538Sjhb 677141538Sjhb value = lapic->lvt_timer; 678141538Sjhb value &= ~APIC_LVTT_TM; 679141538Sjhb value |= APIC_LVTT_TM_ONE_SHOT; 680141538Sjhb lapic->lvt_timer = value; 681141538Sjhb lapic->icr_timer = count; 682141538Sjhb} 683141538Sjhb 684141538Sjhbstatic void 685141538Sjhblapic_timer_periodic(u_int count) 686141538Sjhb{ 687141538Sjhb u_int32_t value; 688141538Sjhb 689141538Sjhb value = lapic->lvt_timer; 690141538Sjhb value &= ~APIC_LVTT_TM; 691141538Sjhb value |= APIC_LVTT_TM_PERIODIC; 692141538Sjhb lapic->lvt_timer = value; 693141538Sjhb lapic->icr_timer = count; 694141538Sjhb} 695141538Sjhb 696141538Sjhbstatic void 697141538Sjhblapic_timer_enable_intr(void) 698141538Sjhb{ 699141538Sjhb u_int32_t value; 700141538Sjhb 701141538Sjhb value = lapic->lvt_timer; 702141538Sjhb value &= ~APIC_LVT_M; 703141538Sjhb lapic->lvt_timer = value; 704141538Sjhb} 705141538Sjhb 706151979Sjhb/* Request a free IDT vector to be used by the specified IRQ. */ 707121986Sjhbu_int 708151979Sjhbapic_alloc_vector(u_int irq) 709121986Sjhb{ 710121986Sjhb u_int vector; 711121986Sjhb 712121986Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 713151979Sjhb 714151979Sjhb /* 715151979Sjhb * Search for a free vector. Currently we just use a very simple 716151979Sjhb * algorithm to find the first free vector. 717151979Sjhb */ 718151979Sjhb mtx_lock_spin(&icu_lock); 719151979Sjhb for (vector = 0; vector < APIC_NUM_IOINTS; vector++) { 720151979Sjhb if (ioint_irqs[vector] != 0) 721151979Sjhb continue; 722151979Sjhb ioint_irqs[vector] = irq; 723151979Sjhb mtx_unlock_spin(&icu_lock); 724151979Sjhb return (vector + APIC_IO_INTS); 725151979Sjhb } 726151979Sjhb mtx_unlock_spin(&icu_lock); 727151979Sjhb panic("Couldn't find an APIC vector for IRQ %u", irq); 728121986Sjhb} 729121986Sjhb 730151979Sjhbvoid 731151979Sjhbapic_enable_vector(u_int vector) 732151979Sjhb{ 733151979Sjhb 734151979Sjhb KASSERT(vector != IDT_SYSCALL, ("Attempt to overwrite syscall entry")); 735151979Sjhb KASSERT(ioint_handlers[vector / 32] != NULL, 736151979Sjhb ("No ISR handler for vector %u", vector)); 737151979Sjhb setidt(vector, ioint_handlers[vector / 32], SDT_SYS386IGT, SEL_KPL, 738151979Sjhb GSEL(GCODE_SEL, SEL_KPL)); 739151979Sjhb} 740151979Sjhb 741151979Sjhb/* Release an APIC vector when it's no longer in use. */ 742151979Sjhbvoid 743151979Sjhbapic_free_vector(u_int vector, u_int irq) 744151979Sjhb{ 745151979Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 746151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 747151979Sjhb ("Vector %u does not map to an IRQ line", vector)); 748151979Sjhb KASSERT(irq < NUM_IO_INTS, ("Invalid IRQ %u", irq)); 749151979Sjhb KASSERT(ioint_irqs[vector - APIC_IO_INTS] == irq, ("IRQ mismatch")); 750151979Sjhb mtx_lock_spin(&icu_lock); 751151979Sjhb ioint_irqs[vector - APIC_IO_INTS] = 0; 752151979Sjhb mtx_unlock_spin(&icu_lock); 753151979Sjhb} 754151979Sjhb 755151979Sjhb/* Map an IDT vector (APIC) to an IRQ (interrupt source). */ 756121986Sjhbu_int 757121986Sjhbapic_idt_to_irq(u_int vector) 758121986Sjhb{ 759121986Sjhb 760122690Sjhb KASSERT(vector >= APIC_IO_INTS && vector != IDT_SYSCALL && 761151979Sjhb vector <= APIC_IO_INTS + APIC_NUM_IOINTS, 762121986Sjhb ("Vector %u does not map to an IRQ line", vector)); 763151979Sjhb return (ioint_irqs[vector - APIC_IO_INTS]); 764121986Sjhb} 765121986Sjhb 766151979Sjhb#ifdef DDB 767121986Sjhb/* 768151979Sjhb * Dump data about APIC IDT vector mappings. 769151979Sjhb */ 770151979SjhbDB_SHOW_COMMAND(apic, db_show_apic) 771151979Sjhb{ 772151979Sjhb struct intsrc *isrc; 773160312Sjhb int i, verbose; 774151979Sjhb u_int irq; 775151979Sjhb 776151979Sjhb if (strcmp(modif, "vv") == 0) 777151979Sjhb verbose = 2; 778151979Sjhb else if (strcmp(modif, "v") == 0) 779151979Sjhb verbose = 1; 780151979Sjhb else 781151979Sjhb verbose = 0; 782160312Sjhb for (i = 0; i < APIC_NUM_IOINTS + 1 && !db_pager_quit; i++) { 783151979Sjhb irq = ioint_irqs[i]; 784151979Sjhb if (irq != 0 && irq != IRQ_SYSCALL) { 785151979Sjhb db_printf("vec 0x%2x -> ", i + APIC_IO_INTS); 786151979Sjhb if (irq == IRQ_TIMER) 787151979Sjhb db_printf("lapic timer\n"); 788151979Sjhb else if (irq < NUM_IO_INTS) { 789151979Sjhb isrc = intr_lookup_source(irq); 790151979Sjhb if (isrc == NULL || verbose == 0) 791151979Sjhb db_printf("IRQ %u\n", irq); 792151979Sjhb else 793151979Sjhb db_dump_intr_event(isrc->is_event, 794151979Sjhb verbose == 2); 795151979Sjhb } else 796151979Sjhb db_printf("IRQ %u ???\n", irq); 797151979Sjhb } 798151979Sjhb } 799151979Sjhb} 800162233Sjhb 801162233Sjhbstatic void 802162233Sjhbdump_mask(const char *prefix, uint32_t v, int base) 803162233Sjhb{ 804162233Sjhb int i, first; 805162233Sjhb 806162233Sjhb first = 1; 807162233Sjhb for (i = 0; i < 32; i++) 808162233Sjhb if (v & (1 << i)) { 809162233Sjhb if (first) { 810162233Sjhb db_printf("%s:", prefix); 811162233Sjhb first = 0; 812162233Sjhb } 813162233Sjhb db_printf(" %02x", base + i); 814162233Sjhb } 815162233Sjhb if (!first) 816162233Sjhb db_printf("\n"); 817162233Sjhb} 818162233Sjhb 819162233Sjhb/* Show info from the lapic regs for this CPU. */ 820162233SjhbDB_SHOW_COMMAND(lapic, db_show_lapic) 821162233Sjhb{ 822162233Sjhb uint32_t v; 823162233Sjhb 824162233Sjhb db_printf("lapic ID = %d\n", lapic_id()); 825162233Sjhb v = lapic->version; 826162233Sjhb db_printf("version = %d.%d\n", (v & APIC_VER_VERSION) >> 4, 827162233Sjhb v & 0xf); 828162233Sjhb db_printf("max LVT = %d\n", (v & APIC_VER_MAXLVT) >> MAXLVTSHIFT); 829162233Sjhb v = lapic->svr; 830162233Sjhb db_printf("SVR = %02x (%s)\n", v & APIC_SVR_VECTOR, 831162233Sjhb v & APIC_SVR_ENABLE ? "enabled" : "disabled"); 832162233Sjhb db_printf("TPR = %02x\n", lapic->tpr); 833162233Sjhb 834162233Sjhb#define dump_field(prefix, index) \ 835162233Sjhb dump_mask(__XSTRING(prefix ## index), lapic->prefix ## index, \ 836162233Sjhb index * 32) 837162233Sjhb 838162233Sjhb db_printf("In-service Interrupts:\n"); 839162233Sjhb dump_field(isr, 0); 840162233Sjhb dump_field(isr, 1); 841162233Sjhb dump_field(isr, 2); 842162233Sjhb dump_field(isr, 3); 843162233Sjhb dump_field(isr, 4); 844162233Sjhb dump_field(isr, 5); 845162233Sjhb dump_field(isr, 6); 846162233Sjhb dump_field(isr, 7); 847162233Sjhb 848162233Sjhb db_printf("TMR Interrupts:\n"); 849162233Sjhb dump_field(tmr, 0); 850162233Sjhb dump_field(tmr, 1); 851162233Sjhb dump_field(tmr, 2); 852162233Sjhb dump_field(tmr, 3); 853162233Sjhb dump_field(tmr, 4); 854162233Sjhb dump_field(tmr, 5); 855162233Sjhb dump_field(tmr, 6); 856162233Sjhb dump_field(tmr, 7); 857162233Sjhb 858162233Sjhb db_printf("IRR Interrupts:\n"); 859162233Sjhb dump_field(irr, 0); 860162233Sjhb dump_field(irr, 1); 861162233Sjhb dump_field(irr, 2); 862162233Sjhb dump_field(irr, 3); 863162233Sjhb dump_field(irr, 4); 864162233Sjhb dump_field(irr, 5); 865162233Sjhb dump_field(irr, 6); 866162233Sjhb dump_field(irr, 7); 867162233Sjhb 868162233Sjhb#undef dump_field 869162233Sjhb} 870151979Sjhb#endif 871151979Sjhb 872151979Sjhb/* 873121986Sjhb * APIC probing support code. This includes code to manage enumerators. 874121986Sjhb */ 875121986Sjhb 876121986Sjhbstatic SLIST_HEAD(, apic_enumerator) enumerators = 877121986Sjhb SLIST_HEAD_INITIALIZER(enumerators); 878121986Sjhbstatic struct apic_enumerator *best_enum; 879121986Sjhb 880121986Sjhbvoid 881121986Sjhbapic_register_enumerator(struct apic_enumerator *enumerator) 882121986Sjhb{ 883121986Sjhb#ifdef INVARIANTS 884121986Sjhb struct apic_enumerator *apic_enum; 885121986Sjhb 886121986Sjhb SLIST_FOREACH(apic_enum, &enumerators, apic_next) { 887121986Sjhb if (apic_enum == enumerator) 888121986Sjhb panic("%s: Duplicate register of %s", __func__, 889121986Sjhb enumerator->apic_name); 890121986Sjhb } 891121986Sjhb#endif 892121986Sjhb SLIST_INSERT_HEAD(&enumerators, enumerator, apic_next); 893121986Sjhb} 894121986Sjhb 895121986Sjhb/* 896123133Sjhb * Probe the APIC enumerators, enumerate CPUs, and initialize the 897123133Sjhb * local APIC. 898121986Sjhb */ 899121986Sjhbstatic void 900121986Sjhbapic_init(void *dummy __unused) 901121986Sjhb{ 902121986Sjhb struct apic_enumerator *enumerator; 903123133Sjhb uint64_t apic_base; 904121986Sjhb int retval, best; 905121986Sjhb 906153383Sjhb /* We only support built in local APICs. */ 907153383Sjhb if (!(cpu_feature & CPUID_APIC)) 908121986Sjhb return; 909121986Sjhb 910123133Sjhb /* Don't probe if APIC mode is disabled. */ 911123133Sjhb if (resource_disabled("apic", 0)) 912123133Sjhb return; 913123133Sjhb 914121986Sjhb /* First, probe all the enumerators to find the best match. */ 915121986Sjhb best_enum = NULL; 916121986Sjhb best = 0; 917121986Sjhb SLIST_FOREACH(enumerator, &enumerators, apic_next) { 918121986Sjhb retval = enumerator->apic_probe(); 919121986Sjhb if (retval > 0) 920121986Sjhb continue; 921121986Sjhb if (best_enum == NULL || best < retval) { 922121986Sjhb best_enum = enumerator; 923121986Sjhb best = retval; 924121986Sjhb } 925121986Sjhb } 926121986Sjhb if (best_enum == NULL) { 927121986Sjhb if (bootverbose) 928121986Sjhb printf("APIC: Could not find any APICs.\n"); 929121986Sjhb return; 930121986Sjhb } 931121986Sjhb 932121986Sjhb if (bootverbose) 933121986Sjhb printf("APIC: Using the %s enumerator.\n", 934121986Sjhb best_enum->apic_name); 935121986Sjhb 936121986Sjhb /* 937121986Sjhb * To work around an errata, we disable the local APIC on some 938121986Sjhb * CPUs during early startup. We need to turn the local APIC back 939121986Sjhb * on on such CPUs now. 940121986Sjhb */ 941121986Sjhb if (cpu == CPU_686 && strcmp(cpu_vendor, "GenuineIntel") == 0 && 942121986Sjhb (cpu_id & 0xff0) == 0x610) { 943121986Sjhb apic_base = rdmsr(MSR_APICBASE); 944121986Sjhb apic_base |= APICBASE_ENABLED; 945121986Sjhb wrmsr(MSR_APICBASE, apic_base); 946121986Sjhb } 947123133Sjhb 948123133Sjhb /* Second, probe the CPU's in the system. */ 949123133Sjhb retval = best_enum->apic_probe_cpus(); 950123133Sjhb if (retval != 0) 951123133Sjhb printf("%s: Failed to probe CPUs: returned %d\n", 952123133Sjhb best_enum->apic_name, retval); 953123133Sjhb 954123133Sjhb /* Third, initialize the local APIC. */ 955121986Sjhb retval = best_enum->apic_setup_local(); 956121986Sjhb if (retval != 0) 957121986Sjhb printf("%s: Failed to setup the local APIC: returned %d\n", 958121986Sjhb best_enum->apic_name, retval); 959123432Sjeff#ifdef SMP 960123432Sjeff /* Last, setup the cpu topology now that we have probed CPUs */ 961123432Sjeff mp_topology(); 962123432Sjeff#endif 963121986Sjhb} 964123133SjhbSYSINIT(apic_init, SI_SUB_CPU, SI_ORDER_FIRST, apic_init, NULL) 965121986Sjhb 966121986Sjhb/* 967121986Sjhb * Setup the I/O APICs. 968121986Sjhb */ 969121986Sjhbstatic void 970121986Sjhbapic_setup_io(void *dummy __unused) 971121986Sjhb{ 972121986Sjhb int retval; 973121986Sjhb 974121986Sjhb if (best_enum == NULL) 975121986Sjhb return; 976121986Sjhb retval = best_enum->apic_setup_io(); 977121986Sjhb if (retval != 0) 978121986Sjhb printf("%s: Failed to setup I/O APICs: returned %d\n", 979121986Sjhb best_enum->apic_name, retval); 980121986Sjhb 981121986Sjhb /* 982121986Sjhb * Finish setting up the local APIC on the BSP once we know how to 983121986Sjhb * properly program the LINT pins. 984121986Sjhb */ 985121986Sjhb lapic_setup(); 986121986Sjhb if (bootverbose) 987121986Sjhb lapic_dump("BSP"); 988121986Sjhb} 989121986SjhbSYSINIT(apic_setup_io, SI_SUB_INTR, SI_ORDER_SECOND, apic_setup_io, NULL) 990121986Sjhb 991121986Sjhb#ifdef SMP 992121986Sjhb/* 993121986Sjhb * Inter Processor Interrupt functions. The lapic_ipi_*() functions are 994139240Sjhb * private to the sys/i386 code. The public interface for the rest of the 995121986Sjhb * kernel is defined in mp_machdep.c. 996121986Sjhb */ 997121986Sjhbint 998121986Sjhblapic_ipi_wait(int delay) 999121986Sjhb{ 1000121986Sjhb int x, incr; 1001121986Sjhb 1002121986Sjhb /* 1003121986Sjhb * Wait delay loops for IPI to be sent. This is highly bogus 1004121986Sjhb * since this is sensitive to CPU clock speed. If delay is 1005121986Sjhb * -1, we wait forever. 1006121986Sjhb */ 1007121986Sjhb if (delay == -1) { 1008121986Sjhb incr = 0; 1009121986Sjhb delay = 1; 1010121986Sjhb } else 1011121986Sjhb incr = 1; 1012121986Sjhb for (x = 0; x < delay; x += incr) { 1013121986Sjhb if ((lapic->icr_lo & APIC_DELSTAT_MASK) == APIC_DELSTAT_IDLE) 1014121986Sjhb return (1); 1015121986Sjhb ia32_pause(); 1016121986Sjhb } 1017121986Sjhb return (0); 1018121986Sjhb} 1019121986Sjhb 1020121986Sjhbvoid 1021121986Sjhblapic_ipi_raw(register_t icrlo, u_int dest) 1022121986Sjhb{ 1023121986Sjhb register_t value, eflags; 1024121986Sjhb 1025121986Sjhb /* XXX: Need more sanity checking of icrlo? */ 1026121986Sjhb KASSERT(lapic != NULL, ("%s called too early", __func__)); 1027121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1028121986Sjhb ("%s: invalid dest field", __func__)); 1029121986Sjhb KASSERT((icrlo & APIC_ICRLO_RESV_MASK) == 0, 1030121986Sjhb ("%s: reserved bits set in ICR LO register", __func__)); 1031121986Sjhb 1032121986Sjhb /* Set destination in ICR HI register if it is being used. */ 1033121986Sjhb eflags = intr_disable(); 1034121986Sjhb if ((icrlo & APIC_DEST_MASK) == APIC_DEST_DESTFLD) { 1035121986Sjhb value = lapic->icr_hi; 1036121986Sjhb value &= ~APIC_ID_MASK; 1037121986Sjhb value |= dest << APIC_ID_SHIFT; 1038121986Sjhb lapic->icr_hi = value; 1039121986Sjhb } 1040121986Sjhb 1041121986Sjhb /* Program the contents of the IPI and dispatch it. */ 1042121986Sjhb value = lapic->icr_lo; 1043121986Sjhb value &= APIC_ICRLO_RESV_MASK; 1044121986Sjhb value |= icrlo; 1045121986Sjhb lapic->icr_lo = value; 1046121986Sjhb intr_restore(eflags); 1047121986Sjhb} 1048121986Sjhb 1049125317Sjeff#define BEFORE_SPIN 1000000 1050121986Sjhb#ifdef DETECT_DEADLOCK 1051121986Sjhb#define AFTER_SPIN 1000 1052121986Sjhb#endif 1053121986Sjhb 1054121986Sjhbvoid 1055121986Sjhblapic_ipi_vectored(u_int vector, int dest) 1056121986Sjhb{ 1057121986Sjhb register_t icrlo, destfield; 1058121986Sjhb 1059121986Sjhb KASSERT((vector & ~APIC_VECTOR_MASK) == 0, 1060121986Sjhb ("%s: invalid vector %d", __func__, vector)); 1061121986Sjhb 1062121986Sjhb icrlo = vector | APIC_DELMODE_FIXED | APIC_DESTMODE_PHY | 1063121986Sjhb APIC_LEVEL_DEASSERT | APIC_TRIGMOD_EDGE; 1064121986Sjhb destfield = 0; 1065121986Sjhb switch (dest) { 1066121986Sjhb case APIC_IPI_DEST_SELF: 1067121986Sjhb icrlo |= APIC_DEST_SELF; 1068121986Sjhb break; 1069121986Sjhb case APIC_IPI_DEST_ALL: 1070121986Sjhb icrlo |= APIC_DEST_ALLISELF; 1071121986Sjhb break; 1072121986Sjhb case APIC_IPI_DEST_OTHERS: 1073121986Sjhb icrlo |= APIC_DEST_ALLESELF; 1074121986Sjhb break; 1075121986Sjhb default: 1076121986Sjhb KASSERT((dest & ~(APIC_ID_MASK >> APIC_ID_SHIFT)) == 0, 1077121986Sjhb ("%s: invalid destination 0x%x", __func__, dest)); 1078121986Sjhb destfield = dest; 1079121986Sjhb } 1080121986Sjhb 1081125317Sjeff /* Wait for an earlier IPI to finish. */ 1082150176Sjhb if (!lapic_ipi_wait(BEFORE_SPIN)) { 1083150176Sjhb if (panicstr != NULL) 1084150176Sjhb return; 1085150176Sjhb else 1086150176Sjhb panic("APIC: Previous IPI is stuck"); 1087150176Sjhb } 1088121986Sjhb 1089121986Sjhb lapic_ipi_raw(icrlo, destfield); 1090121986Sjhb 1091121986Sjhb#ifdef DETECT_DEADLOCK 1092121986Sjhb /* Wait for IPI to be delivered. */ 1093121986Sjhb if (!lapic_ipi_wait(AFTER_SPIN)) { 1094121986Sjhb#ifdef needsattention 1095121986Sjhb /* 1096121986Sjhb * XXX FIXME: 1097121986Sjhb * 1098121986Sjhb * The above function waits for the message to actually be 1099121986Sjhb * delivered. It breaks out after an arbitrary timeout 1100121986Sjhb * since the message should eventually be delivered (at 1101121986Sjhb * least in theory) and that if it wasn't we would catch 1102121986Sjhb * the failure with the check above when the next IPI is 1103121986Sjhb * sent. 1104121986Sjhb * 1105139240Sjhb * We could skip this wait entirely, EXCEPT it probably 1106121986Sjhb * protects us from other routines that assume that the 1107121986Sjhb * message was delivered and acted upon when this function 1108121986Sjhb * returns. 1109121986Sjhb */ 1110121986Sjhb printf("APIC: IPI might be stuck\n"); 1111121986Sjhb#else /* !needsattention */ 1112121986Sjhb /* Wait until mesage is sent without a timeout. */ 1113121986Sjhb while (lapic->icr_lo & APIC_DELSTAT_PEND) 1114121986Sjhb ia32_pause(); 1115121986Sjhb#endif /* needsattention */ 1116121986Sjhb } 1117121986Sjhb#endif /* DETECT_DEADLOCK */ 1118121986Sjhb} 1119121986Sjhb#endif /* SMP */ 1120