1/*- 2 * Copyright 2006-2007 by Juniper Networks. 3 * Copyright 2008 Semihalf. 4 * Copyright 2010 The FreeBSD Foundation 5 * All rights reserved. 6 * 7 * Portions of this software were developed by Semihalf 8 * under sponsorship from the FreeBSD Foundation. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 3. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, 26 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 27 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED 28 * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, 29 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 30 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 31 * SUCH DAMAGE. 32 * 33 * From: FreeBSD: src/sys/powerpc/mpc85xx/pci_ocp.c,v 1.9 2010/03/23 23:46:28 marcel 34 */ 35 36#include <sys/cdefs.h> 37__FBSDID("$FreeBSD$"); 38 39#include <sys/param.h> 40#include <sys/systm.h> 41#include <sys/ktr.h> 42#include <sys/sockio.h> 43#include <sys/mbuf.h> 44#include <sys/malloc.h> 45#include <sys/kernel.h> 46#include <sys/module.h> 47#include <sys/socket.h> 48#include <sys/queue.h> 49#include <sys/bus.h> 50#include <sys/lock.h> 51#include <sys/mutex.h> 52#include <sys/rman.h> 53#include <sys/endian.h> 54 55#include <vm/vm.h> 56#include <vm/pmap.h> 57 58#include <dev/fdt/fdt_common.h> 59#include <dev/ofw/ofw_bus.h> 60#include <dev/ofw/ofw_bus_subr.h> 61#include <dev/pci/pcivar.h> 62#include <dev/pci/pcireg.h> 63#include <dev/pci/pcib_private.h> 64 65#include "ofw_bus_if.h" 66#include "pcib_if.h" 67 68#include <machine/resource.h> 69#include <machine/bus.h> 70#include <machine/intr_machdep.h> 71 72#include <powerpc/mpc85xx/mpc85xx.h> 73 74#define REG_CFG_ADDR 0x0000 75#define CONFIG_ACCESS_ENABLE 0x80000000 76 77#define REG_CFG_DATA 0x0004 78#define REG_INT_ACK 0x0008 79 80#define REG_POTAR(n) (0x0c00 + 0x20 * (n)) 81#define REG_POTEAR(n) (0x0c04 + 0x20 * (n)) 82#define REG_POWBAR(n) (0x0c08 + 0x20 * (n)) 83#define REG_POWAR(n) (0x0c10 + 0x20 * (n)) 84 85#define REG_PITAR(n) (0x0e00 - 0x20 * (n)) 86#define REG_PIWBAR(n) (0x0e08 - 0x20 * (n)) 87#define REG_PIWBEAR(n) (0x0e0c - 0x20 * (n)) 88#define REG_PIWAR(n) (0x0e10 - 0x20 * (n)) 89 90#define REG_PEX_MES_DR 0x0020 91#define REG_PEX_MES_IER 0x0028 92#define REG_PEX_ERR_DR 0x0e00 93#define REG_PEX_ERR_EN 0x0e08 94 95#define PCIR_LTSSM 0x404 96#define LTSSM_STAT_L0 0x16 97 98#define DEVFN(b, s, f) ((b << 16) | (s << 8) | f) 99 100struct fsl_pcib_softc { 101 device_t sc_dev; 102 103 struct rman sc_iomem; 104 bus_addr_t sc_iomem_va; /* Virtual mapping. */ 105 bus_addr_t sc_iomem_size; 106 bus_addr_t sc_iomem_alloc; /* Next allocation. */ 107 int sc_iomem_target; 108 struct rman sc_ioport; 109 bus_addr_t sc_ioport_va; /* Virtual mapping. */ 110 bus_addr_t sc_ioport_size; 111 bus_addr_t sc_ioport_alloc; /* Next allocation. */ 112 int sc_ioport_target; 113 114 struct resource *sc_res; 115 bus_space_handle_t sc_bsh; 116 bus_space_tag_t sc_bst; 117 int sc_rid; 118 119 int sc_busnr; 120 int sc_pcie; 121 uint8_t sc_pcie_capreg; /* PCI-E Capability Reg Set */ 122 123 /* Devices that need special attention. */ 124 int sc_devfn_tundra; 125 int sc_devfn_via_ide; 126 127 struct fdt_pci_intr sc_intr_info; 128}; 129 130/* Local forward declerations. */ 131static uint32_t fsl_pcib_cfgread(struct fsl_pcib_softc *, u_int, u_int, u_int, 132 u_int, int); 133static void fsl_pcib_cfgwrite(struct fsl_pcib_softc *, u_int, u_int, u_int, 134 u_int, uint32_t, int); 135static int fsl_pcib_decode_win(phandle_t, struct fsl_pcib_softc *); 136static void fsl_pcib_err_init(device_t); 137static void fsl_pcib_inbound(struct fsl_pcib_softc *, int, int, u_long, 138 u_long, u_long); 139static int fsl_pcib_init(struct fsl_pcib_softc *, int, int); 140static int fsl_pcib_intr_info(phandle_t, struct fsl_pcib_softc *); 141static int fsl_pcib_set_range(struct fsl_pcib_softc *, int, int, u_long, 142 u_long); 143static void fsl_pcib_outbound(struct fsl_pcib_softc *, int, int, u_long, 144 u_long, u_long); 145 146/* Forward declerations. */ 147static int fsl_pcib_attach(device_t); 148static int fsl_pcib_detach(device_t); 149static int fsl_pcib_probe(device_t); 150 151static struct resource *fsl_pcib_alloc_resource(device_t, device_t, int, int *, 152 u_long, u_long, u_long, u_int); 153static int fsl_pcib_read_ivar(device_t, device_t, int, uintptr_t *); 154static int fsl_pcib_release_resource(device_t, device_t, int, int, 155 struct resource *); 156static int fsl_pcib_write_ivar(device_t, device_t, int, uintptr_t); 157 158static int fsl_pcib_maxslots(device_t); 159static uint32_t fsl_pcib_read_config(device_t, u_int, u_int, u_int, u_int, int); 160static void fsl_pcib_write_config(device_t, u_int, u_int, u_int, u_int, 161 uint32_t, int); 162 163/* Configuration r/w mutex. */ 164struct mtx pcicfg_mtx; 165static int mtx_initialized = 0; 166 167/* 168 * Bus interface definitions. 169 */ 170static device_method_t fsl_pcib_methods[] = { 171 /* Device interface */ 172 DEVMETHOD(device_probe, fsl_pcib_probe), 173 DEVMETHOD(device_attach, fsl_pcib_attach), 174 DEVMETHOD(device_detach, fsl_pcib_detach), 175 176 /* Bus interface */ 177 DEVMETHOD(bus_read_ivar, fsl_pcib_read_ivar), 178 DEVMETHOD(bus_write_ivar, fsl_pcib_write_ivar), 179 DEVMETHOD(bus_alloc_resource, fsl_pcib_alloc_resource), 180 DEVMETHOD(bus_release_resource, fsl_pcib_release_resource), 181 DEVMETHOD(bus_activate_resource, bus_generic_activate_resource), 182 DEVMETHOD(bus_deactivate_resource, bus_generic_deactivate_resource), 183 DEVMETHOD(bus_setup_intr, bus_generic_setup_intr), 184 DEVMETHOD(bus_teardown_intr, bus_generic_teardown_intr), 185 186 /* pcib interface */ 187 DEVMETHOD(pcib_maxslots, fsl_pcib_maxslots), 188 DEVMETHOD(pcib_read_config, fsl_pcib_read_config), 189 DEVMETHOD(pcib_write_config, fsl_pcib_write_config), 190 DEVMETHOD(pcib_route_interrupt, pcib_route_interrupt), 191 192 /* OFW bus interface */ 193 DEVMETHOD(ofw_bus_get_compat, ofw_bus_gen_get_compat), 194 DEVMETHOD(ofw_bus_get_model, ofw_bus_gen_get_model), 195 DEVMETHOD(ofw_bus_get_name, ofw_bus_gen_get_name), 196 DEVMETHOD(ofw_bus_get_node, ofw_bus_gen_get_node), 197 DEVMETHOD(ofw_bus_get_type, ofw_bus_gen_get_type), 198 199 DEVMETHOD_END 200}; 201 202static driver_t fsl_pcib_driver = { 203 "pcib", 204 fsl_pcib_methods, 205 sizeof(struct fsl_pcib_softc), 206}; 207 208devclass_t pcib_devclass; 209 210DRIVER_MODULE(pcib, fdtbus, fsl_pcib_driver, pcib_devclass, 0, 0); 211 212static int 213fsl_pcib_probe(device_t dev) 214{ 215 phandle_t node; 216 217 node = ofw_bus_get_node(dev); 218 if (!fdt_is_type(node, "pci")) 219 return (ENXIO); 220 221 if (!(fdt_is_compatible(node, "fsl,mpc8540-pci") || 222 fdt_is_compatible(node, "fsl,mpc8548-pcie"))) 223 return (ENXIO); 224 225 device_set_desc(dev, "Freescale Integrated PCI/PCI-E Controller"); 226 return (BUS_PROBE_DEFAULT); 227} 228 229static int 230fsl_pcib_attach(device_t dev) 231{ 232 struct fsl_pcib_softc *sc; 233 phandle_t node; 234 uint32_t cfgreg; 235 int maxslot; 236 uint8_t ltssm, capptr; 237 238 sc = device_get_softc(dev); 239 sc->sc_dev = dev; 240 241 sc->sc_rid = 0; 242 sc->sc_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &sc->sc_rid, 243 RF_ACTIVE); 244 if (sc->sc_res == NULL) { 245 device_printf(dev, "could not map I/O memory\n"); 246 return (ENXIO); 247 } 248 sc->sc_bst = rman_get_bustag(sc->sc_res); 249 sc->sc_bsh = rman_get_bushandle(sc->sc_res); 250 sc->sc_busnr = 0; 251 252 if (!mtx_initialized) { 253 mtx_init(&pcicfg_mtx, "pcicfg", NULL, MTX_SPIN); 254 mtx_initialized = 1; 255 } 256 257 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_VENDOR, 2); 258 if (cfgreg != 0x1057 && cfgreg != 0x1957) 259 goto err; 260 261 capptr = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_CAP_PTR, 1); 262 while (capptr != 0) { 263 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, capptr, 2); 264 switch (cfgreg & 0xff) { 265 case PCIY_PCIX: 266 break; 267 case PCIY_EXPRESS: 268 sc->sc_pcie = 1; 269 sc->sc_pcie_capreg = capptr; 270 break; 271 } 272 capptr = (cfgreg >> 8) & 0xff; 273 } 274 275 node = ofw_bus_get_node(dev); 276 /* 277 * Get PCI interrupt info. 278 */ 279 if (fsl_pcib_intr_info(node, sc) != 0) { 280 device_printf(dev, "could not retrieve interrupt info\n"); 281 goto err; 282 } 283 284 /* 285 * Configure decode windows for PCI(E) access. 286 */ 287 if (fsl_pcib_decode_win(node, sc) != 0) 288 goto err; 289 290 cfgreg = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_COMMAND, 2); 291 cfgreg |= PCIM_CMD_SERRESPEN | PCIM_CMD_BUSMASTEREN | PCIM_CMD_MEMEN | 292 PCIM_CMD_PORTEN; 293 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_COMMAND, cfgreg, 2); 294 295 sc->sc_devfn_tundra = -1; 296 sc->sc_devfn_via_ide = -1; 297 298 299 /* 300 * Scan bus using firmware configured, 0 based bus numbering. 301 */ 302 sc->sc_busnr = 0; 303 maxslot = (sc->sc_pcie) ? 0 : PCI_SLOTMAX; 304 fsl_pcib_init(sc, sc->sc_busnr, maxslot); 305 306 if (sc->sc_pcie) { 307 ltssm = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_LTSSM, 1); 308 if (ltssm < LTSSM_STAT_L0) { 309 if (bootverbose) 310 printf("PCI %d: no PCIE link, skipping\n", 311 device_get_unit(dev)); 312 return (0); 313 } 314 } 315 316 fsl_pcib_err_init(dev); 317 318 device_add_child(dev, "pci", -1); 319 return (bus_generic_attach(dev)); 320 321err: 322 bus_release_resource(dev, SYS_RES_MEMORY, sc->sc_rid, sc->sc_res); 323 return (ENXIO); 324} 325 326static uint32_t 327fsl_pcib_cfgread(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 328 u_int reg, int bytes) 329{ 330 uint32_t addr, data; 331 332 if (bus == sc->sc_busnr - 1) 333 bus = 0; 334 335 addr = CONFIG_ACCESS_ENABLE; 336 addr |= (bus & 0xff) << 16; 337 addr |= (slot & 0x1f) << 11; 338 addr |= (func & 0x7) << 8; 339 addr |= reg & 0xfc; 340 if (sc->sc_pcie) 341 addr |= (reg & 0xf00) << 16; 342 343 mtx_lock_spin(&pcicfg_mtx); 344 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 345 346 switch (bytes) { 347 case 1: 348 data = bus_space_read_1(sc->sc_bst, sc->sc_bsh, 349 REG_CFG_DATA + (reg & 3)); 350 break; 351 case 2: 352 data = le16toh(bus_space_read_2(sc->sc_bst, sc->sc_bsh, 353 REG_CFG_DATA + (reg & 2))); 354 break; 355 case 4: 356 data = le32toh(bus_space_read_4(sc->sc_bst, sc->sc_bsh, 357 REG_CFG_DATA)); 358 break; 359 default: 360 data = ~0; 361 break; 362 } 363 mtx_unlock_spin(&pcicfg_mtx); 364 return (data); 365} 366 367static void 368fsl_pcib_cfgwrite(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 369 u_int reg, uint32_t data, int bytes) 370{ 371 uint32_t addr; 372 373 if (bus == sc->sc_busnr - 1) 374 bus = 0; 375 376 addr = CONFIG_ACCESS_ENABLE; 377 addr |= (bus & 0xff) << 16; 378 addr |= (slot & 0x1f) << 11; 379 addr |= (func & 0x7) << 8; 380 addr |= reg & 0xfc; 381 if (sc->sc_pcie) 382 addr |= (reg & 0xf00) << 16; 383 384 mtx_lock_spin(&pcicfg_mtx); 385 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_CFG_ADDR, addr); 386 387 switch (bytes) { 388 case 1: 389 bus_space_write_1(sc->sc_bst, sc->sc_bsh, 390 REG_CFG_DATA + (reg & 3), data); 391 break; 392 case 2: 393 bus_space_write_2(sc->sc_bst, sc->sc_bsh, 394 REG_CFG_DATA + (reg & 2), htole16(data)); 395 break; 396 case 4: 397 bus_space_write_4(sc->sc_bst, sc->sc_bsh, 398 REG_CFG_DATA, htole32(data)); 399 break; 400 } 401 mtx_unlock_spin(&pcicfg_mtx); 402} 403 404#if 0 405static void 406dump(struct fsl_pcib_softc *sc) 407{ 408 unsigned int i; 409 410#define RD(o) bus_space_read_4(sc->sc_bst, sc->sc_bsh, o) 411 for (i = 0; i < 5; i++) { 412 printf("POTAR%u =0x%08x\n", i, RD(REG_POTAR(i))); 413 printf("POTEAR%u =0x%08x\n", i, RD(REG_POTEAR(i))); 414 printf("POWBAR%u =0x%08x\n", i, RD(REG_POWBAR(i))); 415 printf("POWAR%u =0x%08x\n", i, RD(REG_POWAR(i))); 416 } 417 printf("\n"); 418 for (i = 1; i < 4; i++) { 419 printf("PITAR%u =0x%08x\n", i, RD(REG_PITAR(i))); 420 printf("PIWBAR%u =0x%08x\n", i, RD(REG_PIWBAR(i))); 421 printf("PIWBEAR%u=0x%08x\n", i, RD(REG_PIWBEAR(i))); 422 printf("PIWAR%u =0x%08x\n", i, RD(REG_PIWAR(i))); 423 } 424 printf("\n"); 425#undef RD 426 427 for (i = 0; i < 0x48; i += 4) { 428 printf("cfg%02x=0x%08x\n", i, fsl_pcib_cfgread(sc, 0, 0, 0, 429 i, 4)); 430 } 431} 432#endif 433 434static int 435fsl_pcib_maxslots(device_t dev) 436{ 437 struct fsl_pcib_softc *sc = device_get_softc(dev); 438 439 return ((sc->sc_pcie) ? 0 : PCI_SLOTMAX); 440} 441 442static uint32_t 443fsl_pcib_read_config(device_t dev, u_int bus, u_int slot, u_int func, 444 u_int reg, int bytes) 445{ 446 struct fsl_pcib_softc *sc = device_get_softc(dev); 447 u_int devfn; 448 449 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 450 return (~0); 451 devfn = DEVFN(bus, slot, func); 452 if (devfn == sc->sc_devfn_tundra) 453 return (~0); 454 if (devfn == sc->sc_devfn_via_ide && reg == PCIR_INTPIN) 455 return (1); 456 return (fsl_pcib_cfgread(sc, bus, slot, func, reg, bytes)); 457} 458 459static void 460fsl_pcib_write_config(device_t dev, u_int bus, u_int slot, u_int func, 461 u_int reg, uint32_t val, int bytes) 462{ 463 struct fsl_pcib_softc *sc = device_get_softc(dev); 464 465 if (bus == sc->sc_busnr && !sc->sc_pcie && slot < 10) 466 return; 467 fsl_pcib_cfgwrite(sc, bus, slot, func, reg, val, bytes); 468} 469 470static void 471fsl_pcib_init_via(struct fsl_pcib_softc *sc, uint16_t device, int bus, 472 int slot, int fn) 473{ 474 475 if (device == 0x0686) { 476 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x52, 0x34, 1); 477 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x77, 0x00, 1); 478 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x83, 0x98, 1); 479 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x85, 0x03, 1); 480 } else if (device == 0x0571) { 481 sc->sc_devfn_via_ide = DEVFN(bus, slot, fn); 482 fsl_pcib_write_config(sc->sc_dev, bus, slot, fn, 0x40, 0x0b, 1); 483 } 484} 485 486static int 487fsl_pcib_init_bar(struct fsl_pcib_softc *sc, int bus, int slot, int func, 488 int barno) 489{ 490 bus_addr_t *allocp; 491 uint32_t addr, mask, size; 492 int reg, width; 493 494 reg = PCIR_BAR(barno); 495 496 if (DEVFN(bus, slot, func) == sc->sc_devfn_via_ide) { 497 switch (barno) { 498 case 0: addr = 0x1f0; break; 499 case 1: addr = 0x3f4; break; 500 case 2: addr = 0x170; break; 501 case 3: addr = 0x374; break; 502 case 4: addr = 0xcc0; break; 503 default: return (1); 504 } 505 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 506 return (1); 507 } 508 509 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, ~0, 4); 510 size = fsl_pcib_read_config(sc->sc_dev, bus, slot, func, reg, 4); 511 if (size == 0) 512 return (1); 513 width = ((size & 7) == 4) ? 2 : 1; 514 515 if (size & 1) { /* I/O port */ 516 allocp = &sc->sc_ioport_alloc; 517 size &= ~3; 518 if ((size & 0xffff0000) == 0) 519 size |= 0xffff0000; 520 } else { /* memory */ 521 allocp = &sc->sc_iomem_alloc; 522 size &= ~15; 523 } 524 mask = ~size; 525 size = mask + 1; 526 /* Sanity check (must be a power of 2). */ 527 if (size & mask) 528 return (width); 529 530 addr = (*allocp + mask) & ~mask; 531 *allocp = addr + size; 532 533 if (bootverbose) 534 printf("PCI %u:%u:%u:%u: reg %x: size=%08x: addr=%08x\n", 535 device_get_unit(sc->sc_dev), bus, slot, func, reg, 536 size, addr); 537 538 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg, addr, 4); 539 if (width == 2) 540 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, reg + 4, 541 0, 4); 542 return (width); 543} 544 545static u_int 546fsl_pcib_route_int(struct fsl_pcib_softc *sc, u_int bus, u_int slot, u_int func, 547 u_int intpin) 548{ 549 int err, unit; 550 u_int devfn, intline; 551 552 unit = device_get_unit(sc->sc_dev); 553 554 devfn = DEVFN(bus, slot, func); 555 if (devfn == sc->sc_devfn_via_ide) 556 intline = MAP_IRQ(0, 14); 557 else if (devfn == sc->sc_devfn_via_ide + 1) 558 intline = MAP_IRQ(0, 10); 559 else if (devfn == sc->sc_devfn_via_ide + 2) 560 intline = MAP_IRQ(0, 10); 561 else { 562 if (intpin != 0) 563 err = fdt_pci_route_intr(bus, slot, func, intpin, 564 &sc->sc_intr_info, &intline); 565 else 566 intline = 0xff; 567 } 568 569 if (bootverbose) 570 printf("PCI %u:%u:%u:%u: intpin %u: intline=%u\n", 571 unit, bus, slot, func, intpin, intline); 572 573 return (intline); 574} 575 576static int 577fsl_pcib_init(struct fsl_pcib_softc *sc, int bus, int maxslot) 578{ 579 int secbus; 580 int old_pribus, old_secbus, old_subbus; 581 int new_pribus, new_secbus, new_subbus; 582 int slot, func, maxfunc; 583 int bar, maxbar; 584 uint16_t vendor, device; 585 uint8_t command, hdrtype, class, subclass; 586 uint8_t intline, intpin; 587 588 secbus = bus; 589 for (slot = 0; slot <= maxslot; slot++) { 590 maxfunc = 0; 591 for (func = 0; func <= maxfunc; func++) { 592 hdrtype = fsl_pcib_read_config(sc->sc_dev, bus, slot, 593 func, PCIR_HDRTYPE, 1); 594 595 if ((hdrtype & PCIM_HDRTYPE) > PCI_MAXHDRTYPE) 596 continue; 597 598 if (func == 0 && (hdrtype & PCIM_MFDEV)) 599 maxfunc = PCI_FUNCMAX; 600 601 vendor = fsl_pcib_read_config(sc->sc_dev, bus, slot, 602 func, PCIR_VENDOR, 2); 603 device = fsl_pcib_read_config(sc->sc_dev, bus, slot, 604 func, PCIR_DEVICE, 2); 605 606 if (vendor == 0x1957 && device == 0x3fff) { 607 sc->sc_devfn_tundra = DEVFN(bus, slot, func); 608 continue; 609 } 610 611 command = fsl_pcib_read_config(sc->sc_dev, bus, slot, 612 func, PCIR_COMMAND, 1); 613 command &= ~(PCIM_CMD_MEMEN | PCIM_CMD_PORTEN); 614 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 615 PCIR_COMMAND, command, 1); 616 617 if (vendor == 0x1106) 618 fsl_pcib_init_via(sc, device, bus, slot, func); 619 620 /* Program the base address registers. */ 621 maxbar = (hdrtype & PCIM_HDRTYPE) ? 1 : 6; 622 bar = 0; 623 while (bar < maxbar) 624 bar += fsl_pcib_init_bar(sc, bus, slot, func, 625 bar); 626 627 /* Perform interrupt routing. */ 628 intpin = fsl_pcib_read_config(sc->sc_dev, bus, slot, 629 func, PCIR_INTPIN, 1); 630 intline = fsl_pcib_route_int(sc, bus, slot, func, 631 intpin); 632 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 633 PCIR_INTLINE, intline, 1); 634 635 command |= PCIM_CMD_MEMEN | PCIM_CMD_PORTEN; 636 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 637 PCIR_COMMAND, command, 1); 638 639 /* 640 * Handle PCI-PCI bridges 641 */ 642 class = fsl_pcib_read_config(sc->sc_dev, bus, slot, 643 func, PCIR_CLASS, 1); 644 subclass = fsl_pcib_read_config(sc->sc_dev, bus, slot, 645 func, PCIR_SUBCLASS, 1); 646 647 /* Allow only proper PCI-PCI briges */ 648 if (class != PCIC_BRIDGE) 649 continue; 650 if (subclass != PCIS_BRIDGE_PCI) 651 continue; 652 653 secbus++; 654 655 /* Program I/O decoder. */ 656 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 657 PCIR_IOBASEL_1, sc->sc_ioport.rm_start >> 8, 1); 658 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 659 PCIR_IOLIMITL_1, sc->sc_ioport.rm_end >> 8, 1); 660 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 661 PCIR_IOBASEH_1, sc->sc_ioport.rm_start >> 16, 2); 662 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 663 PCIR_IOLIMITH_1, sc->sc_ioport.rm_end >> 16, 2); 664 665 /* Program (non-prefetchable) memory decoder. */ 666 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 667 PCIR_MEMBASE_1, sc->sc_iomem.rm_start >> 16, 2); 668 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 669 PCIR_MEMLIMIT_1, sc->sc_iomem.rm_end >> 16, 2); 670 671 /* Program prefetchable memory decoder. */ 672 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 673 PCIR_PMBASEL_1, 0x0010, 2); 674 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 675 PCIR_PMLIMITL_1, 0x000f, 2); 676 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 677 PCIR_PMBASEH_1, 0x00000000, 4); 678 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 679 PCIR_PMLIMITH_1, 0x00000000, 4); 680 681 /* Read currect bus register configuration */ 682 old_pribus = fsl_pcib_read_config(sc->sc_dev, bus, 683 slot, func, PCIR_PRIBUS_1, 1); 684 old_secbus = fsl_pcib_read_config(sc->sc_dev, bus, 685 slot, func, PCIR_SECBUS_1, 1); 686 old_subbus = fsl_pcib_read_config(sc->sc_dev, bus, 687 slot, func, PCIR_SUBBUS_1, 1); 688 689 if (bootverbose) 690 printf("PCI: reading firmware bus numbers for " 691 "secbus = %d (bus/sec/sub) = (%d/%d/%d)\n", 692 secbus, old_pribus, old_secbus, old_subbus); 693 694 new_pribus = bus; 695 new_secbus = secbus; 696 697 secbus = fsl_pcib_init(sc, secbus, 698 (subclass == PCIS_BRIDGE_PCI) ? PCI_SLOTMAX : 0); 699 700 new_subbus = secbus; 701 702 if (bootverbose) 703 printf("PCI: translate firmware bus numbers " 704 "for secbus %d (%d/%d/%d) -> (%d/%d/%d)\n", 705 secbus, old_pribus, old_secbus, old_subbus, 706 new_pribus, new_secbus, new_subbus); 707 708 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 709 PCIR_PRIBUS_1, new_pribus, 1); 710 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 711 PCIR_SECBUS_1, new_secbus, 1); 712 fsl_pcib_write_config(sc->sc_dev, bus, slot, func, 713 PCIR_SUBBUS_1, new_subbus, 1); 714 } 715 } 716 717 return (secbus); 718} 719 720static void 721fsl_pcib_inbound(struct fsl_pcib_softc *sc, int wnd, int tgt, u_long start, 722 u_long size, u_long pci_start) 723{ 724 uint32_t attr, bar, tar; 725 726 KASSERT(wnd > 0, ("%s: inbound window 0 is invalid", __func__)); 727 728 switch (tgt) { 729 /* XXX OCP85XX_TGTIF_RAM2, OCP85XX_TGTIF_RAM_INTL should be handled */ 730 case OCP85XX_TGTIF_RAM1: 731 attr = 0xa0f55000 | (ffsl(size) - 2); 732 break; 733 default: 734 attr = 0; 735 break; 736 } 737 tar = start >> 12; 738 bar = pci_start >> 12; 739 740 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PITAR(wnd), tar); 741 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBEAR(wnd), 0); 742 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWBAR(wnd), bar); 743 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PIWAR(wnd), attr); 744} 745 746static void 747fsl_pcib_outbound(struct fsl_pcib_softc *sc, int wnd, int res, u_long start, 748 u_long size, u_long pci_start) 749{ 750 uint32_t attr, bar, tar; 751 752 switch (res) { 753 case SYS_RES_MEMORY: 754 attr = 0x80044000 | (ffsl(size) - 2); 755 break; 756 case SYS_RES_IOPORT: 757 attr = 0x80088000 | (ffsl(size) - 2); 758 break; 759 default: 760 attr = 0x0004401f; 761 break; 762 } 763 bar = start >> 12; 764 tar = pci_start >> 12; 765 766 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTAR(wnd), tar); 767 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POTEAR(wnd), 0); 768 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWBAR(wnd), bar); 769 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_POWAR(wnd), attr); 770} 771 772static int 773fsl_pcib_set_range(struct fsl_pcib_softc *sc, int type, int wnd, u_long start, 774 u_long size) 775{ 776 struct rman *rm; 777 u_long end, alloc; 778 bus_addr_t pci_start, pci_end; 779 bus_addr_t *vap, *allocp; 780 int error; 781 782 end = start + size - 1; 783 784 switch (type) { 785 case SYS_RES_IOPORT: 786 rm = &sc->sc_ioport; 787 pci_start = 0x0000; 788 pci_end = 0xffff; 789 alloc = 0x1000; 790 vap = &sc->sc_ioport_va; 791 allocp = &sc->sc_ioport_alloc; 792 break; 793 case SYS_RES_MEMORY: 794 rm = &sc->sc_iomem; 795 pci_start = start; 796 pci_end = end; 797 alloc = 0; 798 vap = &sc->sc_iomem_va; 799 allocp = &sc->sc_iomem_alloc; 800 break; 801 default: 802 return (EINVAL); 803 } 804 805 rm->rm_type = RMAN_ARRAY; 806 rm->rm_start = pci_start; 807 rm->rm_end = pci_end; 808 error = rman_init(rm); 809 if (error) 810 return (error); 811 812 error = rman_manage_region(rm, pci_start, pci_end); 813 if (error) { 814 rman_fini(rm); 815 return (error); 816 } 817 818 *allocp = pci_start + alloc; 819 *vap = (uintptr_t)pmap_mapdev(start, size); 820 fsl_pcib_outbound(sc, wnd, type, start, size, pci_start); 821 return (0); 822} 823 824static void 825fsl_pcib_err_init(device_t dev) 826{ 827 struct fsl_pcib_softc *sc; 828 uint16_t sec_stat, dsr; 829 uint32_t dcr, err_en; 830 831 sc = device_get_softc(dev); 832 833 sec_stat = fsl_pcib_cfgread(sc, 0, 0, 0, PCIR_SECSTAT_1, 2); 834 if (sec_stat) 835 fsl_pcib_cfgwrite(sc, 0, 0, 0, PCIR_SECSTAT_1, 0xffff, 2); 836 if (sc->sc_pcie) { 837 /* Clear error bits */ 838 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_IER, 839 0xffffffff); 840 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_MES_DR, 841 0xffffffff); 842 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_DR, 843 0xffffffff); 844 845 dsr = fsl_pcib_cfgread(sc, 0, 0, 0, 846 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 2); 847 if (dsr) 848 fsl_pcib_cfgwrite(sc, 0, 0, 0, 849 sc->sc_pcie_capreg + PCIER_DEVICE_STA, 850 0xffff, 2); 851 852 /* Enable all errors reporting */ 853 err_en = 0x00bfff00; 854 bus_space_write_4(sc->sc_bst, sc->sc_bsh, REG_PEX_ERR_EN, 855 err_en); 856 857 /* Enable error reporting: URR, FER, NFER */ 858 dcr = fsl_pcib_cfgread(sc, 0, 0, 0, 859 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, 4); 860 dcr |= PCIEM_CTL_URR_ENABLE | PCIEM_CTL_FER_ENABLE | 861 PCIEM_CTL_NFER_ENABLE; 862 fsl_pcib_cfgwrite(sc, 0, 0, 0, 863 sc->sc_pcie_capreg + PCIER_DEVICE_CTL, dcr, 4); 864 } 865} 866 867static int 868fsl_pcib_detach(device_t dev) 869{ 870 871 if (mtx_initialized) { 872 mtx_destroy(&pcicfg_mtx); 873 mtx_initialized = 0; 874 } 875 return (bus_generic_detach(dev)); 876} 877 878static struct resource * 879fsl_pcib_alloc_resource(device_t dev, device_t child, int type, int *rid, 880 u_long start, u_long end, u_long count, u_int flags) 881{ 882 struct fsl_pcib_softc *sc = device_get_softc(dev); 883 struct rman *rm; 884 struct resource *res; 885 bus_addr_t va; 886 887 switch (type) { 888 case SYS_RES_IOPORT: 889 rm = &sc->sc_ioport; 890 va = sc->sc_ioport_va; 891 break; 892 case SYS_RES_MEMORY: 893 rm = &sc->sc_iomem; 894 va = sc->sc_iomem_va; 895 break; 896 case SYS_RES_IRQ: 897 if (start < 16) { 898 device_printf(dev, "%s requested ISA interrupt %lu\n", 899 device_get_nameunit(child), start); 900 } 901 flags |= RF_SHAREABLE; 902 return (BUS_ALLOC_RESOURCE(device_get_parent(dev), child, 903 type, rid, start, end, count, flags)); 904 default: 905 return (NULL); 906 } 907 908 res = rman_reserve_resource(rm, start, end, count, flags, child); 909 if (res == NULL) 910 return (NULL); 911 912 rman_set_bustag(res, &bs_le_tag); 913 rman_set_bushandle(res, va + rman_get_start(res) - rm->rm_start); 914 return (res); 915} 916 917static int 918fsl_pcib_release_resource(device_t dev, device_t child, int type, int rid, 919 struct resource *res) 920{ 921 922 return (rman_release_resource(res)); 923} 924 925static int 926fsl_pcib_read_ivar(device_t dev, device_t child, int which, uintptr_t *result) 927{ 928 struct fsl_pcib_softc *sc = device_get_softc(dev); 929 930 switch (which) { 931 case PCIB_IVAR_BUS: 932 *result = sc->sc_busnr; 933 return (0); 934 case PCIB_IVAR_DOMAIN: 935 *result = device_get_unit(dev); 936 return (0); 937 } 938 return (ENOENT); 939} 940 941static int 942fsl_pcib_write_ivar(device_t dev, device_t child, int which, uintptr_t value) 943{ 944 struct fsl_pcib_softc *sc = device_get_softc(dev); 945 946 switch (which) { 947 case PCIB_IVAR_BUS: 948 sc->sc_busnr = value; 949 return (0); 950 } 951 return (ENOENT); 952} 953 954static int 955fsl_pcib_intr_info(phandle_t node, struct fsl_pcib_softc *sc) 956{ 957 int error; 958 959 if ((error = fdt_pci_intr_info(node, &sc->sc_intr_info)) != 0) 960 return (error); 961 962 return (0); 963} 964 965static int 966fsl_pcib_decode_win(phandle_t node, struct fsl_pcib_softc *sc) 967{ 968 struct fdt_pci_range io_space, mem_space; 969 device_t dev; 970 int error; 971 972 dev = sc->sc_dev; 973 974 if ((error = fdt_pci_ranges(node, &io_space, &mem_space)) != 0) { 975 device_printf(dev, "could not retrieve 'ranges' data\n"); 976 return (error); 977 } 978 979 /* 980 * Configure LAW decode windows. 981 */ 982 error = law_pci_target(sc->sc_res, &sc->sc_iomem_target, 983 &sc->sc_ioport_target); 984 if (error != 0) { 985 device_printf(dev, "could not retrieve PCI LAW target info\n"); 986 return (error); 987 } 988 error = law_enable(sc->sc_iomem_target, mem_space.base_parent, 989 mem_space.len); 990 if (error != 0) { 991 device_printf(dev, "could not program LAW for PCI MEM range\n"); 992 return (error); 993 } 994 error = law_enable(sc->sc_ioport_target, io_space.base_parent, 995 io_space.len); 996 if (error != 0) { 997 device_printf(dev, "could not program LAW for PCI IO range\n"); 998 return (error); 999 } 1000 1001 /* 1002 * Set outbout and inbound windows. 1003 */ 1004 fsl_pcib_outbound(sc, 0, -1, 0, 0, 0); 1005 if ((error = fsl_pcib_set_range(sc, SYS_RES_MEMORY, 1, 1006 mem_space.base_parent, mem_space.len)) != 0) 1007 return (error); 1008 if ((error = fsl_pcib_set_range(sc, SYS_RES_IOPORT, 2, 1009 io_space.base_parent, io_space.len)) != 0) 1010 return (error); 1011 1012 fsl_pcib_outbound(sc, 3, -1, 0, 0, 0); 1013 fsl_pcib_outbound(sc, 4, -1, 0, 0, 0); 1014 1015 fsl_pcib_inbound(sc, 1, -1, 0, 0, 0); 1016 fsl_pcib_inbound(sc, 2, -1, 0, 0, 0); 1017 fsl_pcib_inbound(sc, 3, OCP85XX_TGTIF_RAM1, 0, 1018 2U * 1024U * 1024U * 1024U, 0); 1019 1020 return (0); 1021} 1022