1219820Sjeff/* 2219820Sjeff * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3219820Sjeff * 4219820Sjeff * This software is available to you under a choice of one of two 5219820Sjeff * licenses. You may choose to be licensed under the terms of the GNU 6219820Sjeff * General Public License (GPL) Version 2, available from the file 7219820Sjeff * COPYING in the main directory of this source tree, or the 8219820Sjeff * OpenIB.org BSD license below: 9219820Sjeff * 10219820Sjeff * Redistribution and use in source and binary forms, with or 11219820Sjeff * without modification, are permitted provided that the following 12219820Sjeff * conditions are met: 13219820Sjeff * 14219820Sjeff * - Redistributions of source code must retain the above 15219820Sjeff * copyright notice, this list of conditions and the following 16219820Sjeff * disclaimer. 17219820Sjeff * 18219820Sjeff * - Redistributions in binary form must reproduce the above 19219820Sjeff * copyright notice, this list of conditions and the following 20219820Sjeff * disclaimer in the documentation and/or other materials 21219820Sjeff * provided with the distribution. 22219820Sjeff * 23219820Sjeff * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24219820Sjeff * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25219820Sjeff * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26219820Sjeff * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27219820Sjeff * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28219820Sjeff * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29219820Sjeff * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30219820Sjeff * SOFTWARE. 31219820Sjeff */ 32219820Sjeff 33219820Sjeff#ifndef MLX4_DEVICE_H 34219820Sjeff#define MLX4_DEVICE_H 35219820Sjeff 36219820Sjeff#include <linux/pci.h> 37219820Sjeff#include <linux/completion.h> 38219820Sjeff#include <linux/radix-tree.h> 39219820Sjeff 40219820Sjeff#include <asm/atomic.h> 41219820Sjeff 42219820Sjeff#include <linux/mlx4/driver.h> 43219820Sjeff 44219820Sjeffenum { 45219820Sjeff MLX4_FLAG_MSI_X = 1 << 0, 46219820Sjeff MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 47219820Sjeff}; 48219820Sjeff 49219820Sjeffenum { 50219820Sjeff MLX4_MAX_PORTS = 2 51219820Sjeff}; 52219820Sjeff 53219820Sjeffenum { 54219820Sjeff MLX4_BOARD_ID_LEN = 64 55219820Sjeff}; 56219820Sjeff 57219820Sjeffenum { 58219820Sjeff MLX4_DEV_CAP_FLAG_RC = 1 << 0, 59219820Sjeff MLX4_DEV_CAP_FLAG_UC = 1 << 1, 60219820Sjeff MLX4_DEV_CAP_FLAG_UD = 1 << 2, 61219820Sjeff MLX4_DEV_CAP_FLAG_XRC = 1 << 3, 62219820Sjeff MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, 63219820Sjeff MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, 64219820Sjeff MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, 65219820Sjeff MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, 66219820Sjeff MLX4_DEV_CAP_FLAG_DPDP = 1 << 12, 67219820Sjeff MLX4_DEV_CAP_FLAG_RAW_ETY = 1 << 13, 68219820Sjeff MLX4_DEV_CAP_FLAG_BLH = 1 << 15, 69219820Sjeff MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, 70219820Sjeff MLX4_DEV_CAP_FLAG_APM = 1 << 17, 71219820Sjeff MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, 72219820Sjeff MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, 73219820Sjeff MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, 74219820Sjeff MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21, 75219820Sjeff MLX4_DEV_CAP_FLAG_IBOE = 1 << 30, 76219820Sjeff MLX4_DEV_CAP_FLAG_FC_T11 = 1 << 31 77219820Sjeff}; 78219820Sjeff 79219820Sjeffenum { 80219820Sjeff MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 81219820Sjeff MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 82219820Sjeff MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 83219820Sjeff MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 84219820Sjeff MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 85219820Sjeff}; 86219820Sjeff 87219820Sjeffenum mlx4_event { 88219820Sjeff MLX4_EVENT_TYPE_COMP = 0x00, 89219820Sjeff MLX4_EVENT_TYPE_PATH_MIG = 0x01, 90219820Sjeff MLX4_EVENT_TYPE_COMM_EST = 0x02, 91219820Sjeff MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 92219820Sjeff MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 93219820Sjeff MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 94219820Sjeff MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 95219820Sjeff MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 96219820Sjeff MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 97219820Sjeff MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 98219820Sjeff MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 99219820Sjeff MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 100219820Sjeff MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 101219820Sjeff MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 102219820Sjeff MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 103219820Sjeff MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 104219820Sjeff MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 105219820Sjeff MLX4_EVENT_TYPE_CMD = 0x0a 106219820Sjeff}; 107219820Sjeff 108219820Sjeffenum { 109219820Sjeff MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 110219820Sjeff MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 111219820Sjeff}; 112219820Sjeff 113219820Sjeffenum { 114219820Sjeff MLX4_PERM_LOCAL_READ = 1 << 10, 115219820Sjeff MLX4_PERM_LOCAL_WRITE = 1 << 11, 116219820Sjeff MLX4_PERM_REMOTE_READ = 1 << 12, 117219820Sjeff MLX4_PERM_REMOTE_WRITE = 1 << 13, 118219820Sjeff MLX4_PERM_ATOMIC = 1 << 14 119219820Sjeff}; 120219820Sjeff 121219820Sjeffenum { 122219820Sjeff MLX4_OPCODE_NOP = 0x00, 123219820Sjeff MLX4_OPCODE_SEND_INVAL = 0x01, 124219820Sjeff MLX4_OPCODE_RDMA_WRITE = 0x08, 125219820Sjeff MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 126219820Sjeff MLX4_OPCODE_SEND = 0x0a, 127219820Sjeff MLX4_OPCODE_SEND_IMM = 0x0b, 128219820Sjeff MLX4_OPCODE_LSO = 0x0e, 129219820Sjeff MLX4_OPCODE_BIG_LSO = 0x2e, 130219820Sjeff MLX4_OPCODE_RDMA_READ = 0x10, 131219820Sjeff MLX4_OPCODE_ATOMIC_CS = 0x11, 132219820Sjeff MLX4_OPCODE_ATOMIC_FA = 0x12, 133219820Sjeff MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 134219820Sjeff MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 135219820Sjeff MLX4_OPCODE_BIND_MW = 0x18, 136219820Sjeff MLX4_OPCODE_FMR = 0x19, 137219820Sjeff MLX4_OPCODE_LOCAL_INVAL = 0x1b, 138219820Sjeff MLX4_OPCODE_CONFIG_CMD = 0x1f, 139219820Sjeff 140219820Sjeff MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 141219820Sjeff MLX4_RECV_OPCODE_SEND = 0x01, 142219820Sjeff MLX4_RECV_OPCODE_SEND_IMM = 0x02, 143219820Sjeff MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 144219820Sjeff 145219820Sjeff MLX4_CQE_OPCODE_ERROR = 0x1e, 146219820Sjeff MLX4_CQE_OPCODE_RESIZE = 0x16, 147219820Sjeff}; 148219820Sjeff 149219820Sjeffenum { 150219820Sjeff MLX4_STAT_RATE_OFFSET = 5 151219820Sjeff}; 152219820Sjeff 153219820Sjeffenum { 154219820Sjeff MLX4_MTT_FLAG_PRESENT = 1 155219820Sjeff}; 156219820Sjeff 157219820Sjeffenum mlx4_qp_region { 158219820Sjeff MLX4_QP_REGION_FW = 0, 159219820Sjeff MLX4_QP_REGION_ETH_ADDR, 160219820Sjeff MLX4_QP_REGION_FC_ADDR, 161219820Sjeff MLX4_NUM_QP_REGION 162219820Sjeff}; 163219820Sjeff 164219820Sjeffenum mlx4_port_type { 165219820Sjeff MLX4_PORT_TYPE_NONE = 0, 166219820Sjeff MLX4_PORT_TYPE_IB = 1, 167219820Sjeff MLX4_PORT_TYPE_ETH = 2, 168219820Sjeff MLX4_PORT_TYPE_AUTO = 3 169219820Sjeff}; 170219820Sjeff 171219820Sjeffenum mlx4_special_vlan_idx { 172219820Sjeff MLX4_NO_VLAN_IDX = 0, 173219820Sjeff MLX4_VLAN_MISS_IDX, 174219820Sjeff MLX4_VLAN_REGULAR 175219820Sjeff}; 176219820Sjeff#define MLX4_LEAST_ATTACHED_VECTOR 0xffffffff 177219820Sjeff 178219820Sjeffenum { 179219820Sjeff MLX4_CUNTERS_DISABLED, 180219820Sjeff MLX4_CUNTERS_BASIC, 181219820Sjeff MLX4_CUNTERS_EXT 182219820Sjeff}; 183219820Sjeff 184219820Sjeffenum { 185219820Sjeff MAX_FAST_REG_PAGES = 511, 186219820Sjeff}; 187219820Sjeff 188219820Sjeffstatic inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 189219820Sjeff{ 190219820Sjeff return (major << 32) | (minor << 16) | subminor; 191219820Sjeff} 192219820Sjeff 193219820Sjeffstruct mlx4_caps { 194219820Sjeff u64 fw_ver; 195219820Sjeff int num_ports; 196219820Sjeff int vl_cap[MLX4_MAX_PORTS + 1]; 197219820Sjeff int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 198219820Sjeff __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 199219820Sjeff u64 def_mac[MLX4_MAX_PORTS + 1]; 200219820Sjeff int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 201219820Sjeff int gid_table_len[MLX4_MAX_PORTS + 1]; 202219820Sjeff int pkey_table_len[MLX4_MAX_PORTS + 1]; 203219820Sjeff int trans_type[MLX4_MAX_PORTS + 1]; 204219820Sjeff int vendor_oui[MLX4_MAX_PORTS + 1]; 205219820Sjeff int wavelength[MLX4_MAX_PORTS + 1]; 206219820Sjeff u64 trans_code[MLX4_MAX_PORTS + 1]; 207219820Sjeff int local_ca_ack_delay; 208219820Sjeff int num_uars; 209219820Sjeff int bf_reg_size; 210219820Sjeff int bf_regs_per_page; 211219820Sjeff int max_sq_sg; 212219820Sjeff int max_rq_sg; 213219820Sjeff int num_qps; 214219820Sjeff int max_wqes; 215219820Sjeff int max_sq_desc_sz; 216219820Sjeff int max_rq_desc_sz; 217219820Sjeff int max_qp_init_rdma; 218219820Sjeff int max_qp_dest_rdma; 219219820Sjeff int sqp_start; 220219820Sjeff int num_srqs; 221219820Sjeff int max_srq_wqes; 222219820Sjeff int max_srq_sge; 223219820Sjeff int reserved_srqs; 224219820Sjeff int num_cqs; 225219820Sjeff int max_cqes; 226219820Sjeff int reserved_cqs; 227219820Sjeff int num_eqs; 228219820Sjeff int reserved_eqs; 229219820Sjeff int num_comp_vectors; 230219820Sjeff int num_mpts; 231219820Sjeff int num_mtt_segs; 232219820Sjeff int mtts_per_seg; 233219820Sjeff int fmr_reserved_mtts; 234219820Sjeff int reserved_mtts; 235219820Sjeff int reserved_mrws; 236219820Sjeff int reserved_uars; 237219820Sjeff int num_mgms; 238219820Sjeff int num_amgms; 239219820Sjeff int reserved_mcgs; 240219820Sjeff int num_qp_per_mgm; 241219820Sjeff int num_pds; 242219820Sjeff int reserved_pds; 243219820Sjeff int mtt_entry_sz; 244219820Sjeff int reserved_xrcds; 245219820Sjeff int max_xrcds; 246219820Sjeff u32 max_msg_sz; 247219820Sjeff u32 page_size_cap; 248219820Sjeff u64 flags; 249219820Sjeff u32 bmme_flags; 250219820Sjeff u32 reserved_lkey; 251219820Sjeff u16 stat_rate_support; 252219820Sjeff int udp_rss; 253219820Sjeff int loopback_support; 254220016Sjeff int wol; 255219820Sjeff u8 port_width_cap[MLX4_MAX_PORTS + 1]; 256219820Sjeff int max_gso_sz; 257219820Sjeff int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 258219820Sjeff int reserved_qps; 259219820Sjeff int reserved_qps_base[MLX4_NUM_QP_REGION]; 260219820Sjeff int log_num_macs; 261219820Sjeff int log_num_vlans; 262219820Sjeff int log_num_prios; 263219820Sjeff enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 264219820Sjeff u8 supported_type[MLX4_MAX_PORTS + 1]; 265219820Sjeff enum mlx4_port_type port_mask[MLX4_MAX_PORTS + 1]; 266219820Sjeff enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 267219820Sjeff u8 counters_mode; 268219820Sjeff u32 max_basic_counters; 269219820Sjeff u32 max_ext_counters; 270219820Sjeff u32 mc_promisc_mode; 271219820Sjeff}; 272219820Sjeff 273219820Sjeffstruct mlx4_buf_list { 274219820Sjeff void *buf; 275219820Sjeff dma_addr_t map; 276219820Sjeff}; 277219820Sjeff 278219820Sjeffstruct mlx4_buf { 279219820Sjeff struct mlx4_buf_list direct; 280219820Sjeff struct mlx4_buf_list *page_list; 281219820Sjeff int nbufs; 282219820Sjeff int npages; 283219820Sjeff int page_shift; 284219820Sjeff}; 285219820Sjeff 286219820Sjeffstruct mlx4_mtt { 287219820Sjeff u32 first_seg; 288219820Sjeff int order; 289219820Sjeff int page_shift; 290219820Sjeff}; 291219820Sjeff 292219820Sjeffenum { 293219820Sjeff MLX4_DB_PER_PAGE = PAGE_SIZE / 4 294219820Sjeff}; 295219820Sjeff 296219820Sjeffstruct mlx4_db_pgdir { 297219820Sjeff struct list_head list; 298219820Sjeff DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 299219820Sjeff DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 300219820Sjeff unsigned long *bits[2]; 301219820Sjeff __be32 *db_page; 302219820Sjeff dma_addr_t db_dma; 303219820Sjeff}; 304219820Sjeff 305219820Sjeffstruct mlx4_ib_user_db_page; 306219820Sjeff 307219820Sjeffstruct mlx4_db { 308219820Sjeff __be32 *db; 309219820Sjeff union { 310219820Sjeff struct mlx4_db_pgdir *pgdir; 311219820Sjeff struct mlx4_ib_user_db_page *user_page; 312219820Sjeff } u; 313219820Sjeff dma_addr_t dma; 314219820Sjeff int index; 315219820Sjeff int order; 316219820Sjeff}; 317219820Sjeff 318219820Sjeffstruct mlx4_hwq_resources { 319219820Sjeff struct mlx4_db db; 320219820Sjeff struct mlx4_mtt mtt; 321219820Sjeff struct mlx4_buf buf; 322219820Sjeff}; 323219820Sjeff 324219820Sjeffstruct mlx4_mr { 325219820Sjeff struct mlx4_mtt mtt; 326219820Sjeff u64 iova; 327219820Sjeff u64 size; 328219820Sjeff u32 key; 329219820Sjeff u32 pd; 330219820Sjeff u32 access; 331219820Sjeff int enabled; 332219820Sjeff}; 333219820Sjeff 334219820Sjeffstruct mlx4_fmr { 335219820Sjeff struct mlx4_mr mr; 336219820Sjeff struct mlx4_mpt_entry *mpt; 337219820Sjeff __be64 *mtts; 338219820Sjeff dma_addr_t dma_handle; 339219820Sjeff int max_pages; 340219820Sjeff int max_maps; 341219820Sjeff int maps; 342219820Sjeff u8 page_shift; 343219820Sjeff}; 344219820Sjeff 345219820Sjeffstruct mlx4_uar { 346219820Sjeff unsigned long pfn; 347219820Sjeff int index; 348219820Sjeff struct list_head bf_list; 349219820Sjeff unsigned free_bf_bmap; 350219820Sjeff void __iomem *map; 351219820Sjeff void __iomem *bf_map; 352219820Sjeff}; 353219820Sjeff 354219820Sjeffstruct mlx4_bf { 355219820Sjeff unsigned long offset; 356219820Sjeff int buf_size; 357219820Sjeff struct mlx4_uar *uar; 358219820Sjeff void __iomem *reg; 359219820Sjeff}; 360219820Sjeff 361219820Sjeffstruct mlx4_cq { 362219820Sjeff void (*comp) (struct mlx4_cq *); 363219820Sjeff void (*event) (struct mlx4_cq *, enum mlx4_event); 364219820Sjeff 365219820Sjeff struct mlx4_uar *uar; 366219820Sjeff 367219820Sjeff u32 cons_index; 368219820Sjeff 369219820Sjeff __be32 *set_ci_db; 370219820Sjeff __be32 *arm_db; 371219820Sjeff int arm_sn; 372219820Sjeff 373219820Sjeff int cqn; 374219820Sjeff unsigned vector; 375219820Sjeff 376219820Sjeff atomic_t refcount; 377219820Sjeff struct completion free; 378219820Sjeff}; 379219820Sjeff 380219820Sjeffstruct mlx4_qp { 381219820Sjeff void (*event) (struct mlx4_qp *, enum mlx4_event); 382219820Sjeff 383219820Sjeff int qpn; 384219820Sjeff 385219820Sjeff atomic_t refcount; 386219820Sjeff struct completion free; 387219820Sjeff}; 388219820Sjeff 389219820Sjeffstruct mlx4_srq { 390219820Sjeff void (*event) (struct mlx4_srq *, enum mlx4_event); 391219820Sjeff 392219820Sjeff int srqn; 393219820Sjeff int max; 394219820Sjeff int max_gs; 395219820Sjeff int wqe_shift; 396219820Sjeff 397219820Sjeff atomic_t refcount; 398219820Sjeff struct completion free; 399219820Sjeff}; 400219820Sjeff 401219820Sjeffstruct mlx4_av { 402219820Sjeff __be32 port_pd; 403219820Sjeff u8 reserved1; 404219820Sjeff u8 g_slid; 405219820Sjeff __be16 dlid; 406219820Sjeff u8 reserved2; 407219820Sjeff u8 gid_index; 408219820Sjeff u8 stat_rate; 409219820Sjeff u8 hop_limit; 410219820Sjeff __be32 sl_tclass_flowlabel; 411219820Sjeff u8 dgid[16]; 412219820Sjeff}; 413219820Sjeff 414219820Sjeffstruct mlx4_eth_av { 415219820Sjeff __be32 port_pd; 416219820Sjeff u8 reserved1; 417219820Sjeff u8 smac_idx; 418219820Sjeff u16 reserved2; 419219820Sjeff u8 reserved3; 420219820Sjeff u8 gid_index; 421219820Sjeff u8 stat_rate; 422219820Sjeff u8 hop_limit; 423219820Sjeff __be32 sl_tclass_flowlabel; 424219820Sjeff u8 dgid[16]; 425219820Sjeff u32 reserved4[2]; 426219820Sjeff __be16 vlan; 427219820Sjeff u8 mac[6]; 428219820Sjeff}; 429219820Sjeff 430219820Sjeffunion mlx4_ext_av { 431219820Sjeff struct mlx4_av ib; 432219820Sjeff struct mlx4_eth_av eth; 433219820Sjeff}; 434219820Sjeff 435219820Sjeffstruct mlx4_counters { 436219820Sjeff __be32 counter_mode; 437219820Sjeff __be32 num_ifc; 438219820Sjeff u32 reserved[2]; 439219820Sjeff __be64 rx_frames; 440219820Sjeff __be64 rx_bytes; 441219820Sjeff __be64 tx_frames; 442219820Sjeff __be64 tx_bytes; 443219820Sjeff}; 444219820Sjeff 445219820Sjeffstruct mlx4_counters_ext { 446219820Sjeff __be32 counter_mode; 447219820Sjeff __be32 num_ifc; 448219820Sjeff u32 reserved[2]; 449219820Sjeff __be64 rx_uni_frames; 450219820Sjeff __be64 rx_uni_bytes; 451219820Sjeff __be64 rx_mcast_frames; 452219820Sjeff __be64 rx_mcast_bytes; 453219820Sjeff __be64 rx_bcast_frames; 454219820Sjeff __be64 rx_bcast_bytes; 455219820Sjeff __be64 rx_nobuf_frames; 456219820Sjeff __be64 rx_nobuf_bytes; 457219820Sjeff __be64 rx_err_frames; 458219820Sjeff __be64 rx_err_bytes; 459219820Sjeff __be64 tx_uni_frames; 460219820Sjeff __be64 tx_uni_bytes; 461219820Sjeff __be64 tx_mcast_frames; 462219820Sjeff __be64 tx_mcast_bytes; 463219820Sjeff __be64 tx_bcast_frames; 464219820Sjeff __be64 tx_bcast_bytes; 465219820Sjeff __be64 tx_nobuf_frames; 466219820Sjeff __be64 tx_nobuf_bytes; 467219820Sjeff __be64 tx_err_frames; 468219820Sjeff __be64 tx_err_bytes; 469219820Sjeff}; 470219820Sjeff 471219820Sjeffstruct mlx4_dev { 472219820Sjeff struct pci_dev *pdev; 473219820Sjeff unsigned long flags; 474219820Sjeff struct mlx4_caps caps; 475219820Sjeff struct radix_tree_root qp_table_tree; 476219820Sjeff struct radix_tree_root srq_table_tree; 477219820Sjeff u32 rev_id; 478219820Sjeff char board_id[MLX4_BOARD_ID_LEN]; 479219820Sjeff}; 480219820Sjeff 481219820Sjeffstruct mlx4_init_port_param { 482219820Sjeff int set_guid0; 483219820Sjeff int set_node_guid; 484219820Sjeff int set_si_guid; 485219820Sjeff u16 mtu; 486219820Sjeff int port_width_cap; 487219820Sjeff u16 vl_cap; 488219820Sjeff u16 max_gid; 489219820Sjeff u16 max_pkey; 490219820Sjeff u64 guid0; 491219820Sjeff u64 node_guid; 492219820Sjeff u64 si_guid; 493219820Sjeff}; 494219820Sjeff 495219820Sjeffstatic inline void mlx4_query_steer_cap(struct mlx4_dev *dev, int *log_mac, 496219820Sjeff int *log_vlan, int *log_prio) 497219820Sjeff{ 498219820Sjeff *log_mac = dev->caps.log_num_macs; 499219820Sjeff *log_vlan = dev->caps.log_num_vlans; 500219820Sjeff *log_prio = dev->caps.log_num_prios; 501219820Sjeff} 502219820Sjeff 503219820Sjeff#define mlx4_foreach_port(port, dev, type) \ 504219820Sjeff for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 505219820Sjeff if ((type) == (dev)->caps.port_mask[(port)]) 506219820Sjeff 507219820Sjeff#define mlx4_foreach_ib_transport_port(port, dev) \ 508219820Sjeff for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 509219820Sjeff if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 510219820Sjeff ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 511219820Sjeff 512219820Sjeffint mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 513219820Sjeff struct mlx4_buf *buf); 514219820Sjeffvoid mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 515219820Sjeffstatic inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 516219820Sjeff{ 517219820Sjeff if (buf->direct.buf != NULL) 518219820Sjeff return buf->direct.buf + offset; 519219820Sjeff else 520219820Sjeff return buf->page_list[offset >> PAGE_SHIFT].buf + 521219820Sjeff (offset & (PAGE_SIZE - 1)); 522219820Sjeff} 523219820Sjeff 524219820Sjeffint mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 525219820Sjeffvoid mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 526219820Sjeff 527219820Sjeffint mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 528219820Sjeffvoid mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 529219820Sjeff 530219820Sjeffint mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 531219820Sjeffvoid mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 532219820Sjeffint mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); 533219820Sjeffvoid mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 534219820Sjeff 535219820Sjeffint mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 536219820Sjeff struct mlx4_mtt *mtt); 537219820Sjeffvoid mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 538219820Sjeffu64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 539220016Sjeffint mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 540220016Sjeffint mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 541219820Sjeff 542220016Sjeff 543219820Sjeffint mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align, u32 *base_mridx); 544219820Sjeffvoid mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt); 545219820Sjeffint mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, 546219820Sjeff u64 iova, u64 size, u32 access, int npages, 547219820Sjeff int page_shift, struct mlx4_mr *mr); 548219820Sjeffint mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 549219820Sjeff int npages, int page_shift, struct mlx4_mr *mr); 550219820Sjeffvoid mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr); 551219820Sjeffvoid mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 552219820Sjeffint mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 553219820Sjeffint mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 554219820Sjeff int start_index, int npages, u64 *page_list); 555219820Sjeffint mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 556219820Sjeff struct mlx4_buf *buf); 557219820Sjeff 558219820Sjeffint mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 559219820Sjeffvoid mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 560219820Sjeff 561219820Sjeffint mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 562219820Sjeff int size, int max_direct); 563219820Sjeffvoid mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 564219820Sjeff int size); 565219820Sjeff 566219820Sjeffint mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 567219820Sjeff struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 568219820Sjeff unsigned vector, int collapsed); 569219820Sjeffvoid mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 570219820Sjeff 571219820Sjeffint mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 572219820Sjeffvoid mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 573219820Sjeff 574219820Sjeffint mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 575219820Sjeffvoid mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 576219820Sjeff 577219820Sjeffint mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd, 578219820Sjeff struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 579219820Sjeffvoid mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 580219820Sjeffint mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 581219820Sjeffint mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 582219820Sjeff 583219820Sjeffint mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 584219820Sjeffint mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 585219820Sjeff 586219820Sjeffint mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 587219820Sjeff int block_mcast_loopback, enum mlx4_mcast_prot prot); 588219820Sjeffint mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 589219820Sjeff enum mlx4_mcast_prot prot); 590219820Sjeff 591219820Sjeffint mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index); 592219820Sjeffvoid mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index); 593219820Sjeff 594219820Sjeffint mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 595219820Sjeffint mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 596219820Sjeffvoid mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); 597219820Sjeff 598219820Sjeffint mlx4_map_phys_fmr_fbo(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 599219820Sjeff u64 *page_list, int npages, u64 iova, u32 fbo, 600219820Sjeff u32 len, u32 *lkey, u32 *rkey, int same_key); 601219820Sjeffint mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 602219820Sjeff int npages, u64 iova, u32 *lkey, u32 *rkey); 603219820Sjeffint mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, 604219820Sjeff u32 access, int max_pages, int max_maps, 605219820Sjeff u8 page_shift, struct mlx4_fmr *fmr); 606219820Sjeffint mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 607219820Sjeff int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 608219820Sjeffint mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 609219820Sjeffvoid mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 610219820Sjeff u32 *lkey, u32 *rkey); 611219820Sjeffint mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 612219820Sjeffint mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 613219820Sjeffint mlx4_SYNC_TPT(struct mlx4_dev *dev); 614219820Sjeffint mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length, 615219820Sjeff u8 op_modifier, u32 in_offset[], u32 counter_out[]); 616219820Sjeffint mlx4_test_interrupts(struct mlx4_dev *dev); 617219820Sjeff 618219820Sjeffvoid mlx4_get_fc_t11_settings(struct mlx4_dev *dev, int *enable_pre_t11, int *t11_supported); 619219820Sjeff 620219820Sjeffint mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 621219820Sjeffvoid mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 622219820Sjeff 623219820Sjeff#endif /* MLX4_DEVICE_H */ 624