1/* 2 * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved. 3 * 4 * This software is available to you under a choice of one of two 5 * licenses. You may choose to be licensed under the terms of the GNU 6 * General Public License (GPL) Version 2, available from the file 7 * COPYING in the main directory of this source tree, or the 8 * OpenIB.org BSD license below: 9 * 10 * Redistribution and use in source and binary forms, with or 11 * without modification, are permitted provided that the following 12 * conditions are met: 13 * 14 * - Redistributions of source code must retain the above 15 * copyright notice, this list of conditions and the following 16 * disclaimer. 17 * 18 * - Redistributions in binary form must reproduce the above 19 * copyright notice, this list of conditions and the following 20 * disclaimer in the documentation and/or other materials 21 * provided with the distribution. 22 * 23 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, 24 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 25 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND 26 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS 27 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN 28 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 29 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE 30 * SOFTWARE. 31 */ 32 33#ifndef MLX4_DEVICE_H 34#define MLX4_DEVICE_H 35 36#include <linux/pci.h> 37#include <linux/completion.h> 38#include <linux/radix-tree.h> 39 40#include <asm/atomic.h> 41 42#include <linux/mlx4/driver.h> 43 44enum { 45 MLX4_FLAG_MSI_X = 1 << 0, 46 MLX4_FLAG_OLD_PORT_CMDS = 1 << 1, 47}; 48 49enum { 50 MLX4_MAX_PORTS = 2 51}; 52 53enum { 54 MLX4_BOARD_ID_LEN = 64 55}; 56 57enum { 58 MLX4_DEV_CAP_FLAG_RC = 1 << 0, 59 MLX4_DEV_CAP_FLAG_UC = 1 << 1, 60 MLX4_DEV_CAP_FLAG_UD = 1 << 2, 61 MLX4_DEV_CAP_FLAG_XRC = 1 << 3, 62 MLX4_DEV_CAP_FLAG_SRQ = 1 << 6, 63 MLX4_DEV_CAP_FLAG_IPOIB_CSUM = 1 << 7, 64 MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1 << 8, 65 MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1 << 9, 66 MLX4_DEV_CAP_FLAG_DPDP = 1 << 12, 67 MLX4_DEV_CAP_FLAG_RAW_ETY = 1 << 13, 68 MLX4_DEV_CAP_FLAG_BLH = 1 << 15, 69 MLX4_DEV_CAP_FLAG_MEM_WINDOW = 1 << 16, 70 MLX4_DEV_CAP_FLAG_APM = 1 << 17, 71 MLX4_DEV_CAP_FLAG_ATOMIC = 1 << 18, 72 MLX4_DEV_CAP_FLAG_RAW_MCAST = 1 << 19, 73 MLX4_DEV_CAP_FLAG_UD_AV_PORT = 1 << 20, 74 MLX4_DEV_CAP_FLAG_UD_MCAST = 1 << 21, 75 MLX4_DEV_CAP_FLAG_IBOE = 1 << 30, 76 MLX4_DEV_CAP_FLAG_FC_T11 = 1 << 31 77}; 78 79enum { 80 MLX4_BMME_FLAG_LOCAL_INV = 1 << 6, 81 MLX4_BMME_FLAG_REMOTE_INV = 1 << 7, 82 MLX4_BMME_FLAG_TYPE_2_WIN = 1 << 9, 83 MLX4_BMME_FLAG_RESERVED_LKEY = 1 << 10, 84 MLX4_BMME_FLAG_FAST_REG_WR = 1 << 11, 85}; 86 87enum mlx4_event { 88 MLX4_EVENT_TYPE_COMP = 0x00, 89 MLX4_EVENT_TYPE_PATH_MIG = 0x01, 90 MLX4_EVENT_TYPE_COMM_EST = 0x02, 91 MLX4_EVENT_TYPE_SQ_DRAINED = 0x03, 92 MLX4_EVENT_TYPE_SRQ_QP_LAST_WQE = 0x13, 93 MLX4_EVENT_TYPE_SRQ_LIMIT = 0x14, 94 MLX4_EVENT_TYPE_CQ_ERROR = 0x04, 95 MLX4_EVENT_TYPE_WQ_CATAS_ERROR = 0x05, 96 MLX4_EVENT_TYPE_EEC_CATAS_ERROR = 0x06, 97 MLX4_EVENT_TYPE_PATH_MIG_FAILED = 0x07, 98 MLX4_EVENT_TYPE_WQ_INVAL_REQ_ERROR = 0x10, 99 MLX4_EVENT_TYPE_WQ_ACCESS_ERROR = 0x11, 100 MLX4_EVENT_TYPE_SRQ_CATAS_ERROR = 0x12, 101 MLX4_EVENT_TYPE_LOCAL_CATAS_ERROR = 0x08, 102 MLX4_EVENT_TYPE_PORT_CHANGE = 0x09, 103 MLX4_EVENT_TYPE_EQ_OVERFLOW = 0x0f, 104 MLX4_EVENT_TYPE_ECC_DETECT = 0x0e, 105 MLX4_EVENT_TYPE_CMD = 0x0a 106}; 107 108enum { 109 MLX4_PORT_CHANGE_SUBTYPE_DOWN = 1, 110 MLX4_PORT_CHANGE_SUBTYPE_ACTIVE = 4 111}; 112 113enum { 114 MLX4_PERM_LOCAL_READ = 1 << 10, 115 MLX4_PERM_LOCAL_WRITE = 1 << 11, 116 MLX4_PERM_REMOTE_READ = 1 << 12, 117 MLX4_PERM_REMOTE_WRITE = 1 << 13, 118 MLX4_PERM_ATOMIC = 1 << 14 119}; 120 121enum { 122 MLX4_OPCODE_NOP = 0x00, 123 MLX4_OPCODE_SEND_INVAL = 0x01, 124 MLX4_OPCODE_RDMA_WRITE = 0x08, 125 MLX4_OPCODE_RDMA_WRITE_IMM = 0x09, 126 MLX4_OPCODE_SEND = 0x0a, 127 MLX4_OPCODE_SEND_IMM = 0x0b, 128 MLX4_OPCODE_LSO = 0x0e, 129 MLX4_OPCODE_BIG_LSO = 0x2e, 130 MLX4_OPCODE_RDMA_READ = 0x10, 131 MLX4_OPCODE_ATOMIC_CS = 0x11, 132 MLX4_OPCODE_ATOMIC_FA = 0x12, 133 MLX4_OPCODE_MASKED_ATOMIC_CS = 0x14, 134 MLX4_OPCODE_MASKED_ATOMIC_FA = 0x15, 135 MLX4_OPCODE_BIND_MW = 0x18, 136 MLX4_OPCODE_FMR = 0x19, 137 MLX4_OPCODE_LOCAL_INVAL = 0x1b, 138 MLX4_OPCODE_CONFIG_CMD = 0x1f, 139 140 MLX4_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 141 MLX4_RECV_OPCODE_SEND = 0x01, 142 MLX4_RECV_OPCODE_SEND_IMM = 0x02, 143 MLX4_RECV_OPCODE_SEND_INVAL = 0x03, 144 145 MLX4_CQE_OPCODE_ERROR = 0x1e, 146 MLX4_CQE_OPCODE_RESIZE = 0x16, 147}; 148 149enum { 150 MLX4_STAT_RATE_OFFSET = 5 151}; 152 153enum { 154 MLX4_MTT_FLAG_PRESENT = 1 155}; 156 157enum mlx4_qp_region { 158 MLX4_QP_REGION_FW = 0, 159 MLX4_QP_REGION_ETH_ADDR, 160 MLX4_QP_REGION_FC_ADDR, 161 MLX4_NUM_QP_REGION 162}; 163 164enum mlx4_port_type { 165 MLX4_PORT_TYPE_NONE = 0, 166 MLX4_PORT_TYPE_IB = 1, 167 MLX4_PORT_TYPE_ETH = 2, 168 MLX4_PORT_TYPE_AUTO = 3 169}; 170 171enum mlx4_special_vlan_idx { 172 MLX4_NO_VLAN_IDX = 0, 173 MLX4_VLAN_MISS_IDX, 174 MLX4_VLAN_REGULAR 175}; 176#define MLX4_LEAST_ATTACHED_VECTOR 0xffffffff 177 178enum { 179 MLX4_CUNTERS_DISABLED, 180 MLX4_CUNTERS_BASIC, 181 MLX4_CUNTERS_EXT 182}; 183 184enum { 185 MAX_FAST_REG_PAGES = 511, 186}; 187 188static inline u64 mlx4_fw_ver(u64 major, u64 minor, u64 subminor) 189{ 190 return (major << 32) | (minor << 16) | subminor; 191} 192 193struct mlx4_caps { 194 u64 fw_ver; 195 int num_ports; 196 int vl_cap[MLX4_MAX_PORTS + 1]; 197 int ib_mtu_cap[MLX4_MAX_PORTS + 1]; 198 __be32 ib_port_def_cap[MLX4_MAX_PORTS + 1]; 199 u64 def_mac[MLX4_MAX_PORTS + 1]; 200 int eth_mtu_cap[MLX4_MAX_PORTS + 1]; 201 int gid_table_len[MLX4_MAX_PORTS + 1]; 202 int pkey_table_len[MLX4_MAX_PORTS + 1]; 203 int trans_type[MLX4_MAX_PORTS + 1]; 204 int vendor_oui[MLX4_MAX_PORTS + 1]; 205 int wavelength[MLX4_MAX_PORTS + 1]; 206 u64 trans_code[MLX4_MAX_PORTS + 1]; 207 int local_ca_ack_delay; 208 int num_uars; 209 int bf_reg_size; 210 int bf_regs_per_page; 211 int max_sq_sg; 212 int max_rq_sg; 213 int num_qps; 214 int max_wqes; 215 int max_sq_desc_sz; 216 int max_rq_desc_sz; 217 int max_qp_init_rdma; 218 int max_qp_dest_rdma; 219 int sqp_start; 220 int num_srqs; 221 int max_srq_wqes; 222 int max_srq_sge; 223 int reserved_srqs; 224 int num_cqs; 225 int max_cqes; 226 int reserved_cqs; 227 int num_eqs; 228 int reserved_eqs; 229 int num_comp_vectors; 230 int num_mpts; 231 int num_mtt_segs; 232 int mtts_per_seg; 233 int fmr_reserved_mtts; 234 int reserved_mtts; 235 int reserved_mrws; 236 int reserved_uars; 237 int num_mgms; 238 int num_amgms; 239 int reserved_mcgs; 240 int num_qp_per_mgm; 241 int num_pds; 242 int reserved_pds; 243 int mtt_entry_sz; 244 int reserved_xrcds; 245 int max_xrcds; 246 u32 max_msg_sz; 247 u32 page_size_cap; 248 u64 flags; 249 u32 bmme_flags; 250 u32 reserved_lkey; 251 u16 stat_rate_support; 252 int udp_rss; 253 int loopback_support; 254 int wol; 255 u8 port_width_cap[MLX4_MAX_PORTS + 1]; 256 int max_gso_sz; 257 int reserved_qps_cnt[MLX4_NUM_QP_REGION]; 258 int reserved_qps; 259 int reserved_qps_base[MLX4_NUM_QP_REGION]; 260 int log_num_macs; 261 int log_num_vlans; 262 int log_num_prios; 263 enum mlx4_port_type port_type[MLX4_MAX_PORTS + 1]; 264 u8 supported_type[MLX4_MAX_PORTS + 1]; 265 enum mlx4_port_type port_mask[MLX4_MAX_PORTS + 1]; 266 enum mlx4_port_type possible_type[MLX4_MAX_PORTS + 1]; 267 u8 counters_mode; 268 u32 max_basic_counters; 269 u32 max_ext_counters; 270 u32 mc_promisc_mode; 271}; 272 273struct mlx4_buf_list { 274 void *buf; 275 dma_addr_t map; 276}; 277 278struct mlx4_buf { 279 struct mlx4_buf_list direct; 280 struct mlx4_buf_list *page_list; 281 int nbufs; 282 int npages; 283 int page_shift; 284}; 285 286struct mlx4_mtt { 287 u32 first_seg; 288 int order; 289 int page_shift; 290}; 291 292enum { 293 MLX4_DB_PER_PAGE = PAGE_SIZE / 4 294}; 295 296struct mlx4_db_pgdir { 297 struct list_head list; 298 DECLARE_BITMAP(order0, MLX4_DB_PER_PAGE); 299 DECLARE_BITMAP(order1, MLX4_DB_PER_PAGE / 2); 300 unsigned long *bits[2]; 301 __be32 *db_page; 302 dma_addr_t db_dma; 303}; 304 305struct mlx4_ib_user_db_page; 306 307struct mlx4_db { 308 __be32 *db; 309 union { 310 struct mlx4_db_pgdir *pgdir; 311 struct mlx4_ib_user_db_page *user_page; 312 } u; 313 dma_addr_t dma; 314 int index; 315 int order; 316}; 317 318struct mlx4_hwq_resources { 319 struct mlx4_db db; 320 struct mlx4_mtt mtt; 321 struct mlx4_buf buf; 322}; 323 324struct mlx4_mr { 325 struct mlx4_mtt mtt; 326 u64 iova; 327 u64 size; 328 u32 key; 329 u32 pd; 330 u32 access; 331 int enabled; 332}; 333 334struct mlx4_fmr { 335 struct mlx4_mr mr; 336 struct mlx4_mpt_entry *mpt; 337 __be64 *mtts; 338 dma_addr_t dma_handle; 339 int max_pages; 340 int max_maps; 341 int maps; 342 u8 page_shift; 343}; 344 345struct mlx4_uar { 346 unsigned long pfn; 347 int index; 348 struct list_head bf_list; 349 unsigned free_bf_bmap; 350 void __iomem *map; 351 void __iomem *bf_map; 352}; 353 354struct mlx4_bf { 355 unsigned long offset; 356 int buf_size; 357 struct mlx4_uar *uar; 358 void __iomem *reg; 359}; 360 361struct mlx4_cq { 362 void (*comp) (struct mlx4_cq *); 363 void (*event) (struct mlx4_cq *, enum mlx4_event); 364 365 struct mlx4_uar *uar; 366 367 u32 cons_index; 368 369 __be32 *set_ci_db; 370 __be32 *arm_db; 371 int arm_sn; 372 373 int cqn; 374 unsigned vector; 375 376 atomic_t refcount; 377 struct completion free; 378}; 379 380struct mlx4_qp { 381 void (*event) (struct mlx4_qp *, enum mlx4_event); 382 383 int qpn; 384 385 atomic_t refcount; 386 struct completion free; 387}; 388 389struct mlx4_srq { 390 void (*event) (struct mlx4_srq *, enum mlx4_event); 391 392 int srqn; 393 int max; 394 int max_gs; 395 int wqe_shift; 396 397 atomic_t refcount; 398 struct completion free; 399}; 400 401struct mlx4_av { 402 __be32 port_pd; 403 u8 reserved1; 404 u8 g_slid; 405 __be16 dlid; 406 u8 reserved2; 407 u8 gid_index; 408 u8 stat_rate; 409 u8 hop_limit; 410 __be32 sl_tclass_flowlabel; 411 u8 dgid[16]; 412}; 413 414struct mlx4_eth_av { 415 __be32 port_pd; 416 u8 reserved1; 417 u8 smac_idx; 418 u16 reserved2; 419 u8 reserved3; 420 u8 gid_index; 421 u8 stat_rate; 422 u8 hop_limit; 423 __be32 sl_tclass_flowlabel; 424 u8 dgid[16]; 425 u32 reserved4[2]; 426 __be16 vlan; 427 u8 mac[6]; 428}; 429 430union mlx4_ext_av { 431 struct mlx4_av ib; 432 struct mlx4_eth_av eth; 433}; 434 435struct mlx4_counters { 436 __be32 counter_mode; 437 __be32 num_ifc; 438 u32 reserved[2]; 439 __be64 rx_frames; 440 __be64 rx_bytes; 441 __be64 tx_frames; 442 __be64 tx_bytes; 443}; 444 445struct mlx4_counters_ext { 446 __be32 counter_mode; 447 __be32 num_ifc; 448 u32 reserved[2]; 449 __be64 rx_uni_frames; 450 __be64 rx_uni_bytes; 451 __be64 rx_mcast_frames; 452 __be64 rx_mcast_bytes; 453 __be64 rx_bcast_frames; 454 __be64 rx_bcast_bytes; 455 __be64 rx_nobuf_frames; 456 __be64 rx_nobuf_bytes; 457 __be64 rx_err_frames; 458 __be64 rx_err_bytes; 459 __be64 tx_uni_frames; 460 __be64 tx_uni_bytes; 461 __be64 tx_mcast_frames; 462 __be64 tx_mcast_bytes; 463 __be64 tx_bcast_frames; 464 __be64 tx_bcast_bytes; 465 __be64 tx_nobuf_frames; 466 __be64 tx_nobuf_bytes; 467 __be64 tx_err_frames; 468 __be64 tx_err_bytes; 469}; 470 471struct mlx4_dev { 472 struct pci_dev *pdev; 473 unsigned long flags; 474 struct mlx4_caps caps; 475 struct radix_tree_root qp_table_tree; 476 struct radix_tree_root srq_table_tree; 477 u32 rev_id; 478 char board_id[MLX4_BOARD_ID_LEN]; 479}; 480 481struct mlx4_init_port_param { 482 int set_guid0; 483 int set_node_guid; 484 int set_si_guid; 485 u16 mtu; 486 int port_width_cap; 487 u16 vl_cap; 488 u16 max_gid; 489 u16 max_pkey; 490 u64 guid0; 491 u64 node_guid; 492 u64 si_guid; 493}; 494 495static inline void mlx4_query_steer_cap(struct mlx4_dev *dev, int *log_mac, 496 int *log_vlan, int *log_prio) 497{ 498 *log_mac = dev->caps.log_num_macs; 499 *log_vlan = dev->caps.log_num_vlans; 500 *log_prio = dev->caps.log_num_prios; 501} 502 503#define mlx4_foreach_port(port, dev, type) \ 504 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 505 if ((type) == (dev)->caps.port_mask[(port)]) 506 507#define mlx4_foreach_ib_transport_port(port, dev) \ 508 for ((port) = 1; (port) <= (dev)->caps.num_ports; (port)++) \ 509 if (((dev)->caps.port_mask[port] == MLX4_PORT_TYPE_IB) || \ 510 ((dev)->caps.flags & MLX4_DEV_CAP_FLAG_IBOE)) 511 512int mlx4_buf_alloc(struct mlx4_dev *dev, int size, int max_direct, 513 struct mlx4_buf *buf); 514void mlx4_buf_free(struct mlx4_dev *dev, int size, struct mlx4_buf *buf); 515static inline void *mlx4_buf_offset(struct mlx4_buf *buf, int offset) 516{ 517 if (buf->direct.buf != NULL) 518 return buf->direct.buf + offset; 519 else 520 return buf->page_list[offset >> PAGE_SHIFT].buf + 521 (offset & (PAGE_SIZE - 1)); 522} 523 524int mlx4_pd_alloc(struct mlx4_dev *dev, u32 *pdn); 525void mlx4_pd_free(struct mlx4_dev *dev, u32 pdn); 526 527int mlx4_xrcd_alloc(struct mlx4_dev *dev, u32 *xrcdn); 528void mlx4_xrcd_free(struct mlx4_dev *dev, u32 xrcdn); 529 530int mlx4_uar_alloc(struct mlx4_dev *dev, struct mlx4_uar *uar); 531void mlx4_uar_free(struct mlx4_dev *dev, struct mlx4_uar *uar); 532int mlx4_bf_alloc(struct mlx4_dev *dev, struct mlx4_bf *bf); 533void mlx4_bf_free(struct mlx4_dev *dev, struct mlx4_bf *bf); 534 535int mlx4_mtt_init(struct mlx4_dev *dev, int npages, int page_shift, 536 struct mlx4_mtt *mtt); 537void mlx4_mtt_cleanup(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 538u64 mlx4_mtt_addr(struct mlx4_dev *dev, struct mlx4_mtt *mtt); 539int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port); 540int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port); 541 542 543int mlx4_mr_reserve_range(struct mlx4_dev *dev, int cnt, int align, u32 *base_mridx); 544void mlx4_mr_release_range(struct mlx4_dev *dev, u32 base_mridx, int cnt); 545int mlx4_mr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, 546 u64 iova, u64 size, u32 access, int npages, 547 int page_shift, struct mlx4_mr *mr); 548int mlx4_mr_alloc(struct mlx4_dev *dev, u32 pd, u64 iova, u64 size, u32 access, 549 int npages, int page_shift, struct mlx4_mr *mr); 550void mlx4_mr_free_reserved(struct mlx4_dev *dev, struct mlx4_mr *mr); 551void mlx4_mr_free(struct mlx4_dev *dev, struct mlx4_mr *mr); 552int mlx4_mr_enable(struct mlx4_dev *dev, struct mlx4_mr *mr); 553int mlx4_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 554 int start_index, int npages, u64 *page_list); 555int mlx4_buf_write_mtt(struct mlx4_dev *dev, struct mlx4_mtt *mtt, 556 struct mlx4_buf *buf); 557 558int mlx4_db_alloc(struct mlx4_dev *dev, struct mlx4_db *db, int order); 559void mlx4_db_free(struct mlx4_dev *dev, struct mlx4_db *db); 560 561int mlx4_alloc_hwq_res(struct mlx4_dev *dev, struct mlx4_hwq_resources *wqres, 562 int size, int max_direct); 563void mlx4_free_hwq_res(struct mlx4_dev *mdev, struct mlx4_hwq_resources *wqres, 564 int size); 565 566int mlx4_cq_alloc(struct mlx4_dev *dev, int nent, struct mlx4_mtt *mtt, 567 struct mlx4_uar *uar, u64 db_rec, struct mlx4_cq *cq, 568 unsigned vector, int collapsed); 569void mlx4_cq_free(struct mlx4_dev *dev, struct mlx4_cq *cq); 570 571int mlx4_qp_reserve_range(struct mlx4_dev *dev, int cnt, int align, int *base); 572void mlx4_qp_release_range(struct mlx4_dev *dev, int base_qpn, int cnt); 573 574int mlx4_qp_alloc(struct mlx4_dev *dev, int qpn, struct mlx4_qp *qp); 575void mlx4_qp_free(struct mlx4_dev *dev, struct mlx4_qp *qp); 576 577int mlx4_srq_alloc(struct mlx4_dev *dev, u32 pdn, u32 cqn, u16 xrcd, 578 struct mlx4_mtt *mtt, u64 db_rec, struct mlx4_srq *srq); 579void mlx4_srq_free(struct mlx4_dev *dev, struct mlx4_srq *srq); 580int mlx4_srq_arm(struct mlx4_dev *dev, struct mlx4_srq *srq, int limit_watermark); 581int mlx4_srq_query(struct mlx4_dev *dev, struct mlx4_srq *srq, int *limit_watermark); 582 583int mlx4_INIT_PORT(struct mlx4_dev *dev, int port); 584int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port); 585 586int mlx4_multicast_attach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 587 int block_mcast_loopback, enum mlx4_mcast_prot prot); 588int mlx4_multicast_detach(struct mlx4_dev *dev, struct mlx4_qp *qp, u8 gid[16], 589 enum mlx4_mcast_prot prot); 590 591int mlx4_register_mac(struct mlx4_dev *dev, u8 port, u64 mac, int *index); 592void mlx4_unregister_mac(struct mlx4_dev *dev, u8 port, int index); 593 594int mlx4_find_cached_vlan(struct mlx4_dev *dev, u8 port, u16 vid, int *idx); 595int mlx4_register_vlan(struct mlx4_dev *dev, u8 port, u16 vlan, int *index); 596void mlx4_unregister_vlan(struct mlx4_dev *dev, u8 port, int index); 597 598int mlx4_map_phys_fmr_fbo(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 599 u64 *page_list, int npages, u64 iova, u32 fbo, 600 u32 len, u32 *lkey, u32 *rkey, int same_key); 601int mlx4_map_phys_fmr(struct mlx4_dev *dev, struct mlx4_fmr *fmr, u64 *page_list, 602 int npages, u64 iova, u32 *lkey, u32 *rkey); 603int mlx4_fmr_alloc_reserved(struct mlx4_dev *dev, u32 mridx, u32 pd, 604 u32 access, int max_pages, int max_maps, 605 u8 page_shift, struct mlx4_fmr *fmr); 606int mlx4_fmr_alloc(struct mlx4_dev *dev, u32 pd, u32 access, int max_pages, 607 int max_maps, u8 page_shift, struct mlx4_fmr *fmr); 608int mlx4_fmr_enable(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 609void mlx4_fmr_unmap(struct mlx4_dev *dev, struct mlx4_fmr *fmr, 610 u32 *lkey, u32 *rkey); 611int mlx4_fmr_free_reserved(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 612int mlx4_fmr_free(struct mlx4_dev *dev, struct mlx4_fmr *fmr); 613int mlx4_SYNC_TPT(struct mlx4_dev *dev); 614int mlx4_query_diag_counters(struct mlx4_dev *mlx4_dev, int array_length, 615 u8 op_modifier, u32 in_offset[], u32 counter_out[]); 616int mlx4_test_interrupts(struct mlx4_dev *dev); 617 618void mlx4_get_fc_t11_settings(struct mlx4_dev *dev, int *enable_pre_t11, int *t11_supported); 619 620int mlx4_counter_alloc(struct mlx4_dev *dev, u32 *idx); 621void mlx4_counter_free(struct mlx4_dev *dev, u32 idx); 622 623#endif /* MLX4_DEVICE_H */ 624