1178173Simp/* $FreeBSD$ */
2178173Simp
3178173Simp#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_
4178173Simp#define _MIPS32_SENTRY5_SENTRY5REG_H_
5178173Simp
6178173Simp#define	SENTRY5_UART0ADR	0x18000300
7178173Simp#define	SENTRY5_UART1ADR	0x18000400
8178173Simp
9178173Simp/* Reset register implemented here in a PLD device. */
10178173Simp#define	SENTRY5_EXTIFADR	0x1F000000
11178173Simp#define	SENTRY5_DORESET		0x80
12178173Simp
13178173Simp/*
14178173Simp * Custom CP0 register macros.
15178173Simp * XXX: This really needs the mips cpuregs.h file for the barrier.
16178173Simp */
17178173Simp#define S5_RDRW32_C0P0_CUST22(n,r)				\
18178173Simpstatic __inline u_int32_t					\
19178173Simps5_rd_ ## n (void)						\
20178173Simp{								\
21178173Simp	int v0;							\
22178173Simp	__asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;"	\
23178173Simp			  : [v0] "=&r"(v0));			\
24178173Simp	/*mips_barrier();*/					\
25178173Simp	return (v0);						\
26178173Simp}								\
27178173Simpstatic __inline void						\
28178173Simps5_wr_ ## n (u_int32_t a0)					\
29178173Simp{								\
30178173Simp	__asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;"	\
31178173Simp			 __XSTRING(COP0_SYNC)";"		\
32178173Simp			 "nop;"					\
33178173Simp			 "nop;"					\
34178173Simp			 :					\
35178173Simp			 : [a0] "r"(a0));			\
36178173Simp	/*mips_barrier();*/					\
37178173Simp} struct __hack
38178173Simp
39178173Simp/*
40178173Simp * All 5 of these sub-registers are used by Linux.
41178173Simp * There is a further custom register at 25 which is not used.
42178173Simp */
43178173Simp#define	S5_CP0_DIAG	0
44178173Simp#define	S5_CP0_CLKCFG1	1
45178173Simp#define	S5_CP0_CLKCFG2	2
46178173Simp#define	S5_CP0_SYNC	3
47178173Simp#define	S5_CP0_CLKCFG3	4
48178173Simp#define	S5_CP0_RESET	5
49178173Simp
50178173Simp/* s5_[rd|wr]_xxx() */
51178173SimpS5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG);
52178173SimpS5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1);
53178173SimpS5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2);
54178173SimpS5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC);
55178173SimpS5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3);
56178173SimpS5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET);
57178173Simp
58178173Simp#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */
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