1/* $FreeBSD$ */ 2 3#ifndef _MIPS32_SENTRY5_SENTRY5REG_H_ 4#define _MIPS32_SENTRY5_SENTRY5REG_H_ 5 6#define SENTRY5_UART0ADR 0x18000300 7#define SENTRY5_UART1ADR 0x18000400 8 9/* Reset register implemented here in a PLD device. */ 10#define SENTRY5_EXTIFADR 0x1F000000 11#define SENTRY5_DORESET 0x80 12 13/* 14 * Custom CP0 register macros. 15 * XXX: This really needs the mips cpuregs.h file for the barrier. 16 */ 17#define S5_RDRW32_C0P0_CUST22(n,r) \ 18static __inline u_int32_t \ 19s5_rd_ ## n (void) \ 20{ \ 21 int v0; \ 22 __asm __volatile ("mfc0 %[v0], $22, "__XSTRING(r)" ;" \ 23 : [v0] "=&r"(v0)); \ 24 /*mips_barrier();*/ \ 25 return (v0); \ 26} \ 27static __inline void \ 28s5_wr_ ## n (u_int32_t a0) \ 29{ \ 30 __asm __volatile ("mtc0 %[a0], $22, "__XSTRING(r)" ;" \ 31 __XSTRING(COP0_SYNC)";" \ 32 "nop;" \ 33 "nop;" \ 34 : \ 35 : [a0] "r"(a0)); \ 36 /*mips_barrier();*/ \ 37} struct __hack 38 39/* 40 * All 5 of these sub-registers are used by Linux. 41 * There is a further custom register at 25 which is not used. 42 */ 43#define S5_CP0_DIAG 0 44#define S5_CP0_CLKCFG1 1 45#define S5_CP0_CLKCFG2 2 46#define S5_CP0_SYNC 3 47#define S5_CP0_CLKCFG3 4 48#define S5_CP0_RESET 5 49 50/* s5_[rd|wr]_xxx() */ 51S5_RDRW32_C0P0_CUST22(diag, S5_CP0_DIAG); 52S5_RDRW32_C0P0_CUST22(clkcfg1, S5_CP0_CLKCFG1); 53S5_RDRW32_C0P0_CUST22(clkcfg2, S5_CP0_CLKCFG2); 54S5_RDRW32_C0P0_CUST22(sync, S5_CP0_SYNC); 55S5_RDRW32_C0P0_CUST22(clkcfg3, S5_CP0_CLKCFG3); 56S5_RDRW32_C0P0_CUST22(reset, S5_CP0_RESET); 57 58#endif /* _MIPS32_SENTRY5_SENTRY5REG_H_ */ 59