1224110Sjchandra/*- 2224110Sjchandra * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3224110Sjchandra * reserved. 4224110Sjchandra * 5224110Sjchandra * Redistribution and use in source and binary forms, with or without 6224110Sjchandra * modification, are permitted provided that the following conditions are 7224110Sjchandra * met: 8224110Sjchandra * 9224110Sjchandra * 1. Redistributions of source code must retain the above copyright 10224110Sjchandra * notice, this list of conditions and the following disclaimer. 11224110Sjchandra * 2. Redistributions in binary form must reproduce the above copyright 12224110Sjchandra * notice, this list of conditions and the following disclaimer in 13224110Sjchandra * the documentation and/or other materials provided with the 14224110Sjchandra * distribution. 15224110Sjchandra * 16224110Sjchandra * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17224110Sjchandra * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18224110Sjchandra * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19224110Sjchandra * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20224110Sjchandra * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21224110Sjchandra * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22224110Sjchandra * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23224110Sjchandra * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24224110Sjchandra * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25224110Sjchandra * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26224110Sjchandra * THE POSSIBILITY OF SUCH DAMAGE. 27224110Sjchandra * 28225394Sjchandra * NETLOGIC_BSD 29224110Sjchandra * $FreeBSD$ 30225394Sjchandra */ 31224110Sjchandra 32225394Sjchandra#ifndef _NLM_HAL_PIC_H 33225394Sjchandra#define _NLM_HAL_PIC_H 34224110Sjchandra 35224110Sjchandra/* PIC Specific registers */ 36225394Sjchandra#define PIC_CTRL 0x00 37224110Sjchandra 38225394Sjchandra/* PIC control register defines */ 39225394Sjchandra#define PIC_CTRL_ITV 32 /* interrupt timeout value */ 40225394Sjchandra#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */ 41225394Sjchandra#define PIC_CTRL_ITE 18 /* interrupt timeout enable */ 42225394Sjchandra#define PIC_CTRL_STE 10 /* system timer interrupt enable */ 43225394Sjchandra#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */ 44225394Sjchandra#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */ 45225394Sjchandra#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */ 46225394Sjchandra#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */ 47225394Sjchandra#define PIC_CTRL_WTE 0 /* watchdog timer enable */ 48224110Sjchandra 49225394Sjchandra/* PIC Status register defines */ 50225394Sjchandra#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */ 51225394Sjchandra#define PIC_ITE_STATUS 32 /* interrupt timeout status */ 52225394Sjchandra#define PIC_STS_STATUS 4 /* System timer interrupt status */ 53225394Sjchandra#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */ 54225394Sjchandra#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */ 55224110Sjchandra 56225394Sjchandra/* PIC IPI control register offsets */ 57225394Sjchandra#define PIC_IPICTRL_NMI 32 58225394Sjchandra#define PIC_IPICTRL_RIV 20 /* received interrupt vector */ 59225394Sjchandra#define PIC_IPICTRL_IDB 16 /* interrupt destination base */ 60225394Sjchandra#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */ 61224110Sjchandra 62225394Sjchandra/* PIC IRT register offsets */ 63225394Sjchandra#define PIC_IRT_ENABLE 31 64225394Sjchandra#define PIC_IRT_NMI 29 65225394Sjchandra#define PIC_IRT_SCH 28 /* Scheduling scheme */ 66225394Sjchandra#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */ 67225394Sjchandra#define PIC_IRT_DT 19 /* Destination type */ 68225394Sjchandra#define PIC_IRT_DB 16 /* Destination base */ 69225394Sjchandra#define PIC_IRT_DTE 0 /* Destination thread enables */ 70224110Sjchandra 71225394Sjchandra#define PIC_BYTESWAP 0x02 72225394Sjchandra#define PIC_STATUS 0x04 73225394Sjchandra#define PIC_INTR_TIMEOUT 0x06 74225394Sjchandra#define PIC_ICI0_INTR_TIMEOUT 0x08 75225394Sjchandra#define PIC_ICI1_INTR_TIMEOUT 0x0a 76225394Sjchandra#define PIC_ICI2_INTR_TIMEOUT 0x0c 77225394Sjchandra#define PIC_IPI_CTL 0x0e 78225394Sjchandra#define PIC_INT_ACK 0x10 79225394Sjchandra#define PIC_INT_PENDING0 0x12 80225394Sjchandra#define PIC_INT_PENDING1 0x14 81225394Sjchandra#define PIC_INT_PENDING2 0x16 82224110Sjchandra 83225394Sjchandra#define PIC_WDOG0_MAXVAL 0x18 84225394Sjchandra#define PIC_WDOG0_COUNT 0x1a 85225394Sjchandra#define PIC_WDOG0_ENABLE0 0x1c 86225394Sjchandra#define PIC_WDOG0_ENABLE1 0x1e 87225394Sjchandra#define PIC_WDOG0_BEATCMD 0x20 88225394Sjchandra#define PIC_WDOG0_BEAT0 0x22 89225394Sjchandra#define PIC_WDOG0_BEAT1 0x24 90224110Sjchandra 91225394Sjchandra#define PIC_WDOG1_MAXVAL 0x26 92225394Sjchandra#define PIC_WDOG1_COUNT 0x28 93225394Sjchandra#define PIC_WDOG1_ENABLE0 0x2a 94225394Sjchandra#define PIC_WDOG1_ENABLE1 0x2c 95225394Sjchandra#define PIC_WDOG1_BEATCMD 0x2e 96225394Sjchandra#define PIC_WDOG1_BEAT0 0x30 97225394Sjchandra#define PIC_WDOG1_BEAT1 0x32 98224110Sjchandra 99225394Sjchandra#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) 100225394Sjchandra#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) 101225394Sjchandra#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) 102225394Sjchandra#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) 103225394Sjchandra#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) 104225394Sjchandra#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) 105225394Sjchandra#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) 106224110Sjchandra 107225394Sjchandra#define PIC_TIMER0_MAXVAL 0x34 108225394Sjchandra#define PIC_TIMER1_MAXVAL 0x36 109225394Sjchandra#define PIC_TIMER2_MAXVAL 0x38 110225394Sjchandra#define PIC_TIMER3_MAXVAL 0x3a 111225394Sjchandra#define PIC_TIMER4_MAXVAL 0x3c 112225394Sjchandra#define PIC_TIMER5_MAXVAL 0x3e 113225394Sjchandra#define PIC_TIMER6_MAXVAL 0x40 114225394Sjchandra#define PIC_TIMER7_MAXVAL 0x42 115225394Sjchandra#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2)) 116224110Sjchandra 117225394Sjchandra#define PIC_TIMER0_COUNT 0x44 118225394Sjchandra#define PIC_TIMER1_COUNT 0x46 119225394Sjchandra#define PIC_TIMER2_COUNT 0x48 120225394Sjchandra#define PIC_TIMER3_COUNT 0x4a 121225394Sjchandra#define PIC_TIMER4_COUNT 0x4c 122225394Sjchandra#define PIC_TIMER5_COUNT 0x4e 123225394Sjchandra#define PIC_TIMER6_COUNT 0x50 124225394Sjchandra#define PIC_TIMER7_COUNT 0x52 125225394Sjchandra#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) 126224110Sjchandra 127225394Sjchandra#define PIC_ITE0_N0_N1 0x54 128225394Sjchandra#define PIC_ITE1_N0_N1 0x58 129225394Sjchandra#define PIC_ITE2_N0_N1 0x5c 130225394Sjchandra#define PIC_ITE3_N0_N1 0x60 131225394Sjchandra#define PIC_ITE4_N0_N1 0x64 132225394Sjchandra#define PIC_ITE5_N0_N1 0x68 133225394Sjchandra#define PIC_ITE6_N0_N1 0x6c 134225394Sjchandra#define PIC_ITE7_N0_N1 0x70 135225394Sjchandra#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) 136225394Sjchandra 137225394Sjchandra#define PIC_ITE0_N2_N3 0x56 138225394Sjchandra#define PIC_ITE1_N2_N3 0x5a 139225394Sjchandra#define PIC_ITE2_N2_N3 0x5e 140225394Sjchandra#define PIC_ITE3_N2_N3 0x62 141225394Sjchandra#define PIC_ITE4_N2_N3 0x66 142225394Sjchandra#define PIC_ITE5_N2_N3 0x6a 143225394Sjchandra#define PIC_ITE6_N2_N3 0x6e 144225394Sjchandra#define PIC_ITE7_N2_N3 0x72 145225394Sjchandra#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) 146225394Sjchandra 147225394Sjchandra#define PIC_IRT0 0x74 148225394Sjchandra#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 149225394Sjchandra 150225394Sjchandra#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL 151225394Sjchandra 152225394Sjchandra/* 153225394Sjchandra * IRT Map 154225394Sjchandra */ 155225394Sjchandra#define PIC_NUM_IRTS 160 156225394Sjchandra 157225394Sjchandra#define PIC_IRT_WD_0_INDEX 0 158225394Sjchandra#define PIC_IRT_WD_1_INDEX 1 159225394Sjchandra#define PIC_IRT_WD_NMI_0_INDEX 2 160225394Sjchandra#define PIC_IRT_WD_NMI_1_INDEX 3 161225394Sjchandra#define PIC_IRT_TIMER_0_INDEX 4 162225394Sjchandra#define PIC_IRT_TIMER_1_INDEX 5 163225394Sjchandra#define PIC_IRT_TIMER_2_INDEX 6 164225394Sjchandra#define PIC_IRT_TIMER_3_INDEX 7 165225394Sjchandra#define PIC_IRT_TIMER_4_INDEX 8 166225394Sjchandra#define PIC_IRT_TIMER_5_INDEX 9 167225394Sjchandra#define PIC_IRT_TIMER_6_INDEX 10 168225394Sjchandra#define PIC_IRT_TIMER_7_INDEX 11 169225394Sjchandra#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX 170225394Sjchandra#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX) 171225394Sjchandra 172225394Sjchandra 173225394Sjchandra/* 11 and 12 */ 174225394Sjchandra#define PIC_NUM_MSG_Q_IRTS 32 175225394Sjchandra#define PIC_IRT_MSG_Q0_INDEX 12 176225394Sjchandra#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX) 177224110Sjchandra/* 12 to 43 */ 178225394Sjchandra#define PIC_IRT_MSG_0_INDEX 44 179225394Sjchandra#define PIC_IRT_MSG_1_INDEX 45 180225394Sjchandra/* 44 and 45 */ 181225394Sjchandra#define PIC_NUM_PCIE_MSIX_IRTS 32 182225394Sjchandra#define PIC_IRT_PCIE_MSIX_0_INDEX 46 183225394Sjchandra#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX) 184224110Sjchandra/* 46 to 77 */ 185225394Sjchandra#define PIC_NUM_PCIE_LINK_IRTS 4 186225394Sjchandra#define PIC_IRT_PCIE_LINK_0_INDEX 78 187225394Sjchandra#define PIC_IRT_PCIE_LINK_1_INDEX 79 188225394Sjchandra#define PIC_IRT_PCIE_LINK_2_INDEX 80 189225394Sjchandra#define PIC_IRT_PCIE_LINK_3_INDEX 81 190225394Sjchandra#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) 191224110Sjchandra/* 78 to 81 */ 192225394Sjchandra#define PIC_NUM_NA_IRTS 32 193224110Sjchandra/* 82 to 113 */ 194225394Sjchandra#define PIC_IRT_NA_0_INDEX 82 195225394Sjchandra#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX) 196225394Sjchandra#define PIC_IRT_POE_INDEX 114 197225394Sjchandra 198225394Sjchandra#define PIC_NUM_USB_IRTS 6 199225394Sjchandra#define PIC_IRT_USB_0_INDEX 115 200225394Sjchandra#define PIC_IRT_EHCI_0_INDEX 115 201225394Sjchandra#define PIC_IRT_EHCI_1_INDEX 118 202225394Sjchandra#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) 203224110Sjchandra/* 115 to 120 */ 204225394Sjchandra#define PIC_IRT_GDX_INDEX 121 205225394Sjchandra#define PIC_IRT_SEC_INDEX 122 206225394Sjchandra#define PIC_IRT_RSA_INDEX 123 207225394Sjchandra 208225394Sjchandra#define PIC_NUM_COMP_IRTS 4 209225394Sjchandra#define PIC_IRT_COMP_0_INDEX 124 210225394Sjchandra#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX) 211224110Sjchandra/* 124 to 127 */ 212225394Sjchandra#define PIC_IRT_GBU_INDEX 128 213225394Sjchandra#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */ 214225394Sjchandra#define PIC_IRT_ICC_1_INDEX 130 215225394Sjchandra#define PIC_IRT_ICC_2_INDEX 131 216225394Sjchandra#define PIC_IRT_CAM_INDEX 132 217225394Sjchandra#define PIC_IRT_UART_0_INDEX 133 218225394Sjchandra#define PIC_IRT_UART_1_INDEX 134 219225394Sjchandra#define PIC_IRT_I2C_0_INDEX 135 220225394Sjchandra#define PIC_IRT_I2C_1_INDEX 136 221225394Sjchandra#define PIC_IRT_SYS_0_INDEX 137 222225394Sjchandra#define PIC_IRT_SYS_1_INDEX 138 223225394Sjchandra#define PIC_IRT_JTAG_INDEX 139 224225394Sjchandra#define PIC_IRT_PIC_INDEX 140 225225394Sjchandra#define PIC_IRT_NBU_INDEX 141 226225394Sjchandra#define PIC_IRT_TCU_INDEX 142 227225394Sjchandra#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */ 228225394Sjchandra#define PIC_IRT_DMC_0_INDEX 144 229225394Sjchandra#define PIC_IRT_DMC_1_INDEX 145 230224110Sjchandra 231225394Sjchandra#define PIC_NUM_GPIO_IRTS 4 232225394Sjchandra#define PIC_IRT_GPIO_0_INDEX 146 233225394Sjchandra#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX) 234224110Sjchandra 235225394Sjchandra/* 146 to 149 */ 236225394Sjchandra#define PIC_IRT_NOR_INDEX 150 237225394Sjchandra#define PIC_IRT_NAND_INDEX 151 238225394Sjchandra#define PIC_IRT_SPI_INDEX 152 239225394Sjchandra#define PIC_IRT_MMC_INDEX 153 240224110Sjchandra 241225394Sjchandra#define PIC_CLOCK_TIMER 7 242225394Sjchandra#define PIC_IRQ_BASE 8 243224110Sjchandra 244225394Sjchandra#if !defined(LOCORE) && !defined(__ASSEMBLY__) 245224110Sjchandra 246225394Sjchandra#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) 247225394Sjchandra#define PIC_IRT_LAST_IRQ 63 248225394Sjchandra#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ) 249224110Sjchandra 250225394Sjchandra/* 251225394Sjchandra * Misc 252225394Sjchandra */ 253225394Sjchandra#define PIC_IRT_VALID 1 254225394Sjchandra#define PIC_LOCAL_SCHEDULING 1 255225394Sjchandra#define PIC_GLOBAL_SCHEDULING 0 256224110Sjchandra 257225394Sjchandra#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 258225394Sjchandra#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 259225394Sjchandra#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 260225394Sjchandra#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 261224110Sjchandra 262224110Sjchandra/* IRT and h/w interrupt routines */ 263225394Sjchandrastatic inline int 264225394Sjchandranlm_pic_read_irt(uint64_t base, int irt_index) 265224110Sjchandra{ 266225394Sjchandra return nlm_read_pic_reg(base, PIC_IRT(irt_index)); 267224110Sjchandra} 268224110Sjchandra 269225394Sjchandrastatic inline void 270225394Sjchandranlm_pic_send_ipi(uint64_t base, int cpu, int vec, int nmi) 271224110Sjchandra{ 272225394Sjchandra uint64_t ipi; 273225394Sjchandra int node, ncpu; 274224110Sjchandra 275225394Sjchandra node = cpu / 32; 276225394Sjchandra ncpu = cpu & 0x1f; 277225394Sjchandra ipi = ((uint64_t)nmi << 31) | (vec << 20) | (node << 17) | 278225394Sjchandra (1 << (cpu & 0xf)); 279225394Sjchandra if (ncpu > 15) 280225394Sjchandra ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */ 281224110Sjchandra 282225394Sjchandra nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 283224110Sjchandra} 284224110Sjchandra 285225394Sjchandrastatic inline uint64_t 286225394Sjchandranlm_pic_read_control(uint64_t base) 287224110Sjchandra{ 288225394Sjchandra return nlm_read_pic_reg(base, PIC_CTRL); 289224110Sjchandra} 290224110Sjchandra 291225394Sjchandrastatic inline void 292225394Sjchandranlm_pic_write_control(uint64_t base, uint64_t control) 293224110Sjchandra{ 294225394Sjchandra nlm_write_pic_reg(base, PIC_CTRL, control); 295224110Sjchandra} 296224110Sjchandra 297225394Sjchandrastatic inline void 298225394Sjchandranlm_pic_update_control(uint64_t base, uint64_t control) 299224110Sjchandra{ 300225394Sjchandra uint64_t val; 301224110Sjchandra 302225394Sjchandra val = nlm_read_pic_reg(base, PIC_CTRL); 303225394Sjchandra nlm_write_pic_reg(base, PIC_CTRL, control | val); 304224110Sjchandra} 305224110Sjchandra 306225394Sjchandrastatic inline void 307225394Sjchandranlm_pic_ack(uint64_t base, int irt_num) 308224110Sjchandra{ 309225394Sjchandra nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); 310224110Sjchandra 311225394Sjchandra /* Ack the Status register for Watchdog & System timers */ 312225394Sjchandra if (irt_num < 12) 313225394Sjchandra nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); 314224110Sjchandra} 315224110Sjchandra 316225394Sjchandrastatic inline void 317225394Sjchandranlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 318224110Sjchandra{ 319225394Sjchandra uint64_t val; 320224110Sjchandra 321225394Sjchandra val = nlm_read_pic_reg(base, PIC_IRT(irt)); 322225394Sjchandra val |= cpu & 0xf; 323225394Sjchandra if (cpu > 15) 324225394Sjchandra val |= 1 << 16; 325225394Sjchandra nlm_write_pic_reg(base, PIC_IRT(irt), val); 326224110Sjchandra} 327224110Sjchandra 328225394Sjchandrastatic inline void 329225394Sjchandranlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, 330225394Sjchandra int sch, int vec, int dt, int db, int dte) 331224110Sjchandra{ 332225394Sjchandra uint64_t val; 333224110Sjchandra 334225394Sjchandra val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) | 335225394Sjchandra ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) | 336225394Sjchandra ((dt & 0x1) << 19) | ((db & 0x7) << 16) | 337225394Sjchandra (dte & 0xffff); 338224110Sjchandra 339225394Sjchandra nlm_write_pic_reg(base, PIC_IRT(irt_num), val); 340224110Sjchandra} 341224110Sjchandra 342225394Sjchandrastatic inline void 343225394Sjchandranlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, 344225394Sjchandra int sch, int vec, int cpu) 345224110Sjchandra{ 346225394Sjchandra nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, 347225394Sjchandra (cpu >> 4), /* thread group */ 348225394Sjchandra 1 << (cpu & 0xf)); /* thread mask */ 349224110Sjchandra} 350224110Sjchandra 351225394Sjchandrastatic inline uint64_t 352225394Sjchandranlm_pic_read_timer(uint64_t base, int timer) 353225394Sjchandra{ 354225394Sjchandra return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); 355225394Sjchandra} 356224110Sjchandra 357225394Sjchandrastatic inline void 358225394Sjchandranlm_pic_write_timer(uint64_t base, int timer, uint64_t value) 359224110Sjchandra{ 360225394Sjchandra nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); 361224110Sjchandra} 362224110Sjchandra 363225394Sjchandrastatic inline void 364225394Sjchandranlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) 365224110Sjchandra{ 366225394Sjchandra uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); 367225394Sjchandra int en; 368224110Sjchandra 369225394Sjchandra en = (irq > 0); 370225394Sjchandra nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); 371225394Sjchandra nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), 372225394Sjchandra en, 0, 0, irq, cpu); 373225394Sjchandra 374225394Sjchandra /* enable the timer */ 375225394Sjchandra pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); 376225394Sjchandra nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); 377224110Sjchandra} 378224110Sjchandra 379225394Sjchandra#endif /* __ASSEMBLY__ */ 380225394Sjchandra#endif /* _NLM_HAL_PIC_H */ 381