1/*- 2 * Copyright 2003-2011 Netlogic Microsystems (Netlogic). All rights 3 * reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in 13 * the documentation and/or other materials provided with the 14 * distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY Netlogic Microsystems ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL NETLOGIC OR CONTRIBUTORS BE 20 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 21 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 22 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 23 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 24 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 25 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 26 * THE POSSIBILITY OF SUCH DAMAGE. 27 * 28 * NETLOGIC_BSD 29 * $FreeBSD$ 30 */ 31 32#ifndef _NLM_HAL_PIC_H 33#define _NLM_HAL_PIC_H 34 35/* PIC Specific registers */ 36#define PIC_CTRL 0x00 37 38/* PIC control register defines */ 39#define PIC_CTRL_ITV 32 /* interrupt timeout value */ 40#define PIC_CTRL_ICI 19 /* ICI interrupt timeout enable */ 41#define PIC_CTRL_ITE 18 /* interrupt timeout enable */ 42#define PIC_CTRL_STE 10 /* system timer interrupt enable */ 43#define PIC_CTRL_WWR1 8 /* watchdog 1 wraparound count for reset */ 44#define PIC_CTRL_WWR0 6 /* watchdog 0 wraparound count for reset */ 45#define PIC_CTRL_WWN1 4 /* watchdog 1 wraparound count for NMI */ 46#define PIC_CTRL_WWN0 2 /* watchdog 0 wraparound count for NMI */ 47#define PIC_CTRL_WTE 0 /* watchdog timer enable */ 48 49/* PIC Status register defines */ 50#define PIC_ICI_STATUS 33 /* ICI interrupt timeout status */ 51#define PIC_ITE_STATUS 32 /* interrupt timeout status */ 52#define PIC_STS_STATUS 4 /* System timer interrupt status */ 53#define PIC_WNS_STATUS 2 /* NMI status for watchdog timers */ 54#define PIC_WIS_STATUS 0 /* Interrupt status for watchdog timers */ 55 56/* PIC IPI control register offsets */ 57#define PIC_IPICTRL_NMI 32 58#define PIC_IPICTRL_RIV 20 /* received interrupt vector */ 59#define PIC_IPICTRL_IDB 16 /* interrupt destination base */ 60#define PIC_IPICTRL_DTE 0 /* interrupt destination thread enables */ 61 62/* PIC IRT register offsets */ 63#define PIC_IRT_ENABLE 31 64#define PIC_IRT_NMI 29 65#define PIC_IRT_SCH 28 /* Scheduling scheme */ 66#define PIC_IRT_RVEC 20 /* Interrupt receive vectors */ 67#define PIC_IRT_DT 19 /* Destination type */ 68#define PIC_IRT_DB 16 /* Destination base */ 69#define PIC_IRT_DTE 0 /* Destination thread enables */ 70 71#define PIC_BYTESWAP 0x02 72#define PIC_STATUS 0x04 73#define PIC_INTR_TIMEOUT 0x06 74#define PIC_ICI0_INTR_TIMEOUT 0x08 75#define PIC_ICI1_INTR_TIMEOUT 0x0a 76#define PIC_ICI2_INTR_TIMEOUT 0x0c 77#define PIC_IPI_CTL 0x0e 78#define PIC_INT_ACK 0x10 79#define PIC_INT_PENDING0 0x12 80#define PIC_INT_PENDING1 0x14 81#define PIC_INT_PENDING2 0x16 82 83#define PIC_WDOG0_MAXVAL 0x18 84#define PIC_WDOG0_COUNT 0x1a 85#define PIC_WDOG0_ENABLE0 0x1c 86#define PIC_WDOG0_ENABLE1 0x1e 87#define PIC_WDOG0_BEATCMD 0x20 88#define PIC_WDOG0_BEAT0 0x22 89#define PIC_WDOG0_BEAT1 0x24 90 91#define PIC_WDOG1_MAXVAL 0x26 92#define PIC_WDOG1_COUNT 0x28 93#define PIC_WDOG1_ENABLE0 0x2a 94#define PIC_WDOG1_ENABLE1 0x2c 95#define PIC_WDOG1_BEATCMD 0x2e 96#define PIC_WDOG1_BEAT0 0x30 97#define PIC_WDOG1_BEAT1 0x32 98 99#define PIC_WDOG_MAXVAL(i) (PIC_WDOG0_MAXVAL + ((i) ? 7 : 0)) 100#define PIC_WDOG_COUNT(i) (PIC_WDOG0_COUNT + ((i) ? 7 : 0)) 101#define PIC_WDOG_ENABLE0(i) (PIC_WDOG0_ENABLE0 + ((i) ? 7 : 0)) 102#define PIC_WDOG_ENABLE1(i) (PIC_WDOG0_ENABLE1 + ((i) ? 7 : 0)) 103#define PIC_WDOG_BEATCMD(i) (PIC_WDOG0_BEATCMD + ((i) ? 7 : 0)) 104#define PIC_WDOG_BEAT0(i) (PIC_WDOG0_BEAT0 + ((i) ? 7 : 0)) 105#define PIC_WDOG_BEAT1(i) (PIC_WDOG0_BEAT1 + ((i) ? 7 : 0)) 106 107#define PIC_TIMER0_MAXVAL 0x34 108#define PIC_TIMER1_MAXVAL 0x36 109#define PIC_TIMER2_MAXVAL 0x38 110#define PIC_TIMER3_MAXVAL 0x3a 111#define PIC_TIMER4_MAXVAL 0x3c 112#define PIC_TIMER5_MAXVAL 0x3e 113#define PIC_TIMER6_MAXVAL 0x40 114#define PIC_TIMER7_MAXVAL 0x42 115#define PIC_TIMER_MAXVAL(i) (PIC_TIMER0_MAXVAL + ((i) * 2)) 116 117#define PIC_TIMER0_COUNT 0x44 118#define PIC_TIMER1_COUNT 0x46 119#define PIC_TIMER2_COUNT 0x48 120#define PIC_TIMER3_COUNT 0x4a 121#define PIC_TIMER4_COUNT 0x4c 122#define PIC_TIMER5_COUNT 0x4e 123#define PIC_TIMER6_COUNT 0x50 124#define PIC_TIMER7_COUNT 0x52 125#define PIC_TIMER_COUNT(i) (PIC_TIMER0_COUNT + ((i) * 2)) 126 127#define PIC_ITE0_N0_N1 0x54 128#define PIC_ITE1_N0_N1 0x58 129#define PIC_ITE2_N0_N1 0x5c 130#define PIC_ITE3_N0_N1 0x60 131#define PIC_ITE4_N0_N1 0x64 132#define PIC_ITE5_N0_N1 0x68 133#define PIC_ITE6_N0_N1 0x6c 134#define PIC_ITE7_N0_N1 0x70 135#define PIC_ITE_N0_N1(i) (PIC_ITE0_N0_N1 + ((i) * 4)) 136 137#define PIC_ITE0_N2_N3 0x56 138#define PIC_ITE1_N2_N3 0x5a 139#define PIC_ITE2_N2_N3 0x5e 140#define PIC_ITE3_N2_N3 0x62 141#define PIC_ITE4_N2_N3 0x66 142#define PIC_ITE5_N2_N3 0x6a 143#define PIC_ITE6_N2_N3 0x6e 144#define PIC_ITE7_N2_N3 0x72 145#define PIC_ITE_N2_N3(i) (PIC_ITE0_N2_N3 + ((i) * 4)) 146 147#define PIC_IRT0 0x74 148#define PIC_IRT(i) (PIC_IRT0 + ((i) * 2)) 149 150#define TIMER_CYCLES_MAXVAL 0xffffffffffffffffULL 151 152/* 153 * IRT Map 154 */ 155#define PIC_NUM_IRTS 160 156 157#define PIC_IRT_WD_0_INDEX 0 158#define PIC_IRT_WD_1_INDEX 1 159#define PIC_IRT_WD_NMI_0_INDEX 2 160#define PIC_IRT_WD_NMI_1_INDEX 3 161#define PIC_IRT_TIMER_0_INDEX 4 162#define PIC_IRT_TIMER_1_INDEX 5 163#define PIC_IRT_TIMER_2_INDEX 6 164#define PIC_IRT_TIMER_3_INDEX 7 165#define PIC_IRT_TIMER_4_INDEX 8 166#define PIC_IRT_TIMER_5_INDEX 9 167#define PIC_IRT_TIMER_6_INDEX 10 168#define PIC_IRT_TIMER_7_INDEX 11 169#define PIC_IRT_CLOCK_INDEX PIC_IRT_TIMER_7_INDEX 170#define PIC_IRT_TIMER_INDEX(num) ((num) + PIC_IRT_TIMER_0_INDEX) 171 172 173/* 11 and 12 */ 174#define PIC_NUM_MSG_Q_IRTS 32 175#define PIC_IRT_MSG_Q0_INDEX 12 176#define PIC_IRT_MSG_Q_INDEX(qid) ((qid) + PIC_IRT_MSG_Q0_INDEX) 177/* 12 to 43 */ 178#define PIC_IRT_MSG_0_INDEX 44 179#define PIC_IRT_MSG_1_INDEX 45 180/* 44 and 45 */ 181#define PIC_NUM_PCIE_MSIX_IRTS 32 182#define PIC_IRT_PCIE_MSIX_0_INDEX 46 183#define PIC_IRT_PCIE_MSIX_INDEX(num) ((num) + PIC_IRT_PCIE_MSIX_0_INDEX) 184/* 46 to 77 */ 185#define PIC_NUM_PCIE_LINK_IRTS 4 186#define PIC_IRT_PCIE_LINK_0_INDEX 78 187#define PIC_IRT_PCIE_LINK_1_INDEX 79 188#define PIC_IRT_PCIE_LINK_2_INDEX 80 189#define PIC_IRT_PCIE_LINK_3_INDEX 81 190#define PIC_IRT_PCIE_LINK_INDEX(num) ((num) + PIC_IRT_PCIE_LINK_0_INDEX) 191/* 78 to 81 */ 192#define PIC_NUM_NA_IRTS 32 193/* 82 to 113 */ 194#define PIC_IRT_NA_0_INDEX 82 195#define PIC_IRT_NA_INDEX(num) ((num) + PIC_IRT_NA_0_INDEX) 196#define PIC_IRT_POE_INDEX 114 197 198#define PIC_NUM_USB_IRTS 6 199#define PIC_IRT_USB_0_INDEX 115 200#define PIC_IRT_EHCI_0_INDEX 115 201#define PIC_IRT_EHCI_1_INDEX 118 202#define PIC_IRT_USB_INDEX(num) ((num) + PIC_IRT_USB_0_INDEX) 203/* 115 to 120 */ 204#define PIC_IRT_GDX_INDEX 121 205#define PIC_IRT_SEC_INDEX 122 206#define PIC_IRT_RSA_INDEX 123 207 208#define PIC_NUM_COMP_IRTS 4 209#define PIC_IRT_COMP_0_INDEX 124 210#define PIC_IRT_COMP_INDEX(num) ((num) + PIC_IRT_COMP_0_INDEX) 211/* 124 to 127 */ 212#define PIC_IRT_GBU_INDEX 128 213#define PIC_IRT_ICC_0_INDEX 129 /* ICC - Inter Chip Coherency */ 214#define PIC_IRT_ICC_1_INDEX 130 215#define PIC_IRT_ICC_2_INDEX 131 216#define PIC_IRT_CAM_INDEX 132 217#define PIC_IRT_UART_0_INDEX 133 218#define PIC_IRT_UART_1_INDEX 134 219#define PIC_IRT_I2C_0_INDEX 135 220#define PIC_IRT_I2C_1_INDEX 136 221#define PIC_IRT_SYS_0_INDEX 137 222#define PIC_IRT_SYS_1_INDEX 138 223#define PIC_IRT_JTAG_INDEX 139 224#define PIC_IRT_PIC_INDEX 140 225#define PIC_IRT_NBU_INDEX 141 226#define PIC_IRT_TCU_INDEX 142 227#define PIC_IRT_GCU_INDEX 143 /* GBC - Global Coherency */ 228#define PIC_IRT_DMC_0_INDEX 144 229#define PIC_IRT_DMC_1_INDEX 145 230 231#define PIC_NUM_GPIO_IRTS 4 232#define PIC_IRT_GPIO_0_INDEX 146 233#define PIC_IRT_GPIO_INDEX(num) ((num) + PIC_IRT_GPIO_0_INDEX) 234 235/* 146 to 149 */ 236#define PIC_IRT_NOR_INDEX 150 237#define PIC_IRT_NAND_INDEX 151 238#define PIC_IRT_SPI_INDEX 152 239#define PIC_IRT_MMC_INDEX 153 240 241#define PIC_CLOCK_TIMER 7 242#define PIC_IRQ_BASE 8 243 244#if !defined(LOCORE) && !defined(__ASSEMBLY__) 245 246#define PIC_IRT_FIRST_IRQ (PIC_IRQ_BASE) 247#define PIC_IRT_LAST_IRQ 63 248#define PIC_IRQ_IS_IRT(irq) ((irq) >= PIC_IRT_FIRST_IRQ) 249 250/* 251 * Misc 252 */ 253#define PIC_IRT_VALID 1 254#define PIC_LOCAL_SCHEDULING 1 255#define PIC_GLOBAL_SCHEDULING 0 256 257#define nlm_read_pic_reg(b, r) nlm_read_reg64(b, r) 258#define nlm_write_pic_reg(b, r, v) nlm_write_reg64(b, r, v) 259#define nlm_get_pic_pcibase(node) nlm_pcicfg_base(XLP_IO_PIC_OFFSET(node)) 260#define nlm_get_pic_regbase(node) (nlm_get_pic_pcibase(node) + XLP_IO_PCI_HDRSZ) 261 262/* IRT and h/w interrupt routines */ 263static inline int 264nlm_pic_read_irt(uint64_t base, int irt_index) 265{ 266 return nlm_read_pic_reg(base, PIC_IRT(irt_index)); 267} 268 269static inline void 270nlm_pic_send_ipi(uint64_t base, int cpu, int vec, int nmi) 271{ 272 uint64_t ipi; 273 int node, ncpu; 274 275 node = cpu / 32; 276 ncpu = cpu & 0x1f; 277 ipi = ((uint64_t)nmi << 31) | (vec << 20) | (node << 17) | 278 (1 << (cpu & 0xf)); 279 if (ncpu > 15) 280 ipi |= 0x10000; /* Setting bit 16 to select cpus 16-31 */ 281 282 nlm_write_pic_reg(base, PIC_IPI_CTL, ipi); 283} 284 285static inline uint64_t 286nlm_pic_read_control(uint64_t base) 287{ 288 return nlm_read_pic_reg(base, PIC_CTRL); 289} 290 291static inline void 292nlm_pic_write_control(uint64_t base, uint64_t control) 293{ 294 nlm_write_pic_reg(base, PIC_CTRL, control); 295} 296 297static inline void 298nlm_pic_update_control(uint64_t base, uint64_t control) 299{ 300 uint64_t val; 301 302 val = nlm_read_pic_reg(base, PIC_CTRL); 303 nlm_write_pic_reg(base, PIC_CTRL, control | val); 304} 305 306static inline void 307nlm_pic_ack(uint64_t base, int irt_num) 308{ 309 nlm_write_pic_reg(base, PIC_INT_ACK, irt_num); 310 311 /* Ack the Status register for Watchdog & System timers */ 312 if (irt_num < 12) 313 nlm_write_pic_reg(base, PIC_STATUS, (1 << irt_num)); 314} 315 316static inline void 317nlm_set_irt_to_cpu(uint64_t base, int irt, int cpu) 318{ 319 uint64_t val; 320 321 val = nlm_read_pic_reg(base, PIC_IRT(irt)); 322 val |= cpu & 0xf; 323 if (cpu > 15) 324 val |= 1 << 16; 325 nlm_write_pic_reg(base, PIC_IRT(irt), val); 326} 327 328static inline void 329nlm_pic_write_irt(uint64_t base, int irt_num, int en, int nmi, 330 int sch, int vec, int dt, int db, int dte) 331{ 332 uint64_t val; 333 334 val = (((uint64_t)en & 0x1) << 31) | ((nmi & 0x1) << 29) | 335 ((sch & 0x1) << 28) | ((vec & 0x3f) << 20) | 336 ((dt & 0x1) << 19) | ((db & 0x7) << 16) | 337 (dte & 0xffff); 338 339 nlm_write_pic_reg(base, PIC_IRT(irt_num), val); 340} 341 342static inline void 343nlm_pic_write_irt_direct(uint64_t base, int irt_num, int en, int nmi, 344 int sch, int vec, int cpu) 345{ 346 nlm_pic_write_irt(base, irt_num, en, nmi, sch, vec, 1, 347 (cpu >> 4), /* thread group */ 348 1 << (cpu & 0xf)); /* thread mask */ 349} 350 351static inline uint64_t 352nlm_pic_read_timer(uint64_t base, int timer) 353{ 354 return nlm_read_pic_reg(base, PIC_TIMER_COUNT(timer)); 355} 356 357static inline void 358nlm_pic_write_timer(uint64_t base, int timer, uint64_t value) 359{ 360 nlm_write_pic_reg(base, PIC_TIMER_COUNT(timer), value); 361} 362 363static inline void 364nlm_pic_set_timer(uint64_t base, int timer, uint64_t value, int irq, int cpu) 365{ 366 uint64_t pic_ctrl = nlm_read_pic_reg(base, PIC_CTRL); 367 int en; 368 369 en = (irq > 0); 370 nlm_write_pic_reg(base, PIC_TIMER_MAXVAL(timer), value); 371 nlm_pic_write_irt_direct(base, PIC_IRT_TIMER_INDEX(timer), 372 en, 0, 0, irq, cpu); 373 374 /* enable the timer */ 375 pic_ctrl |= (1 << (PIC_CTRL_STE + timer)); 376 nlm_write_pic_reg(base, PIC_CTRL, pic_ctrl); 377} 378 379#endif /* __ASSEMBLY__ */ 380#endif /* _NLM_HAL_PIC_H */ 381