1178172Simp/* $OpenBSD: regnum.h,v 1.3 1999/01/27 04:46:06 imp Exp $ */ 2178172Simp 3178172Simp/*- 4178172Simp * Copyright (c) 1988 University of Utah. 5178172Simp * Copyright (c) 1992, 1993 6178172Simp * The Regents of the University of California. All rights reserved. 7178172Simp * 8178172Simp * This code is derived from software contributed to Berkeley by 9178172Simp * the Systems Programming Group of the University of Utah Computer 10178172Simp * Science Department and Ralph Campbell. 11178172Simp * 12178172Simp * Redistribution and use in source and binary forms, with or without 13178172Simp * modification, are permitted provided that the following conditions 14178172Simp * are met: 15178172Simp * 1. Redistributions of source code must retain the above copyright 16178172Simp * notice, this list of conditions and the following disclaimer. 17178172Simp * 2. Redistributions in binary form must reproduce the above copyright 18178172Simp * notice, this list of conditions and the following disclaimer in the 19178172Simp * documentation and/or other materials provided with the distribution. 20178172Simp * 4. Neither the name of the University nor the names of its contributors 21178172Simp * may be used to endorse or promote products derived from this software 22178172Simp * without specific prior written permission. 23178172Simp * 24178172Simp * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 25178172Simp * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 26178172Simp * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 27178172Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 28178172Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 29178172Simp * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 30178172Simp * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 31178172Simp * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 32178172Simp * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 33178172Simp * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 34178172Simp * SUCH DAMAGE. 35178172Simp * 36178172Simp * from: Utah Hdr: reg.h 1.1 90/07/09 37178172Simp * @(#)reg.h 8.2 (Berkeley) 1/11/94 38178172Simp * JNPR: regnum.h,v 1.6 2007/08/09 11:23:32 katta 39178172Simp * $FreeBSD$ 40178172Simp */ 41178172Simp 42178172Simp#ifndef _MACHINE_REGNUM_H_ 43178172Simp#define _MACHINE_REGNUM_H_ 44178172Simp 45178172Simp/* This must match the numbers 46178172Simp * in pcb.h and is used by 47178172Simp * swtch.S 48178172Simp */ 49211862Sjchandra#define PREG_S0 0 50211862Sjchandra#define PREG_S1 1 51211862Sjchandra#define PREG_S2 2 52211862Sjchandra#define PREG_S3 3 53211862Sjchandra#define PREG_S4 4 54211862Sjchandra#define PREG_S5 5 55211862Sjchandra#define PREG_S6 6 56211862Sjchandra#define PREG_S7 7 57211862Sjchandra#define PREG_SP 8 58211862Sjchandra#define PREG_S8 9 59211862Sjchandra#define PREG_RA 10 60211862Sjchandra#define PREG_SR 11 61211862Sjchandra#define PREG_GP 12 62211862Sjchandra#define PREG_PC 13 63178172Simp 64178172Simp/* 65178172Simp * Location of the saved registers relative to ZERO. 66178172Simp * This must match struct trapframe defined in frame.h exactly. 67178172Simp */ 68178172Simp#define ZERO 0 69178172Simp#define AST 1 70178172Simp#define V0 2 71178172Simp#define V1 3 72178172Simp#define A0 4 73178172Simp#define A1 5 74178172Simp#define A2 6 75178172Simp#define A3 7 76178172Simp#define T0 8 77178172Simp#define T1 9 78178172Simp#define T2 10 79178172Simp#define T3 11 80202031Simp#define TA0 12 81202031Simp#define TA1 13 82202031Simp#define TA2 14 83202031Simp#define TA3 15 84178172Simp#define S0 16 85178172Simp#define S1 17 86178172Simp#define S2 18 87178172Simp#define S3 19 88178172Simp#define S4 20 89178172Simp#define S5 21 90178172Simp#define S6 22 91178172Simp#define S7 23 92178172Simp#define T8 24 93178172Simp#define T9 25 94178172Simp#define K0 26 95178172Simp#define K1 27 96178172Simp#define GP 28 97178172Simp#define SP 29 98178172Simp#define S8 30 99178172Simp#define RA 31 100178172Simp#define SR 32 101178172Simp#define PS SR /* alias for SR */ 102178172Simp#define MULLO 33 103178172Simp#define MULHI 34 104178172Simp#define BADVADDR 35 105178172Simp#define CAUSE 36 106178172Simp#define PC 37 107178172Simp/* 108178172Simp * IC is valid only on RM7K and RM9K processors. Access to this is 109178172Simp * controlled by IC_INT_REG which defined in kernel config 110178172Simp */ 111178172Simp#define IC 38 112178172Simp#define DUMMY 39 /* for 8 byte alignment */ 113178172Simp#define NUMSAVEREGS 40 114178172Simp 115178172Simp/* 116178172Simp * Index of FP registers in 'struct frame', counting from the beginning 117178172Simp * of the frame (i.e., including the general registers). 118178172Simp */ 119178172Simp#define FPBASE NUMSAVEREGS 120178172Simp#define F0 (FPBASE+0) 121178172Simp#define F1 (FPBASE+1) 122178172Simp#define F2 (FPBASE+2) 123178172Simp#define F3 (FPBASE+3) 124178172Simp#define F4 (FPBASE+4) 125178172Simp#define F5 (FPBASE+5) 126178172Simp#define F6 (FPBASE+6) 127178172Simp#define F7 (FPBASE+7) 128178172Simp#define F8 (FPBASE+8) 129178172Simp#define F9 (FPBASE+9) 130178172Simp#define F10 (FPBASE+10) 131178172Simp#define F11 (FPBASE+11) 132178172Simp#define F12 (FPBASE+12) 133178172Simp#define F13 (FPBASE+13) 134178172Simp#define F14 (FPBASE+14) 135178172Simp#define F15 (FPBASE+15) 136178172Simp#define F16 (FPBASE+16) 137178172Simp#define F17 (FPBASE+17) 138178172Simp#define F18 (FPBASE+18) 139178172Simp#define F19 (FPBASE+19) 140178172Simp#define F20 (FPBASE+20) 141178172Simp#define F21 (FPBASE+21) 142178172Simp#define F22 (FPBASE+22) 143178172Simp#define F23 (FPBASE+23) 144178172Simp#define F24 (FPBASE+24) 145178172Simp#define F25 (FPBASE+25) 146178172Simp#define F26 (FPBASE+26) 147178172Simp#define F27 (FPBASE+27) 148178172Simp#define F28 (FPBASE+28) 149178172Simp#define F29 (FPBASE+29) 150178172Simp#define F30 (FPBASE+30) 151178172Simp#define F31 (FPBASE+31) 152178172Simp#define FSR (FPBASE+32) 153178172Simp#define FSR_DUMMY (FPBASE+33) /* For 8 byte alignment */ 154178172Simp 155178172Simp#define NUMFPREGS 34 156178172Simp 157178172Simp#define NREGS (NUMSAVEREGS + NUMFPREGS) 158178172Simp 159178172Simp/* 160178172Simp * Index of FP registers in 'struct frame', relative to the base 161178172Simp * of the FP registers in frame (i.e., *not* including the general 162178172Simp * registers). 163178172Simp */ 164178172Simp#define F0_NUM (0) 165178172Simp#define F1_NUM (1) 166178172Simp#define F2_NUM (2) 167178172Simp#define F3_NUM (3) 168178172Simp#define F4_NUM (4) 169178172Simp#define F5_NUM (5) 170178172Simp#define F6_NUM (6) 171178172Simp#define F7_NUM (7) 172178172Simp#define F8_NUM (8) 173178172Simp#define F9_NUM (9) 174178172Simp#define F10_NUM (10) 175178172Simp#define F11_NUM (11) 176178172Simp#define F12_NUM (12) 177178172Simp#define F13_NUM (13) 178178172Simp#define F14_NUM (14) 179178172Simp#define F15_NUM (15) 180178172Simp#define F16_NUM (16) 181178172Simp#define F17_NUM (17) 182178172Simp#define F18_NUM (18) 183178172Simp#define F19_NUM (19) 184178172Simp#define F20_NUM (20) 185178172Simp#define F21_NUM (21) 186178172Simp#define F22_NUM (22) 187178172Simp#define F23_NUM (23) 188178172Simp#define F24_NUM (24) 189178172Simp#define F25_NUM (25) 190178172Simp#define F26_NUM (26) 191178172Simp#define F27_NUM (27) 192178172Simp#define F28_NUM (28) 193178172Simp#define F29_NUM (29) 194178172Simp#define F30_NUM (30) 195178172Simp#define F31_NUM (31) 196178172Simp#define FSR_NUM (32) 197178172Simp 198178172Simp#endif /* !_MACHINE_REGNUM_H_ */ 199