uart_cpu_octeonusart.c revision 202985 
1/*-
2 * Copyright (c) 2009 M. Warner Losh <imp@FreeBSD.org>
3 * Copyright (c) 2006 Wojciech A. Koszek <wkoszek@FreeBSD.org>
4 * All rights reserved.
5 *
6 * Redistribution and use in source and binary forms, with or without
7 * modification, are permitted provided that the following conditions
8 * are met:
9 * 1. Redistributions of source code must retain the above copyright
10 *    notice, this list of conditions and the following disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 *
27 * $Id$
28 */
29#include "opt_uart.h"
30
31#include <sys/cdefs.h>
32__FBSDID("$FreeBSD: head/sys/mips/cavium/uart_cpu_octeonusart.c 202985 2010-01-25 19:27:20Z imp $");
33
34#include <sys/param.h>
35#include <sys/systm.h>
36#include <sys/bus.h>
37#include <sys/cons.h>
38
39#include <machine/bus.h>
40
41#include <dev/uart/uart.h>
42#include <dev/uart/uart_cpu.h>
43
44#include <mips/cavium/octeon_pcmap_regs.h>
45
46bus_space_tag_t uart_bus_space_io;
47bus_space_tag_t uart_bus_space_mem;
48
49#include <sys/cdefs.h>
50__FBSDID("$FreeBSD: head/sys/mips/cavium/uart_cpu_octeonusart.c 202985 2010-01-25 19:27:20Z imp $");
51
52#include <sys/param.h>
53#include <sys/systm.h>
54#include <sys/bus.h>
55#include <sys/kernel.h>
56#include <sys/malloc.h>
57#include <sys/ktr.h>
58
59#include <vm/vm.h>
60#include <vm/pmap.h>
61#include <vm/vm_kern.h>
62#include <vm/vm_extern.h>
63
64#include <machine/bus.h>
65#include <machine/cache.h>
66
67/*
68 * Specailized uart bus space.  We present a 1 apart byte oriented
69 * bus to the outside world, but internally translate to/from the 8-apart
70 * 64-bit word bus that's on the octeon.  We only support simple read/write
71 * in this space.  Everything else is undefined.
72 */
73static uint8_t
74ou_bs_r_1(void *t, bus_space_handle_t handle, bus_size_t offset)
75{
76
77	return (oct_read64(handle + (offset << 3)));
78}
79
80static uint16_t
81ou_bs_r_2(void *t, bus_space_handle_t handle, bus_size_t offset)
82{
83
84	return (oct_read64(handle + (offset << 3)));
85}
86
87static uint32_t
88ou_bs_r_4(void *t, bus_space_handle_t handle, bus_size_t offset)
89{
90
91	return (oct_read64(handle + (offset << 3)));
92}
93
94static uint64_t
95ou_bs_r_8(void *t, bus_space_handle_t handle, bus_size_t offset)
96{
97
98	return (oct_read64(handle + (offset << 3)));
99}
100
101static void
102ou_bs_w_1(void *t, bus_space_handle_t bsh, bus_size_t offset, uint8_t value)
103{
104
105	oct_write64(bsh + (offset << 3), value);
106}
107
108static void
109ou_bs_w_2(void *t, bus_space_handle_t bsh, bus_size_t offset, uint16_t value)
110{
111
112	oct_write64(bsh + (offset << 3), value);
113}
114
115static void
116ou_bs_w_4(void *t, bus_space_handle_t bsh, bus_size_t offset, uint32_t value)
117{
118
119	oct_write64(bsh + (offset << 3), value);
120}
121
122static void
123ou_bs_w_8(void *t, bus_space_handle_t bsh, bus_size_t offset, uint64_t value)
124{
125
126	oct_write64(bsh + (offset << 3), value);
127}
128
129struct bus_space octeon_uart_tag = {
130	.bs_map = generic_bs_map,
131	.bs_unmap = generic_bs_unmap,
132	.bs_subregion = generic_bs_subregion,
133	.bs_barrier = generic_bs_barrier,
134	.bs_r_1 = ou_bs_r_1,
135	.bs_r_2 = ou_bs_r_2,
136	.bs_r_4 = ou_bs_r_4,
137	.bs_r_8 = ou_bs_r_8,
138	.bs_w_1 = ou_bs_w_1,
139	.bs_w_2 = ou_bs_w_2,
140	.bs_w_4 = ou_bs_w_4,
141	.bs_w_8 = ou_bs_w_8,
142};
143
144extern struct uart_class uart_oct16550_class;
145
146int
147uart_cpu_eqres(struct uart_bas *b1, struct uart_bas *b2)
148{
149
150	return ((b1->bsh == b2->bsh && b1->bst == b2->bst) ? 1 : 0);
151}
152
153int
154uart_cpu_getdev(int devtype, struct uart_devinfo *di)
155{
156	struct uart_class *class = &uart_oct16550_class;
157
158	/*
159	 * These fields need to be setup corretly for uart_getenv to
160	 * work in all cases.
161	 */
162	uart_bus_space_io = NULL;		/* No io map for this device */
163	uart_bus_space_mem = &octeon_uart_tag;
164	di->bas.bst = uart_bus_space_mem;
165
166	/*
167	 * If env specification for UART exists it takes precedence:
168	 * hw.uart.console="mm:0xf1012000" or similar
169	 */
170	if (uart_getenv(devtype, di, class) == 0)
171		return (0);
172
173	/*
174	 * Fallback to UART0 for console.
175	 */
176	di->ops = uart_getops(class);
177	di->bas.chan = 0;
178	if (bus_space_map(di->bas.bst, OCTEON_MIO_UART0, OCTEON_MIO_UART_SIZE,
179	    0, &di->bas.bsh) != 0)
180		return (ENXIO);
181	di->bas.regshft = 0;
182	di->bas.rclk = 0;
183	di->baudrate = 115200;
184	di->databits = 8;
185	di->stopbits = 1;
186	di->parity = UART_PARITY_NONE;
187
188	return (0);
189}
190