1/* $NetBSD: adm5120reg.h,v 1.1 2007/03/20 08:52:03 dyoung Exp $ */ 2 3/*- 4 * Copyright (c) 2007 Ruslan Ermilov and Vsevolod Lobko. 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or 8 * without modification, are permitted provided that the following 9 * conditions are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above 13 * copyright notice, this list of conditions and the following 14 * disclaimer in the documentation and/or other materials provided 15 * with the distribution. 16 * 3. The names of the authors may not be used to endorse or promote 17 * products derived from this software without specific prior 18 * written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHORS ``AS IS'' AND ANY 21 * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, 22 * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A 23 * PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, 25 * OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 26 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, 27 * OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR 29 * TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT 30 * OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY 31 * OF SUCH DAMAGE. 32 * 33 * $FreeBSD$ 34 */ 35 36#ifndef _ADM5120REG_H_ 37#define _ADM5120REG_H_ 38 39/* Helpers from NetBSD */ 40/* __BIT(n): nth bit, where __BIT(0) == 0x1. */ 41#define __BIT(__n) \ 42 (((__n) >= NBBY * sizeof(uintmax_t)) ? 0 : ((uintmax_t)1 << (__n))) 43 44/* __BITS(m, n): bits m through n, m < n. */ 45#define __BITS(__m, __n) \ 46 ((__BIT(MAX((__m), (__n)) + 1) - 1) ^ (__BIT(MIN((__m), (__n))) - 1)) 47 48/* Last byte of physical address space. */ 49#define ADM5120_TOP 0x1fffffff 50#define ADM5120_BOTTOM 0x0 51 52/* Flash addresses */ 53#define ADM5120_BASE_SRAM0 0x1fc00000 54 55/* UARTs */ 56#define ADM5120_BASE_UART1 0x12800000 57#define ADM5120_BASE_UART0 0x12600000 58 59/* ICU */ 60#define ADM5120_BASE_ICU 0x12200000 61#define ICU_STATUS_REG 0x00 62#define ICU_RAW_STATUS_REG 0x04 63#define ICU_ENABLE_REG 0x08 64#define ICU_DISABLE_REG 0x0c 65#define ICU_SOFT_REG 0x10 66#define ICU_MODE_REG 0x14 67#define ICU_FIQ_STATUS_REG 0x18 68#define ICU_TESTSRC_REG 0x1c 69#define ICU_SRCSEL_REG 0x20 70#define ICU_LEVEL_REG 0x24 71#define ICU_INT_MASK 0x3ff 72 73/* Switch */ 74#define ADM5120_BASE_SWITCH 0x12000000 75#define SW_CODE_REG 0x00 76#define CLKS_MASK 0x00300000 77#define CLKS_175MHZ 0x00000000 78#define CLKS_200MHZ 0x00100000 79#define SW_SFTRES_REG 0x04 80#define SW_MEMCONT_REG 0x1c 81#define SDRAM_SIZE_4MBYTES 0x0001 82#define SDRAM_SIZE_8MBYTES 0x0002 83#define SDRAM_SIZE_16MBYTES 0x0003 84#define SDRAM_SIZE_64MBYTES 0x0004 85#define SDRAM_SIZE_128MBYTES 0x0005 86#define SDRAM_SIZE_MASK 0x0007 87#define SRAM0_SIZE_SHIFT 8 88#define SRAM1_SIZE_SHIFT 16 89#define SRAM_MASK 0x0007 90#define SRAM_SSIZE 0x40000 91 92#define ADM5120_BASE_PCI_CONFDATA 0x115ffff8 93#define ADM5120_BASE_PCI_CONFADDR 0x115ffff0 94#define ADM5120_BASE_PCI_IO 0x11500000 95#define ADM5120_BASE_PCI_MEM 0x11400000 96#define ADM5120_BASE_USB 0x11200000 97#define ADM5120_BASE_MPMC 0x11000000 98#define ADM5120_BASE_EXTIO1 0x10e00000 99#define ADM5120_BASE_EXTIO0 0x10c00000 100#define ADM5120_BASE_RSVD0 0x10800000 101#define ADM5120_BASE_SRAM1 0x10000000 102 103#define _REG_READ(b, o) *((volatile uint32_t *)MIPS_PHYS_TO_KSEG1((b) + (o))) 104#define SW_READ(o) _REG_READ(ADM5120_BASE_SWITCH, o) 105 106#define _REG_WRITE(b, o, v) (_REG_READ(b, o)) = (v) 107#define SW_WRITE(o, v) _REG_WRITE(ADM5120_BASE_SWITCH,o, v) 108 109/* USB */ 110 111/* Watchdog Timers: base address is switch controller */ 112 113#define ADM5120_WDOG0 0x00c0 114#define ADM5120_WDOG1 0x00c4 115 116#define ADM5120_WDOG0_WTTR __BIT(31) /* 0: do not reset, 117 * 1: reset on wdog expiration 118 */ 119#define ADM5120_WDOG1_WDE __BIT(31) /* 0: deactivate, 120 * 1: drop all CPU-bound 121 * packets, disable flow 122 * control on all ports. 123 */ 124#define ADM5120_WDOG_WTS_MASK __BITS(30, 16) /* Watchdog Timer Set: 125 * timer expires when it 126 * reaches WTS. Units of 127 * 10ms. 128 */ 129#define ADM5120_WDOG_RSVD __BIT(15) 130#define ADM5120_WDOG_WT_MASK __BITS(14, 0) /* Watchdog Timer: 131 * counts up, write to clear. 132 */ 133 134/* GPIO: base address is switch controller */ 135#define ADM5120_GPIO0 0x00b8 136 137#define ADM5120_GPIO0_OV __BITS(31, 24) /* rw: output value */ 138#define ADM5120_GPIO0_OE __BITS(23, 16) /* rw: output enable, 139 * bit[n] = 0 -> input 140 * bit[n] = 1 -> output 141 */ 142#define ADM5120_GPIO0_IV __BITS(15, 8) /* ro: input value */ 143#define ADM5120_GPIO0_RSVD __BITS(7, 0) /* rw: reserved */ 144 145#define ADM5120_GPIO2 0x00bc 146#define ADM5120_GPIO2_EW __BIT(6) /* 1: enable wait state pin, 147 * pin GPIO[0], for GPIO[1] 148 * or GPIO[3] Chip Select: 149 * memory controller waits for 150 * WAIT# inactive (high). 151 */ 152#define ADM5120_GPIO2_CSX1 __BIT(5) /* 1: GPIO[3:4] act as 153 * Chip Select for 154 * External I/O 1 (CSX1) 155 * and External Interrupt 1 156 * (INTX1), respectively. 157 * 0: CSX1/INTX1 disabled 158 */ 159#define ADM5120_GPIO2_CSX0 __BIT(4) /* 1: GPIO[1:2] act as 160 * Chip Select for 161 * External I/O 0 (CSX0) 162 * and External Interrupt 0 163 * (INTX0), respectively. 164 * 0: CSX0/INTX0 disabled 165 */ 166 167/* MultiPort Memory Controller (MPMC) */ 168 169#define ADM5120_MPMC_CONTROL 0x000 170#define ADM5120_MPMC_CONTROL_DWB __BIT(3) /* write 1 to 171 * drain write 172 * buffers. write 0 173 * for normal buffer 174 * operation. 175 */ 176#define ADM5120_MPMC_CONTROL_LPM __BIT(2) /* 1: activate low-power 177 * mode. SDRAM is 178 * still refreshed. 179 */ 180#define ADM5120_MPMC_CONTROL_AM __BIT(1) /* 1: address mirror: 181 * static memory 182 * chip select 0 183 * is mapped to chip 184 * select 1. 185 */ 186#define ADM5120_MPMC_CONTROL_ME __BIT(0) /* 0: disable MPMC. 187 * DRAM is not 188 * refreshed. 189 * 1: enable MPMC. 190 */ 191 192#define ADM5120_MPMC_STATUS 0x004 193#define ADM5120_MPMC_STATUS_SRA __BIT(2) /* read-only 194 * MPMC operating mode 195 * indication, 196 * 1: self-refresh 197 * acknowledge 198 * 0: normal mode 199 */ 200#define ADM5120_MPMC_STATUS_WBS __BIT(1) /* read-only 201 * write-buffer status, 202 * 0: buffers empty 203 * 1: contain data 204 */ 205#define ADM5120_MPMC_STATUS_BU __BIT(0) /* read-only MPMC 206 * "busy" indication, 207 * 0: MPMC idle 208 * 1: MPMC is performing 209 * memory transactions 210 */ 211 212#define ADM5120_MPMC_SEW 0x080 213#define ADM5120_MPMC_SEW_RSVD __BITS(31, 10) 214#define ADM5120_MPMC_SEW_EWTO __BITS(9, 0) /* timeout access after 215 * 16 * (n + 1) clock cycles 216 * (XXX which clock?) 217 */ 218 219#define ADM5120_MPMC_SC(__i) (0x200 + 0x020 * (__i)) 220#define ADM5120_MPMC_SC_RSVD0 __BITS(31, 21) 221#define ADM5120_MPMC_SC_WP __BIT(20) /* 1: write protect */ 222#define ADM5120_MPMC_SC_BE __BIT(20) /* 1: enable write buffer */ 223#define ADM5120_MPMC_SC_RSVD1 __BITS(18, 9) 224#define ADM5120_MPMC_SC_EW __BIT(8) /* 1: enable extended wait; 225 */ 226#define ADM5120_MPMC_SC_BLS __BIT(7) /* 0: byte line state pins 227 * are active high on read, 228 * active low on write. 229 * 230 * 1: byte line state pins 231 * are active low on read and 232 * on write. 233 */ 234#define ADM5120_MPMC_SC_CCP __BIT(6) /* 0: chip select is active low, 235 * 1: active high 236 */ 237#define ADM5120_MPMC_SC_RSVD2 __BITS(5, 4) 238#define ADM5120_MPMC_SC_PM __BIT(3) /* 0: page mode disabled, 239 * 1: enable asynchronous 240 * page mode four 241 */ 242#define ADM5120_MPMC_SC_RSVD3 __BIT(2) 243#define ADM5120_MPMC_SC_MW_MASK __BITS(1, 0) /* memory width, bits */ 244#define ADM5120_MPMC_SC_MW_8B __SHIFTIN(0, ADM5120_MPMC_SC_MW_MASK) 245#define ADM5120_MPMC_SC_MW_16B __SHIFTIN(1, ADM5120_MPMC_SC_MW_MASK) 246#define ADM5120_MPMC_SC_MW_32B __SHIFTIN(2, ADM5120_MPMC_SC_MW_MASK) 247#define ADM5120_MPMC_SC_MW_RSVD __SHIFTIN(3, ADM5120_MPMC_SC_MW_MASK) 248 249#define ADM5120_MPMC_SWW(__i) (0x204 + 0x020 * (__i)) 250#define ADM5120_MPMC_SWW_RSVD __BITS(31, 4) 251#define ADM5120_MPMC_SWW_WWE __BITS(3, 0) /* delay (n + 1) * HCLK cycles 252 * after asserting chip select 253 * (CS) before asserting write 254 * enable (WE) 255 */ 256 257#define ADM5120_MPMC_SWO(__i) (0x208 + 0x020 * (__i)) 258#define ADM5120_MPMC_SWO_RSVD __BITS(31, 4) 259#define ADM5120_MPMC_SWO_WOE __BITS(3, 0) /* delay n * HCLK cycles 260 * after asserting chip select 261 * before asserting output 262 * enable (OE) 263 */ 264 265#define ADM5120_MPMC_SWR(__i) (0x20c + 0x020 * (__i)) 266#define ADM5120_MPMC_SWR_RSVD __BITS(31, 5) 267#define ADM5120_MPMC_SWR_NMRW __BITS(4, 0) /* read wait states for 268 * either first page-mode 269 * access or for non-page mode 270 * read, (n + 1) * HCLK cycles 271 */ 272 273#define ADM5120_MPMC_SWP(__i) (0x210 + 0x020 * (__i)) 274#define ADM5120_MPMC_SWP_RSVD __BITS(31, 5) 275#define ADM5120_MPMC_SWP_WPS __BITS(4, 0) /* read wait states for 276 * second and subsequent 277 * page-mode read, 278 * (n + 1) * HCLK cycles 279 */ 280 281#define ADM5120_MPMC_SWWR(__i) (0x214 + 0x020 * (__i)) 282#define ADM5120_MPMC_SWWR_RSVD __BITS(31, 5) 283#define ADM5120_MPMC_SWWR_WWS __BITS(4, 0) /* write wait states after 284 * the first read (??), 285 * (n + 2) * HCLK cycles 286 */ 287 288#define ADM5120_MPMC_SWT(__i) (0x218 + 0x020 * (__i)) 289#define ADM5120_MPMC_SWT_RSVD __BITS(31, 4) 290#define ADM5120_MPMC_SWT_WAITTURN __BITS(3, 0) /* bus turnaround time, 291 * (n + 1) * HCLK cycles 292 */ 293 294#endif /* _ADM5120REG_H_ */ 295