1/*- 2 * Copyright (c) 2003 John Baldwin <jhb@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $FreeBSD$ 27 */ 28 29#ifndef _MACHINE_APICVAR_H_ 30#define _MACHINE_APICVAR_H_ 31 32/* 33 * Local && I/O APIC variable definitions. 34 */ 35 36/* 37 * Layout of local APIC interrupt vectors: 38 * 39 * 0xff (255) +-------------+ 40 * | | 15 (Spurious / IPIs / Local Interrupts) 41 * 0xf0 (240) +-------------+ 42 * | | 14 (I/O Interrupts / Timer) 43 * 0xe0 (224) +-------------+ 44 * | | 13 (I/O Interrupts) 45 * 0xd0 (208) +-------------+ 46 * | | 12 (I/O Interrupts) 47 * 0xc0 (192) +-------------+ 48 * | | 11 (I/O Interrupts) 49 * 0xb0 (176) +-------------+ 50 * | | 10 (I/O Interrupts) 51 * 0xa0 (160) +-------------+ 52 * | | 9 (I/O Interrupts) 53 * 0x90 (144) +-------------+ 54 * | | 8 (I/O Interrupts / System Calls) 55 * 0x80 (128) +-------------+ 56 * | | 7 (I/O Interrupts) 57 * 0x70 (112) +-------------+ 58 * | | 6 (I/O Interrupts) 59 * 0x60 (96) +-------------+ 60 * | | 5 (I/O Interrupts) 61 * 0x50 (80) +-------------+ 62 * | | 4 (I/O Interrupts) 63 * 0x40 (64) +-------------+ 64 * | | 3 (I/O Interrupts) 65 * 0x30 (48) +-------------+ 66 * | | 2 (ATPIC Interrupts) 67 * 0x20 (32) +-------------+ 68 * | | 1 (Exceptions, traps, faults, etc.) 69 * 0x10 (16) +-------------+ 70 * | | 0 (Exceptions, traps, faults, etc.) 71 * 0x00 (0) +-------------+ 72 * 73 * Note: 0x80 needs to be handled specially and not allocated to an 74 * I/O device! 75 */ 76 77#define MAX_APIC_ID 0xfe 78#define APIC_ID_ALL 0xff 79 80/* I/O Interrupts are used for external devices such as ISA, PCI, etc. */ 81#define APIC_IO_INTS (IDT_IO_INTS + 16) 82#define APIC_NUM_IOINTS 191 83 84/* The timer interrupt is used for clock handling and drives hardclock, etc. */ 85#define APIC_TIMER_INT (APIC_IO_INTS + APIC_NUM_IOINTS) 86 87/* 88 ********************* !!! WARNING !!! ****************************** 89 * Each local apic has an interrupt receive fifo that is two entries deep 90 * for each interrupt priority class (higher 4 bits of interrupt vector). 91 * Once the fifo is full the APIC can no longer receive interrupts for this 92 * class and sending IPIs from other CPUs will be blocked. 93 * To avoid deadlocks there should be no more than two IPI interrupts 94 * pending at the same time. 95 * Currently this is guaranteed by dividing the IPIs in two groups that have 96 * each at most one IPI interrupt pending. The first group is protected by the 97 * smp_ipi_mtx and waits for the completion of the IPI (Only one IPI user 98 * at a time) The second group uses a single interrupt and a bitmap to avoid 99 * redundant IPI interrupts. 100 */ 101 102/* Interrupts for local APIC LVT entries other than the timer. */ 103#ifdef XEN 104/* These are the Xen i386 APIC definitions */ 105#define APIC_LOCAL_INTS 240 106#define APIC_ERROR_INT APIC_LOCAL_INTS 107#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 108#define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 109#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 110 111#define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 112#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 113#define IPI_INVLPG (APIC_IPI_INTS + 2) 114#define IPI_INVLRNG (APIC_IPI_INTS + 3) 115#define IPI_INVLCACHE (APIC_IPI_INTS + 4) 116#define IPI_LAZYPMAP (APIC_IPI_INTS + 5) /* Lazy pmap release. */ 117/* Vector to handle bitmap based IPIs */ 118#define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6) 119 120/* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */ 121#define IPI_AST 0 /* Generate software trap. */ 122#define IPI_PREEMPT 1 123#define IPI_HARDCLOCK 2 124#define IPI_BITMAP_LAST IPI_HARDCLOCK 125#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 126 127#define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */ 128#define IPI_SUSPEND (APIC_IPI_INTS + 8) /* Suspend CPU until restarted. */ 129#define IPI_STOP_HARD (APIC_IPI_INTS + 9) /* Stop CPU with a NMI. */ 130 131#else /* XEN */ 132/* These are the normal i386 APIC definitions */ 133#define APIC_LOCAL_INTS 240 134#define APIC_ERROR_INT APIC_LOCAL_INTS 135#define APIC_THERMAL_INT (APIC_LOCAL_INTS + 1) 136#define APIC_CMC_INT (APIC_LOCAL_INTS + 2) 137#define APIC_IPI_INTS (APIC_LOCAL_INTS + 3) 138 139#define IPI_RENDEZVOUS (APIC_IPI_INTS) /* Inter-CPU rendezvous. */ 140#define IPI_INVLTLB (APIC_IPI_INTS + 1) /* TLB Shootdown IPIs */ 141#define IPI_INVLPG (APIC_IPI_INTS + 2) 142#define IPI_INVLRNG (APIC_IPI_INTS + 3) 143#define IPI_INVLCACHE (APIC_IPI_INTS + 4) 144#define IPI_LAZYPMAP (APIC_IPI_INTS + 5) /* Lazy pmap release. */ 145/* Vector to handle bitmap based IPIs */ 146#define IPI_BITMAP_VECTOR (APIC_IPI_INTS + 6) 147 148/* IPIs handled by IPI_BITMAPED_VECTOR (XXX ups is there a better place?) */ 149#define IPI_AST 0 /* Generate software trap. */ 150#define IPI_PREEMPT 1 151#define IPI_HARDCLOCK 2 152#define IPI_BITMAP_LAST IPI_HARDCLOCK 153#define IPI_IS_BITMAPED(x) ((x) <= IPI_BITMAP_LAST) 154 155#define IPI_STOP (APIC_IPI_INTS + 7) /* Stop CPU until restarted. */ 156#define IPI_SUSPEND (APIC_IPI_INTS + 8) /* Suspend CPU until restarted. */ 157#define IPI_STOP_HARD (APIC_IPI_INTS + 9) /* Stop CPU with a NMI. */ 158#endif /* XEN */ 159 160/* 161 * The spurious interrupt can share the priority class with the IPIs since 162 * it is not a normal interrupt. (Does not use the APIC's interrupt fifo) 163 */ 164#define APIC_SPURIOUS_INT 255 165 166#define LVT_LINT0 0 167#define LVT_LINT1 1 168#define LVT_TIMER 2 169#define LVT_ERROR 3 170#define LVT_PMC 4 171#define LVT_THERMAL 5 172#define LVT_CMCI 6 173#define LVT_MAX LVT_CMCI 174 175#ifndef LOCORE 176 177#define APIC_IPI_DEST_SELF -1 178#define APIC_IPI_DEST_ALL -2 179#define APIC_IPI_DEST_OTHERS -3 180 181#define APIC_BUS_UNKNOWN -1 182#define APIC_BUS_ISA 0 183#define APIC_BUS_EISA 1 184#define APIC_BUS_PCI 2 185#define APIC_BUS_MAX APIC_BUS_PCI 186 187/* 188 * An APIC enumerator is a psuedo bus driver that enumerates APIC's including 189 * CPU's and I/O APIC's. 190 */ 191struct apic_enumerator { 192 const char *apic_name; 193 int (*apic_probe)(void); 194 int (*apic_probe_cpus)(void); 195 int (*apic_setup_local)(void); 196 int (*apic_setup_io)(void); 197 SLIST_ENTRY(apic_enumerator) apic_next; 198}; 199 200inthand_t 201 IDTVEC(apic_isr1), IDTVEC(apic_isr2), IDTVEC(apic_isr3), 202 IDTVEC(apic_isr4), IDTVEC(apic_isr5), IDTVEC(apic_isr6), 203 IDTVEC(apic_isr7), IDTVEC(cmcint), IDTVEC(errorint), 204 IDTVEC(spuriousint), IDTVEC(timerint); 205 206extern vm_paddr_t lapic_paddr; 207extern int apic_cpuids[]; 208 209u_int apic_alloc_vector(u_int apic_id, u_int irq); 210u_int apic_alloc_vectors(u_int apic_id, u_int *irqs, u_int count, 211 u_int align); 212void apic_disable_vector(u_int apic_id, u_int vector); 213void apic_enable_vector(u_int apic_id, u_int vector); 214void apic_free_vector(u_int apic_id, u_int vector, u_int irq); 215u_int apic_idt_to_irq(u_int apic_id, u_int vector); 216void apic_register_enumerator(struct apic_enumerator *enumerator); 217u_int apic_cpuid(u_int apic_id); 218void *ioapic_create(vm_paddr_t addr, int32_t apic_id, int intbase); 219int ioapic_disable_pin(void *cookie, u_int pin); 220int ioapic_get_vector(void *cookie, u_int pin); 221void ioapic_register(void *cookie); 222int ioapic_remap_vector(void *cookie, u_int pin, int vector); 223int ioapic_set_bus(void *cookie, u_int pin, int bus_type); 224int ioapic_set_extint(void *cookie, u_int pin); 225int ioapic_set_nmi(void *cookie, u_int pin); 226int ioapic_set_polarity(void *cookie, u_int pin, enum intr_polarity pol); 227int ioapic_set_triggermode(void *cookie, u_int pin, 228 enum intr_trigger trigger); 229int ioapic_set_smi(void *cookie, u_int pin); 230void lapic_create(u_int apic_id, int boot_cpu); 231void lapic_disable(void); 232void lapic_disable_pmc(void); 233void lapic_dump(const char *str); 234void lapic_enable_cmc(void); 235int lapic_enable_pmc(void); 236void lapic_eoi(void); 237int lapic_id(void); 238void lapic_init(vm_paddr_t addr); 239int lapic_intr_pending(u_int vector); 240void lapic_ipi_raw(register_t icrlo, u_int dest); 241void lapic_ipi_vectored(u_int vector, int dest); 242int lapic_ipi_wait(int delay); 243void lapic_handle_cmc(void); 244void lapic_handle_error(void); 245void lapic_handle_intr(int vector, struct trapframe *frame); 246void lapic_handle_timer(struct trapframe *frame); 247void lapic_reenable_pmc(void); 248void lapic_set_logical_id(u_int apic_id, u_int cluster, u_int cluster_id); 249int lapic_set_lvt_mask(u_int apic_id, u_int lvt, u_char masked); 250int lapic_set_lvt_mode(u_int apic_id, u_int lvt, u_int32_t mode); 251int lapic_set_lvt_polarity(u_int apic_id, u_int lvt, 252 enum intr_polarity pol); 253int lapic_set_lvt_triggermode(u_int apic_id, u_int lvt, 254 enum intr_trigger trigger); 255void lapic_set_tpr(u_int vector); 256void lapic_setup(int boot); 257 258#endif /* !LOCORE */ 259#endif /* _MACHINE_APICVAR_H_ */ 260