if_wb.c revision 68621
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 68621 2000-11-11 23:08:22Z bmilekic $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#include <vm/vm.h> /* for vtophys */ 106#include <vm/pmap.h> /* for vtophys */ 107#include <machine/bus_memio.h> 108#include <machine/bus_pio.h> 109#include <machine/bus.h> 110#include <machine/resource.h> 111#include <sys/bus.h> 112#include <sys/rman.h> 113 114#include <pci/pcireg.h> 115#include <pci/pcivar.h> 116 117#include <dev/mii/mii.h> 118#include <dev/mii/miivar.h> 119 120/* "controller miibus0" required. See GENERIC if you get errors here. */ 121#include "miibus_if.h" 122 123#define WB_USEIOSPACE 124 125#include <pci/if_wbreg.h> 126 127MODULE_DEPEND(wb, miibus, 1, 1, 1); 128 129#ifndef lint 130static const char rcsid[] = 131 "$FreeBSD: head/sys/pci/if_wb.c 68621 2000-11-11 23:08:22Z bmilekic $"; 132#endif 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct wb_type wb_devs[] = { 138 { WB_VENDORID, WB_DEVICEID_840F, 139 "Winbond W89C840F 10/100BaseTX" }, 140 { CP_VENDORID, CP_DEVICEID_RL100, 141 "Compex RL100-ATX 10/100baseTX" }, 142 { 0, 0, NULL } 143}; 144 145static int wb_probe __P((device_t)); 146static int wb_attach __P((device_t)); 147static int wb_detach __P((device_t)); 148 149static void wb_bfree __P((caddr_t, void *args)); 150static int wb_newbuf __P((struct wb_softc *, 151 struct wb_chain_onefrag *, 152 struct mbuf *)); 153static int wb_encap __P((struct wb_softc *, struct wb_chain *, 154 struct mbuf *)); 155 156static void wb_rxeof __P((struct wb_softc *)); 157static void wb_rxeoc __P((struct wb_softc *)); 158static void wb_txeof __P((struct wb_softc *)); 159static void wb_txeoc __P((struct wb_softc *)); 160static void wb_intr __P((void *)); 161static void wb_tick __P((void *)); 162static void wb_start __P((struct ifnet *)); 163static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 164static void wb_init __P((void *)); 165static void wb_stop __P((struct wb_softc *)); 166static void wb_watchdog __P((struct ifnet *)); 167static void wb_shutdown __P((device_t)); 168static int wb_ifmedia_upd __P((struct ifnet *)); 169static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 170 171static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 172static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 173static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 174 int, int)); 175static void wb_mii_sync __P((struct wb_softc *)); 176static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 177static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 178static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 179 180static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 181static u_int8_t wb_calchash __P((caddr_t)); 182static void wb_setmulti __P((struct wb_softc *)); 183static void wb_reset __P((struct wb_softc *)); 184static void wb_fixmedia __P((struct wb_softc *)); 185static int wb_list_rx_init __P((struct wb_softc *)); 186static int wb_list_tx_init __P((struct wb_softc *)); 187 188static int wb_miibus_readreg __P((device_t, int, int)); 189static int wb_miibus_writereg __P((device_t, int, int, int)); 190static void wb_miibus_statchg __P((device_t)); 191 192#ifdef WB_USEIOSPACE 193#define WB_RES SYS_RES_IOPORT 194#define WB_RID WB_PCI_LOIO 195#else 196#define WB_RES SYS_RES_MEMORY 197#define WB_RID WB_PCI_LOMEM 198#endif 199 200static device_method_t wb_methods[] = { 201 /* Device interface */ 202 DEVMETHOD(device_probe, wb_probe), 203 DEVMETHOD(device_attach, wb_attach), 204 DEVMETHOD(device_detach, wb_detach), 205 DEVMETHOD(device_shutdown, wb_shutdown), 206 207 /* bus interface, for miibus */ 208 DEVMETHOD(bus_print_child, bus_generic_print_child), 209 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 210 211 /* MII interface */ 212 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 213 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 214 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 215 { 0, 0 } 216}; 217 218static driver_t wb_driver = { 219 "wb", 220 wb_methods, 221 sizeof(struct wb_softc) 222}; 223 224static devclass_t wb_devclass; 225 226DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 227DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 228 229#define WB_SETBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) | x) 232 233#define WB_CLRBIT(sc, reg, x) \ 234 CSR_WRITE_4(sc, reg, \ 235 CSR_READ_4(sc, reg) & ~x) 236 237#define SIO_SET(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) | x) 240 241#define SIO_CLR(x) \ 242 CSR_WRITE_4(sc, WB_SIO, \ 243 CSR_READ_4(sc, WB_SIO) & ~x) 244 245/* 246 * Send a read command and address to the EEPROM, check for ACK. 247 */ 248static void wb_eeprom_putbyte(sc, addr) 249 struct wb_softc *sc; 250 int addr; 251{ 252 register int d, i; 253 254 d = addr | WB_EECMD_READ; 255 256 /* 257 * Feed in each bit and stobe the clock. 258 */ 259 for (i = 0x400; i; i >>= 1) { 260 if (d & i) { 261 SIO_SET(WB_SIO_EE_DATAIN); 262 } else { 263 SIO_CLR(WB_SIO_EE_DATAIN); 264 } 265 DELAY(100); 266 SIO_SET(WB_SIO_EE_CLK); 267 DELAY(150); 268 SIO_CLR(WB_SIO_EE_CLK); 269 DELAY(100); 270 } 271 272 return; 273} 274 275/* 276 * Read a word of data stored in the EEPROM at address 'addr.' 277 */ 278static void wb_eeprom_getword(sc, addr, dest) 279 struct wb_softc *sc; 280 int addr; 281 u_int16_t *dest; 282{ 283 register int i; 284 u_int16_t word = 0; 285 286 /* Enter EEPROM access mode. */ 287 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 288 289 /* 290 * Send address of word we want to read. 291 */ 292 wb_eeprom_putbyte(sc, addr); 293 294 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 295 296 /* 297 * Start reading bits from EEPROM. 298 */ 299 for (i = 0x8000; i; i >>= 1) { 300 SIO_SET(WB_SIO_EE_CLK); 301 DELAY(100); 302 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 303 word |= i; 304 SIO_CLR(WB_SIO_EE_CLK); 305 DELAY(100); 306 } 307 308 /* Turn off EEPROM access mode. */ 309 CSR_WRITE_4(sc, WB_SIO, 0); 310 311 *dest = word; 312 313 return; 314} 315 316/* 317 * Read a sequence of words from the EEPROM. 318 */ 319static void wb_read_eeprom(sc, dest, off, cnt, swap) 320 struct wb_softc *sc; 321 caddr_t dest; 322 int off; 323 int cnt; 324 int swap; 325{ 326 int i; 327 u_int16_t word = 0, *ptr; 328 329 for (i = 0; i < cnt; i++) { 330 wb_eeprom_getword(sc, off + i, &word); 331 ptr = (u_int16_t *)(dest + (i * 2)); 332 if (swap) 333 *ptr = ntohs(word); 334 else 335 *ptr = word; 336 } 337 338 return; 339} 340 341/* 342 * Sync the PHYs by setting data bit and strobing the clock 32 times. 343 */ 344static void wb_mii_sync(sc) 345 struct wb_softc *sc; 346{ 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359} 360 361/* 362 * Clock a series of bits through the MII. 363 */ 364static void wb_mii_send(sc, bits, cnt) 365 struct wb_softc *sc; 366 u_int32_t bits; 367 int cnt; 368{ 369 int i; 370 371 SIO_CLR(WB_SIO_MII_CLK); 372 373 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 374 if (bits & i) { 375 SIO_SET(WB_SIO_MII_DATAIN); 376 } else { 377 SIO_CLR(WB_SIO_MII_DATAIN); 378 } 379 DELAY(1); 380 SIO_CLR(WB_SIO_MII_CLK); 381 DELAY(1); 382 SIO_SET(WB_SIO_MII_CLK); 383 } 384} 385 386/* 387 * Read an PHY register through the MII. 388 */ 389static int wb_mii_readreg(sc, frame) 390 struct wb_softc *sc; 391 struct wb_mii_frame *frame; 392 393{ 394 int i, ack; 395 396 WB_LOCK(sc); 397 398 /* 399 * Set up frame for RX. 400 */ 401 frame->mii_stdelim = WB_MII_STARTDELIM; 402 frame->mii_opcode = WB_MII_READOP; 403 frame->mii_turnaround = 0; 404 frame->mii_data = 0; 405 406 CSR_WRITE_4(sc, WB_SIO, 0); 407 408 /* 409 * Turn on data xmit. 410 */ 411 SIO_SET(WB_SIO_MII_DIR); 412 413 wb_mii_sync(sc); 414 415 /* 416 * Send command/address info. 417 */ 418 wb_mii_send(sc, frame->mii_stdelim, 2); 419 wb_mii_send(sc, frame->mii_opcode, 2); 420 wb_mii_send(sc, frame->mii_phyaddr, 5); 421 wb_mii_send(sc, frame->mii_regaddr, 5); 422 423 /* Idle bit */ 424 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 425 DELAY(1); 426 SIO_SET(WB_SIO_MII_CLK); 427 DELAY(1); 428 429 /* Turn off xmit. */ 430 SIO_CLR(WB_SIO_MII_DIR); 431 /* Check for ack */ 432 SIO_CLR(WB_SIO_MII_CLK); 433 DELAY(1); 434 SIO_SET(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_CLR(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_SET(WB_SIO_MII_CLK); 440 DELAY(1); 441 442 /* 443 * Now try reading data bits. If the ack failed, we still 444 * need to clock through 16 cycles to keep the PHY(s) in sync. 445 */ 446 if (ack) { 447 for(i = 0; i < 16; i++) { 448 SIO_CLR(WB_SIO_MII_CLK); 449 DELAY(1); 450 SIO_SET(WB_SIO_MII_CLK); 451 DELAY(1); 452 } 453 goto fail; 454 } 455 456 for (i = 0x8000; i; i >>= 1) { 457 SIO_CLR(WB_SIO_MII_CLK); 458 DELAY(1); 459 if (!ack) { 460 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 461 frame->mii_data |= i; 462 DELAY(1); 463 } 464 SIO_SET(WB_SIO_MII_CLK); 465 DELAY(1); 466 } 467 468fail: 469 470 SIO_CLR(WB_SIO_MII_CLK); 471 DELAY(1); 472 SIO_SET(WB_SIO_MII_CLK); 473 DELAY(1); 474 475 WB_UNLOCK(sc); 476 477 if (ack) 478 return(1); 479 return(0); 480} 481 482/* 483 * Write to a PHY register through the MII. 484 */ 485static int wb_mii_writereg(sc, frame) 486 struct wb_softc *sc; 487 struct wb_mii_frame *frame; 488 489{ 490 WB_LOCK(sc); 491 492 /* 493 * Set up frame for TX. 494 */ 495 496 frame->mii_stdelim = WB_MII_STARTDELIM; 497 frame->mii_opcode = WB_MII_WRITEOP; 498 frame->mii_turnaround = WB_MII_TURNAROUND; 499 500 /* 501 * Turn on data output. 502 */ 503 SIO_SET(WB_SIO_MII_DIR); 504 505 wb_mii_sync(sc); 506 507 wb_mii_send(sc, frame->mii_stdelim, 2); 508 wb_mii_send(sc, frame->mii_opcode, 2); 509 wb_mii_send(sc, frame->mii_phyaddr, 5); 510 wb_mii_send(sc, frame->mii_regaddr, 5); 511 wb_mii_send(sc, frame->mii_turnaround, 2); 512 wb_mii_send(sc, frame->mii_data, 16); 513 514 /* Idle bit. */ 515 SIO_SET(WB_SIO_MII_CLK); 516 DELAY(1); 517 SIO_CLR(WB_SIO_MII_CLK); 518 DELAY(1); 519 520 /* 521 * Turn off xmit. 522 */ 523 SIO_CLR(WB_SIO_MII_DIR); 524 525 WB_UNLOCK(sc); 526 527 return(0); 528} 529 530static int wb_miibus_readreg(dev, phy, reg) 531 device_t dev; 532 int phy, reg; 533{ 534 struct wb_softc *sc; 535 struct wb_mii_frame frame; 536 537 sc = device_get_softc(dev); 538 539 bzero((char *)&frame, sizeof(frame)); 540 541 frame.mii_phyaddr = phy; 542 frame.mii_regaddr = reg; 543 wb_mii_readreg(sc, &frame); 544 545 return(frame.mii_data); 546} 547 548static int wb_miibus_writereg(dev, phy, reg, data) 549 device_t dev; 550 int phy, reg, data; 551{ 552 struct wb_softc *sc; 553 struct wb_mii_frame frame; 554 555 sc = device_get_softc(dev); 556 557 bzero((char *)&frame, sizeof(frame)); 558 559 frame.mii_phyaddr = phy; 560 frame.mii_regaddr = reg; 561 frame.mii_data = data; 562 563 wb_mii_writereg(sc, &frame); 564 565 return(0); 566} 567 568static void wb_miibus_statchg(dev) 569 device_t dev; 570{ 571 struct wb_softc *sc; 572 struct mii_data *mii; 573 574 sc = device_get_softc(dev); 575 WB_LOCK(sc); 576 mii = device_get_softc(sc->wb_miibus); 577 wb_setcfg(sc, mii->mii_media_active); 578 WB_UNLOCK(sc); 579 580 return; 581} 582 583static u_int8_t wb_calchash(addr) 584 caddr_t addr; 585{ 586 u_int32_t crc, carry; 587 int i, j; 588 u_int8_t c; 589 590 /* Compute CRC for the address value. */ 591 crc = 0xFFFFFFFF; /* initial value */ 592 593 for (i = 0; i < 6; i++) { 594 c = *(addr + i); 595 for (j = 0; j < 8; j++) { 596 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 597 crc <<= 1; 598 c >>= 1; 599 if (carry) 600 crc = (crc ^ 0x04c11db6) | carry; 601 } 602 } 603 604 /* 605 * return the filter bit position 606 * Note: I arrived at the following nonsense 607 * through experimentation. It's not the usual way to 608 * generate the bit position but it's the only thing 609 * I could come up with that works. 610 */ 611 return(~(crc >> 26) & 0x0000003F); 612} 613 614/* 615 * Program the 64-bit multicast hash filter. 616 */ 617static void wb_setmulti(sc) 618 struct wb_softc *sc; 619{ 620 struct ifnet *ifp; 621 int h = 0; 622 u_int32_t hashes[2] = { 0, 0 }; 623 struct ifmultiaddr *ifma; 624 u_int32_t rxfilt; 625 int mcnt = 0; 626 627 ifp = &sc->arpcom.ac_if; 628 629 rxfilt = CSR_READ_4(sc, WB_NETCFG); 630 631 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 632 rxfilt |= WB_NETCFG_RX_MULTI; 633 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 634 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 635 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 636 return; 637 } 638 639 /* first, zot all the existing hash bits */ 640 CSR_WRITE_4(sc, WB_MAR0, 0); 641 CSR_WRITE_4(sc, WB_MAR1, 0); 642 643 /* now program new ones */ 644 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 645 ifma = ifma->ifma_link.le_next) { 646 if (ifma->ifma_addr->sa_family != AF_LINK) 647 continue; 648 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 649 if (h < 32) 650 hashes[0] |= (1 << h); 651 else 652 hashes[1] |= (1 << (h - 32)); 653 mcnt++; 654 } 655 656 if (mcnt) 657 rxfilt |= WB_NETCFG_RX_MULTI; 658 else 659 rxfilt &= ~WB_NETCFG_RX_MULTI; 660 661 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 662 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 663 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 664 665 return; 666} 667 668/* 669 * The Winbond manual states that in order to fiddle with the 670 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 671 * first have to put the transmit and/or receive logic in the idle state. 672 */ 673static void wb_setcfg(sc, media) 674 struct wb_softc *sc; 675 u_int32_t media; 676{ 677 int i, restart = 0; 678 679 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 680 restart = 1; 681 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 682 683 for (i = 0; i < WB_TIMEOUT; i++) { 684 DELAY(10); 685 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 686 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 687 break; 688 } 689 690 if (i == WB_TIMEOUT) 691 printf("wb%d: failed to force tx and " 692 "rx to idle state\n", sc->wb_unit); 693 } 694 695 if (IFM_SUBTYPE(media) == IFM_10_T) 696 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 697 else 698 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 699 700 if ((media & IFM_GMASK) == IFM_FDX) 701 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 702 else 703 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 704 705 if (restart) 706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 707 708 return; 709} 710 711static void wb_reset(sc) 712 struct wb_softc *sc; 713{ 714 register int i; 715 struct mii_data *mii; 716 717 CSR_WRITE_4(sc, WB_NETCFG, 0); 718 CSR_WRITE_4(sc, WB_BUSCTL, 0); 719 CSR_WRITE_4(sc, WB_TXADDR, 0); 720 CSR_WRITE_4(sc, WB_RXADDR, 0); 721 722 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 723 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 724 725 for (i = 0; i < WB_TIMEOUT; i++) { 726 DELAY(10); 727 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 728 break; 729 } 730 if (i == WB_TIMEOUT) 731 printf("wb%d: reset never completed!\n", sc->wb_unit); 732 733 /* Wait a little while for the chip to get its brains in order. */ 734 DELAY(1000); 735 736 if (sc->wb_miibus == NULL) 737 return; 738 739 mii = device_get_softc(sc->wb_miibus); 740 if (mii == NULL) 741 return; 742 743 if (mii->mii_instance) { 744 struct mii_softc *miisc; 745 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 746 miisc = LIST_NEXT(miisc, mii_list)) 747 mii_phy_reset(miisc); 748 } 749 750 return; 751} 752 753static void wb_fixmedia(sc) 754 struct wb_softc *sc; 755{ 756 struct mii_data *mii = NULL; 757 struct ifnet *ifp; 758 u_int32_t media; 759 760 if (sc->wb_miibus == NULL) 761 return; 762 763 mii = device_get_softc(sc->wb_miibus); 764 ifp = &sc->arpcom.ac_if; 765 766 mii_pollstat(mii); 767 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 768 media = mii->mii_media_active & ~IFM_10_T; 769 media |= IFM_100_TX; 770 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 771 media = mii->mii_media_active & ~IFM_100_TX; 772 media |= IFM_10_T; 773 } else 774 return; 775 776 ifmedia_set(&mii->mii_media, media); 777 778 return; 779} 780 781/* 782 * Probe for a Winbond chip. Check the PCI vendor and device 783 * IDs against our list and return a device name if we find a match. 784 */ 785static int wb_probe(dev) 786 device_t dev; 787{ 788 struct wb_type *t; 789 790 t = wb_devs; 791 792 while(t->wb_name != NULL) { 793 if ((pci_get_vendor(dev) == t->wb_vid) && 794 (pci_get_device(dev) == t->wb_did)) { 795 device_set_desc(dev, t->wb_name); 796 return(0); 797 } 798 t++; 799 } 800 801 return(ENXIO); 802} 803 804/* 805 * Attach the interface. Allocate softc structures, do ifmedia 806 * setup and ethernet/BPF attach. 807 */ 808static int wb_attach(dev) 809 device_t dev; 810{ 811 u_char eaddr[ETHER_ADDR_LEN]; 812 u_int32_t command; 813 struct wb_softc *sc; 814 struct ifnet *ifp; 815 int unit, error = 0, rid; 816 817 sc = device_get_softc(dev); 818 unit = device_get_unit(dev); 819 820 /* 821 * Handle power management nonsense. 822 */ 823 824 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 825 if (command == 0x01) { 826 827 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 828 if (command & WB_PSTATE_MASK) { 829 u_int32_t iobase, membase, irq; 830 831 /* Save important PCI config data. */ 832 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 833 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 834 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 835 836 /* Reset the power state. */ 837 printf("wb%d: chip is in D%d power mode " 838 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 839 command &= 0xFFFFFFFC; 840 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 841 842 /* Restore PCI config data. */ 843 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 844 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 845 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 846 } 847 } 848 849 /* 850 * Map control/status registers. 851 */ 852 command = pci_read_config(dev, PCIR_COMMAND, 4); 853 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 854 pci_write_config(dev, PCIR_COMMAND, command, 4); 855 command = pci_read_config(dev, PCIR_COMMAND, 4); 856 857#ifdef WB_USEIOSPACE 858 if (!(command & PCIM_CMD_PORTEN)) { 859 printf("wb%d: failed to enable I/O ports!\n", unit); 860 error = ENXIO; 861 goto fail; 862 } 863#else 864 if (!(command & PCIM_CMD_MEMEN)) { 865 printf("wb%d: failed to enable memory mapping!\n", unit); 866 error = ENXIO; 867 goto fail; 868 } 869#endif 870 871 rid = WB_RID; 872 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 873 0, ~0, 1, RF_ACTIVE); 874 875 if (sc->wb_res == NULL) { 876 printf("wb%d: couldn't map ports/memory\n", unit); 877 error = ENXIO; 878 goto fail; 879 } 880 881 sc->wb_btag = rman_get_bustag(sc->wb_res); 882 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 883 884 /* Allocate interrupt */ 885 rid = 0; 886 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 887 RF_SHAREABLE | RF_ACTIVE); 888 889 if (sc->wb_irq == NULL) { 890 printf("wb%d: couldn't map interrupt\n", unit); 891 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 892 error = ENXIO; 893 goto fail; 894 } 895 896 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 897 wb_intr, sc, &sc->wb_intrhand); 898 899 if (error) { 900 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 901 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 902 printf("wb%d: couldn't set up irq\n", unit); 903 goto fail; 904 } 905 906 /* Save the cache line size. */ 907 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 908 909 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_DEF); 910 WB_LOCK(sc); 911 912 /* Reset the adapter. */ 913 wb_reset(sc); 914 915 /* 916 * Get station address from the EEPROM. 917 */ 918 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 919 920 /* 921 * A Winbond chip was detected. Inform the world. 922 */ 923 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 924 925 sc->wb_unit = unit; 926 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 927 928 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 929 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 930 931 if (sc->wb_ldata == NULL) { 932 printf("wb%d: no memory for list buffers!\n", unit); 933 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 934 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 935 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 936 error = ENXIO; 937 goto fail; 938 } 939 940 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 941 942 ifp = &sc->arpcom.ac_if; 943 ifp->if_softc = sc; 944 ifp->if_unit = unit; 945 ifp->if_name = "wb"; 946 ifp->if_mtu = ETHERMTU; 947 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 948 ifp->if_ioctl = wb_ioctl; 949 ifp->if_output = ether_output; 950 ifp->if_start = wb_start; 951 ifp->if_watchdog = wb_watchdog; 952 ifp->if_init = wb_init; 953 ifp->if_baudrate = 10000000; 954 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 955 956 /* 957 * Do MII setup. 958 */ 959 if (mii_phy_probe(dev, &sc->wb_miibus, 960 wb_ifmedia_upd, wb_ifmedia_sts)) { 961 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 962 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 963 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 964 free(sc->wb_ldata_ptr, M_DEVBUF); 965 error = ENXIO; 966 goto fail; 967 } 968 969 /* 970 * Call MI attach routine. 971 */ 972 ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 973 WB_UNLOCK(sc); 974 return(0); 975 976fail: 977 if (error) 978 device_delete_child(dev, sc->wb_miibus); 979 WB_UNLOCK(sc); 980 mtx_destroy(&sc->wb_mtx); 981 982 return(error); 983} 984 985static int wb_detach(dev) 986 device_t dev; 987{ 988 struct wb_softc *sc; 989 struct ifnet *ifp; 990 991 sc = device_get_softc(dev); 992 WB_LOCK(sc); 993 ifp = &sc->arpcom.ac_if; 994 995 wb_stop(sc); 996 ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 997 998 /* Delete any miibus and phy devices attached to this interface */ 999 bus_generic_detach(dev); 1000 device_delete_child(dev, sc->wb_miibus); 1001 1002 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1003 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1004 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1005 1006 free(sc->wb_ldata_ptr, M_DEVBUF); 1007 1008 WB_UNLOCK(sc); 1009 mtx_destroy(&sc->wb_mtx); 1010 1011 return(0); 1012} 1013 1014/* 1015 * Initialize the transmit descriptors. 1016 */ 1017static int wb_list_tx_init(sc) 1018 struct wb_softc *sc; 1019{ 1020 struct wb_chain_data *cd; 1021 struct wb_list_data *ld; 1022 int i; 1023 1024 cd = &sc->wb_cdata; 1025 ld = sc->wb_ldata; 1026 1027 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1028 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1029 if (i == (WB_TX_LIST_CNT - 1)) { 1030 cd->wb_tx_chain[i].wb_nextdesc = 1031 &cd->wb_tx_chain[0]; 1032 } else { 1033 cd->wb_tx_chain[i].wb_nextdesc = 1034 &cd->wb_tx_chain[i + 1]; 1035 } 1036 } 1037 1038 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1039 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1040 1041 return(0); 1042} 1043 1044 1045/* 1046 * Initialize the RX descriptors and allocate mbufs for them. Note that 1047 * we arrange the descriptors in a closed ring, so that the last descriptor 1048 * points back to the first. 1049 */ 1050static int wb_list_rx_init(sc) 1051 struct wb_softc *sc; 1052{ 1053 struct wb_chain_data *cd; 1054 struct wb_list_data *ld; 1055 int i; 1056 1057 cd = &sc->wb_cdata; 1058 ld = sc->wb_ldata; 1059 1060 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1061 cd->wb_rx_chain[i].wb_ptr = 1062 (struct wb_desc *)&ld->wb_rx_list[i]; 1063 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1064 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1065 return(ENOBUFS); 1066 if (i == (WB_RX_LIST_CNT - 1)) { 1067 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1068 ld->wb_rx_list[i].wb_next = 1069 vtophys(&ld->wb_rx_list[0]); 1070 } else { 1071 cd->wb_rx_chain[i].wb_nextdesc = 1072 &cd->wb_rx_chain[i + 1]; 1073 ld->wb_rx_list[i].wb_next = 1074 vtophys(&ld->wb_rx_list[i + 1]); 1075 } 1076 } 1077 1078 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1079 1080 return(0); 1081} 1082 1083static void wb_bfree(buf, args) 1084 caddr_t buf; 1085 void *args; 1086{ 1087 return; 1088} 1089 1090/* 1091 * Initialize an RX descriptor and attach an MBUF cluster. 1092 */ 1093static int wb_newbuf(sc, c, m) 1094 struct wb_softc *sc; 1095 struct wb_chain_onefrag *c; 1096 struct mbuf *m; 1097{ 1098 struct mbuf *m_new = NULL; 1099 1100 if (m == NULL) { 1101 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1102 if (m_new == NULL) { 1103 printf("wb%d: no memory for rx " 1104 "list -- packet dropped!\n", sc->wb_unit); 1105 return(ENOBUFS); 1106 } 1107 m_new->m_data = c->wb_buf; 1108 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1109 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1110 EXT_NET_DRV); 1111 } else { 1112 m_new = m; 1113 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1114 m_new->m_data = m_new->m_ext.ext_buf; 1115 } 1116 1117 m_adj(m_new, sizeof(u_int64_t)); 1118 1119 c->wb_mbuf = m_new; 1120 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1121 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1122 c->wb_ptr->wb_status = WB_RXSTAT; 1123 1124 return(0); 1125} 1126 1127/* 1128 * A frame has been uploaded: pass the resulting mbuf chain up to 1129 * the higher level protocols. 1130 */ 1131static void wb_rxeof(sc) 1132 struct wb_softc *sc; 1133{ 1134 struct ether_header *eh; 1135 struct mbuf *m = NULL; 1136 struct ifnet *ifp; 1137 struct wb_chain_onefrag *cur_rx; 1138 int total_len = 0; 1139 u_int32_t rxstat; 1140 1141 ifp = &sc->arpcom.ac_if; 1142 1143 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1144 WB_RXSTAT_OWN)) { 1145 struct mbuf *m0 = NULL; 1146 1147 cur_rx = sc->wb_cdata.wb_rx_head; 1148 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1149 1150 m = cur_rx->wb_mbuf; 1151 1152 if ((rxstat & WB_RXSTAT_MIIERR) || 1153 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1154 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1155 !(rxstat & WB_RXSTAT_LASTFRAG) || 1156 !(rxstat & WB_RXSTAT_RXCMP)) { 1157 ifp->if_ierrors++; 1158 wb_newbuf(sc, cur_rx, m); 1159 printf("wb%x: receiver babbling: possible chip " 1160 "bug, forcing reset\n", sc->wb_unit); 1161 wb_fixmedia(sc); 1162 wb_reset(sc); 1163 wb_init(sc); 1164 return; 1165 } 1166 1167 if (rxstat & WB_RXSTAT_RXERR) { 1168 ifp->if_ierrors++; 1169 wb_newbuf(sc, cur_rx, m); 1170 break; 1171 } 1172 1173 /* No errors; receive the packet. */ 1174 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1175 1176 /* 1177 * XXX The Winbond chip includes the CRC with every 1178 * received frame, and there's no way to turn this 1179 * behavior off (at least, I can't find anything in 1180 * the manual that explains how to do it) so we have 1181 * to trim off the CRC manually. 1182 */ 1183 total_len -= ETHER_CRC_LEN; 1184 1185 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1186 total_len + ETHER_ALIGN, 0, ifp, NULL); 1187 wb_newbuf(sc, cur_rx, m); 1188 if (m0 == NULL) { 1189 ifp->if_ierrors++; 1190 break; 1191 } 1192 m_adj(m0, ETHER_ALIGN); 1193 m = m0; 1194 1195 ifp->if_ipackets++; 1196 eh = mtod(m, struct ether_header *); 1197 1198 /* Remove header from mbuf and pass it on. */ 1199 m_adj(m, sizeof(struct ether_header)); 1200 ether_input(ifp, eh, m); 1201 } 1202} 1203 1204void wb_rxeoc(sc) 1205 struct wb_softc *sc; 1206{ 1207 wb_rxeof(sc); 1208 1209 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1210 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1211 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1212 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1213 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1214 1215 return; 1216} 1217 1218/* 1219 * A frame was downloaded to the chip. It's safe for us to clean up 1220 * the list buffers. 1221 */ 1222static void wb_txeof(sc) 1223 struct wb_softc *sc; 1224{ 1225 struct wb_chain *cur_tx; 1226 struct ifnet *ifp; 1227 1228 ifp = &sc->arpcom.ac_if; 1229 1230 /* Clear the timeout timer. */ 1231 ifp->if_timer = 0; 1232 1233 if (sc->wb_cdata.wb_tx_head == NULL) 1234 return; 1235 1236 /* 1237 * Go through our tx list and free mbufs for those 1238 * frames that have been transmitted. 1239 */ 1240 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1241 u_int32_t txstat; 1242 1243 cur_tx = sc->wb_cdata.wb_tx_head; 1244 txstat = WB_TXSTATUS(cur_tx); 1245 1246 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1247 break; 1248 1249 if (txstat & WB_TXSTAT_TXERR) { 1250 ifp->if_oerrors++; 1251 if (txstat & WB_TXSTAT_ABORT) 1252 ifp->if_collisions++; 1253 if (txstat & WB_TXSTAT_LATECOLL) 1254 ifp->if_collisions++; 1255 } 1256 1257 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1258 1259 ifp->if_opackets++; 1260 m_freem(cur_tx->wb_mbuf); 1261 cur_tx->wb_mbuf = NULL; 1262 1263 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1264 sc->wb_cdata.wb_tx_head = NULL; 1265 sc->wb_cdata.wb_tx_tail = NULL; 1266 break; 1267 } 1268 1269 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1270 } 1271 1272 return; 1273} 1274 1275/* 1276 * TX 'end of channel' interrupt handler. 1277 */ 1278static void wb_txeoc(sc) 1279 struct wb_softc *sc; 1280{ 1281 struct ifnet *ifp; 1282 1283 ifp = &sc->arpcom.ac_if; 1284 1285 ifp->if_timer = 0; 1286 1287 if (sc->wb_cdata.wb_tx_head == NULL) { 1288 ifp->if_flags &= ~IFF_OACTIVE; 1289 sc->wb_cdata.wb_tx_tail = NULL; 1290 } else { 1291 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1292 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1293 ifp->if_timer = 5; 1294 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1295 } 1296 } 1297 1298 return; 1299} 1300 1301static void wb_intr(arg) 1302 void *arg; 1303{ 1304 struct wb_softc *sc; 1305 struct ifnet *ifp; 1306 u_int32_t status; 1307 1308 sc = arg; 1309 WB_LOCK(sc); 1310 ifp = &sc->arpcom.ac_if; 1311 1312 if (!(ifp->if_flags & IFF_UP)) { 1313 WB_UNLOCK(sc); 1314 return; 1315 } 1316 1317 /* Disable interrupts. */ 1318 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1319 1320 for (;;) { 1321 1322 status = CSR_READ_4(sc, WB_ISR); 1323 if (status) 1324 CSR_WRITE_4(sc, WB_ISR, status); 1325 1326 if ((status & WB_INTRS) == 0) 1327 break; 1328 1329 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1330 ifp->if_ierrors++; 1331 wb_reset(sc); 1332 if (status & WB_ISR_RX_ERR) 1333 wb_fixmedia(sc); 1334 wb_init(sc); 1335 continue; 1336 } 1337 1338 if (status & WB_ISR_RX_OK) 1339 wb_rxeof(sc); 1340 1341 if (status & WB_ISR_RX_IDLE) 1342 wb_rxeoc(sc); 1343 1344 if (status & WB_ISR_TX_OK) 1345 wb_txeof(sc); 1346 1347 if (status & WB_ISR_TX_NOBUF) 1348 wb_txeoc(sc); 1349 1350 if (status & WB_ISR_TX_IDLE) { 1351 wb_txeof(sc); 1352 if (sc->wb_cdata.wb_tx_head != NULL) { 1353 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1354 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1355 } 1356 } 1357 1358 if (status & WB_ISR_TX_UNDERRUN) { 1359 ifp->if_oerrors++; 1360 wb_txeof(sc); 1361 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1362 /* Jack up TX threshold */ 1363 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1364 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1365 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1366 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1367 } 1368 1369 if (status & WB_ISR_BUS_ERR) { 1370 wb_reset(sc); 1371 wb_init(sc); 1372 } 1373 1374 } 1375 1376 /* Re-enable interrupts. */ 1377 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1378 1379 if (ifp->if_snd.ifq_head != NULL) { 1380 wb_start(ifp); 1381 } 1382 1383 WB_UNLOCK(sc); 1384 1385 return; 1386} 1387 1388static void wb_tick(xsc) 1389 void *xsc; 1390{ 1391 struct wb_softc *sc; 1392 struct mii_data *mii; 1393 1394 sc = xsc; 1395 WB_LOCK(sc); 1396 mii = device_get_softc(sc->wb_miibus); 1397 1398 mii_tick(mii); 1399 1400 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1401 1402 WB_UNLOCK(sc); 1403 1404 return; 1405} 1406 1407/* 1408 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1409 * pointers to the fragment pointers. 1410 */ 1411static int wb_encap(sc, c, m_head) 1412 struct wb_softc *sc; 1413 struct wb_chain *c; 1414 struct mbuf *m_head; 1415{ 1416 int frag = 0; 1417 struct wb_desc *f = NULL; 1418 int total_len; 1419 struct mbuf *m; 1420 1421 /* 1422 * Start packing the mbufs in this chain into 1423 * the fragment pointers. Stop when we run out 1424 * of fragments or hit the end of the mbuf chain. 1425 */ 1426 m = m_head; 1427 total_len = 0; 1428 1429 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1430 if (m->m_len != 0) { 1431 if (frag == WB_MAXFRAGS) 1432 break; 1433 total_len += m->m_len; 1434 f = &c->wb_ptr->wb_frag[frag]; 1435 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1436 if (frag == 0) { 1437 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1438 f->wb_status = 0; 1439 } else 1440 f->wb_status = WB_TXSTAT_OWN; 1441 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1442 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1443 frag++; 1444 } 1445 } 1446 1447 /* 1448 * Handle special case: we used up all 16 fragments, 1449 * but we have more mbufs left in the chain. Copy the 1450 * data into an mbuf cluster. Note that we don't 1451 * bother clearing the values in the other fragment 1452 * pointers/counters; it wouldn't gain us anything, 1453 * and would waste cycles. 1454 */ 1455 if (m != NULL) { 1456 struct mbuf *m_new = NULL; 1457 1458 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1459 if (m_new == NULL) { 1460 printf("wb%d: no memory for tx list", sc->wb_unit); 1461 return(1); 1462 } 1463 if (m_head->m_pkthdr.len > MHLEN) { 1464 MCLGET(m_new, M_DONTWAIT); 1465 if (!(m_new->m_flags & M_EXT)) { 1466 m_freem(m_new); 1467 printf("wb%d: no memory for tx list", 1468 sc->wb_unit); 1469 return(1); 1470 } 1471 } 1472 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1473 mtod(m_new, caddr_t)); 1474 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1475 m_freem(m_head); 1476 m_head = m_new; 1477 f = &c->wb_ptr->wb_frag[0]; 1478 f->wb_status = 0; 1479 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1480 f->wb_ctl = total_len = m_new->m_len; 1481 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1482 frag = 1; 1483 } 1484 1485 if (total_len < WB_MIN_FRAMELEN) { 1486 f = &c->wb_ptr->wb_frag[frag]; 1487 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1488 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1489 f->wb_ctl |= WB_TXCTL_TLINK; 1490 f->wb_status = WB_TXSTAT_OWN; 1491 frag++; 1492 } 1493 1494 c->wb_mbuf = m_head; 1495 c->wb_lastdesc = frag - 1; 1496 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1497 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1498 1499 return(0); 1500} 1501 1502/* 1503 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1504 * to the mbuf data regions directly in the transmit lists. We also save a 1505 * copy of the pointers since the transmit list fragment pointers are 1506 * physical addresses. 1507 */ 1508 1509static void wb_start(ifp) 1510 struct ifnet *ifp; 1511{ 1512 struct wb_softc *sc; 1513 struct mbuf *m_head = NULL; 1514 struct wb_chain *cur_tx = NULL, *start_tx; 1515 1516 sc = ifp->if_softc; 1517 WB_LOCK(sc); 1518 1519 /* 1520 * Check for an available queue slot. If there are none, 1521 * punt. 1522 */ 1523 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1524 ifp->if_flags |= IFF_OACTIVE; 1525 WB_UNLOCK(sc); 1526 return; 1527 } 1528 1529 start_tx = sc->wb_cdata.wb_tx_free; 1530 1531 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1532 IF_DEQUEUE(&ifp->if_snd, m_head); 1533 if (m_head == NULL) 1534 break; 1535 1536 /* Pick a descriptor off the free list. */ 1537 cur_tx = sc->wb_cdata.wb_tx_free; 1538 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1539 1540 /* Pack the data into the descriptor. */ 1541 wb_encap(sc, cur_tx, m_head); 1542 1543 if (cur_tx != start_tx) 1544 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1545 1546 /* 1547 * If there's a BPF listener, bounce a copy of this frame 1548 * to him. 1549 */ 1550 if (ifp->if_bpf) 1551 bpf_mtap(ifp, cur_tx->wb_mbuf); 1552 } 1553 1554 /* 1555 * If there are no packets queued, bail. 1556 */ 1557 if (cur_tx == NULL) { 1558 WB_UNLOCK(sc); 1559 return; 1560 } 1561 1562 /* 1563 * Place the request for the upload interrupt 1564 * in the last descriptor in the chain. This way, if 1565 * we're chaining several packets at once, we'll only 1566 * get an interupt once for the whole chain rather than 1567 * once for each packet. 1568 */ 1569 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1570 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1571 sc->wb_cdata.wb_tx_tail = cur_tx; 1572 1573 if (sc->wb_cdata.wb_tx_head == NULL) { 1574 sc->wb_cdata.wb_tx_head = start_tx; 1575 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1576 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1577 } else { 1578 /* 1579 * We need to distinguish between the case where 1580 * the own bit is clear because the chip cleared it 1581 * and where the own bit is clear because we haven't 1582 * set it yet. The magic value WB_UNSET is just some 1583 * ramdomly chosen number which doesn't have the own 1584 * bit set. When we actually transmit the frame, the 1585 * status word will have _only_ the own bit set, so 1586 * the txeoc handler will be able to tell if it needs 1587 * to initiate another transmission to flush out pending 1588 * frames. 1589 */ 1590 WB_TXOWN(start_tx) = WB_UNSENT; 1591 } 1592 1593 /* 1594 * Set a timeout in case the chip goes out to lunch. 1595 */ 1596 ifp->if_timer = 5; 1597 WB_UNLOCK(sc); 1598 1599 return; 1600} 1601 1602static void wb_init(xsc) 1603 void *xsc; 1604{ 1605 struct wb_softc *sc = xsc; 1606 struct ifnet *ifp = &sc->arpcom.ac_if; 1607 int i; 1608 struct mii_data *mii; 1609 1610 WB_LOCK(sc); 1611 mii = device_get_softc(sc->wb_miibus); 1612 1613 /* 1614 * Cancel pending I/O and free all RX/TX buffers. 1615 */ 1616 wb_stop(sc); 1617 wb_reset(sc); 1618 1619 sc->wb_txthresh = WB_TXTHRESH_INIT; 1620 1621 /* 1622 * Set cache alignment and burst length. 1623 */ 1624#ifdef foo 1625 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1626 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1627 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1628#endif 1629 1630 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1631 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1632 switch(sc->wb_cachesize) { 1633 case 32: 1634 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1635 break; 1636 case 16: 1637 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1638 break; 1639 case 8: 1640 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1641 break; 1642 case 0: 1643 default: 1644 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1645 break; 1646 } 1647 1648 /* This doesn't tend to work too well at 100Mbps. */ 1649 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1650 1651 /* Init our MAC address */ 1652 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1653 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1654 } 1655 1656 /* Init circular RX list. */ 1657 if (wb_list_rx_init(sc) == ENOBUFS) { 1658 printf("wb%d: initialization failed: no " 1659 "memory for rx buffers\n", sc->wb_unit); 1660 wb_stop(sc); 1661 WB_UNLOCK(sc); 1662 return; 1663 } 1664 1665 /* Init TX descriptors. */ 1666 wb_list_tx_init(sc); 1667 1668 /* If we want promiscuous mode, set the allframes bit. */ 1669 if (ifp->if_flags & IFF_PROMISC) { 1670 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1671 } else { 1672 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1673 } 1674 1675 /* 1676 * Set capture broadcast bit to capture broadcast frames. 1677 */ 1678 if (ifp->if_flags & IFF_BROADCAST) { 1679 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1680 } else { 1681 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1682 } 1683 1684 /* 1685 * Program the multicast filter, if necessary. 1686 */ 1687 wb_setmulti(sc); 1688 1689 /* 1690 * Load the address of the RX list. 1691 */ 1692 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1693 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1694 1695 /* 1696 * Enable interrupts. 1697 */ 1698 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1699 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1700 1701 /* Enable receiver and transmitter. */ 1702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1703 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1704 1705 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1706 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1707 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1708 1709 mii_mediachg(mii); 1710 1711 ifp->if_flags |= IFF_RUNNING; 1712 ifp->if_flags &= ~IFF_OACTIVE; 1713 1714 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1715 WB_UNLOCK(sc); 1716 1717 return; 1718} 1719 1720/* 1721 * Set media options. 1722 */ 1723static int wb_ifmedia_upd(ifp) 1724 struct ifnet *ifp; 1725{ 1726 struct wb_softc *sc; 1727 1728 sc = ifp->if_softc; 1729 1730 if (ifp->if_flags & IFF_UP) 1731 wb_init(sc); 1732 1733 return(0); 1734} 1735 1736/* 1737 * Report current media status. 1738 */ 1739static void wb_ifmedia_sts(ifp, ifmr) 1740 struct ifnet *ifp; 1741 struct ifmediareq *ifmr; 1742{ 1743 struct wb_softc *sc; 1744 struct mii_data *mii; 1745 1746 sc = ifp->if_softc; 1747 1748 mii = device_get_softc(sc->wb_miibus); 1749 1750 mii_pollstat(mii); 1751 ifmr->ifm_active = mii->mii_media_active; 1752 ifmr->ifm_status = mii->mii_media_status; 1753 1754 return; 1755} 1756 1757static int wb_ioctl(ifp, command, data) 1758 struct ifnet *ifp; 1759 u_long command; 1760 caddr_t data; 1761{ 1762 struct wb_softc *sc = ifp->if_softc; 1763 struct mii_data *mii; 1764 struct ifreq *ifr = (struct ifreq *) data; 1765 int error = 0; 1766 1767 WB_LOCK(sc); 1768 1769 switch(command) { 1770 case SIOCSIFADDR: 1771 case SIOCGIFADDR: 1772 case SIOCSIFMTU: 1773 error = ether_ioctl(ifp, command, data); 1774 break; 1775 case SIOCSIFFLAGS: 1776 if (ifp->if_flags & IFF_UP) { 1777 wb_init(sc); 1778 } else { 1779 if (ifp->if_flags & IFF_RUNNING) 1780 wb_stop(sc); 1781 } 1782 error = 0; 1783 break; 1784 case SIOCADDMULTI: 1785 case SIOCDELMULTI: 1786 wb_setmulti(sc); 1787 error = 0; 1788 break; 1789 case SIOCGIFMEDIA: 1790 case SIOCSIFMEDIA: 1791 mii = device_get_softc(sc->wb_miibus); 1792 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1793 break; 1794 default: 1795 error = EINVAL; 1796 break; 1797 } 1798 1799 WB_UNLOCK(sc); 1800 1801 return(error); 1802} 1803 1804static void wb_watchdog(ifp) 1805 struct ifnet *ifp; 1806{ 1807 struct wb_softc *sc; 1808 1809 sc = ifp->if_softc; 1810 1811 WB_LOCK(sc); 1812 ifp->if_oerrors++; 1813 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1814#ifdef foo 1815 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1816 printf("wb%d: no carrier - transceiver cable problem?\n", 1817 sc->wb_unit); 1818#endif 1819 wb_stop(sc); 1820 wb_reset(sc); 1821 wb_init(sc); 1822 1823 if (ifp->if_snd.ifq_head != NULL) 1824 wb_start(ifp); 1825 WB_UNLOCK(sc); 1826 1827 return; 1828} 1829 1830/* 1831 * Stop the adapter and free any mbufs allocated to the 1832 * RX and TX lists. 1833 */ 1834static void wb_stop(sc) 1835 struct wb_softc *sc; 1836{ 1837 register int i; 1838 struct ifnet *ifp; 1839 1840 WB_LOCK(sc); 1841 ifp = &sc->arpcom.ac_if; 1842 ifp->if_timer = 0; 1843 1844 untimeout(wb_tick, sc, sc->wb_stat_ch); 1845 1846 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1847 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1848 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1849 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1850 1851 /* 1852 * Free data in the RX lists. 1853 */ 1854 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1855 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1856 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1857 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1858 } 1859 } 1860 bzero((char *)&sc->wb_ldata->wb_rx_list, 1861 sizeof(sc->wb_ldata->wb_rx_list)); 1862 1863 /* 1864 * Free the TX list buffers. 1865 */ 1866 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1867 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1868 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1869 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1870 } 1871 } 1872 1873 bzero((char *)&sc->wb_ldata->wb_tx_list, 1874 sizeof(sc->wb_ldata->wb_tx_list)); 1875 1876 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1877 WB_UNLOCK(sc); 1878 1879 return; 1880} 1881 1882/* 1883 * Stop all chip I/O so that the kernel's probe routines don't 1884 * get confused by errant DMAs when rebooting. 1885 */ 1886static void wb_shutdown(dev) 1887 device_t dev; 1888{ 1889 struct wb_softc *sc; 1890 1891 sc = device_get_softc(dev); 1892 wb_stop(sc); 1893 1894 return; 1895} 1896