if_wb.c revision 64837
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul * 3250477Speter * $FreeBSD: head/sys/pci/if_wb.c 64837 2000-08-19 08:32:59Z dwmalone $ 3341502Swpaul */ 3441502Swpaul 3541502Swpaul/* 3641502Swpaul * Winbond fast ethernet PCI NIC driver 3741502Swpaul * 3841502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 3941502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4041502Swpaul * Winbond itself and some made by Linksys. 4141502Swpaul * 4241502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4341502Swpaul * Electrical Engineering Department 4441502Swpaul * Columbia University, New York City 4541502Swpaul */ 4641502Swpaul 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8648745Swpaul#include "opt_bdg.h" 8741502Swpaul 8841502Swpaul#include <sys/param.h> 8941502Swpaul#include <sys/systm.h> 9041502Swpaul#include <sys/sockio.h> 9141502Swpaul#include <sys/mbuf.h> 9241502Swpaul#include <sys/malloc.h> 9341502Swpaul#include <sys/kernel.h> 9441502Swpaul#include <sys/socket.h> 9550675Swpaul#include <sys/queue.h> 9641502Swpaul 9741502Swpaul#include <net/if.h> 9841502Swpaul#include <net/if_arp.h> 9941502Swpaul#include <net/ethernet.h> 10041502Swpaul#include <net/if_dl.h> 10141502Swpaul#include <net/if_media.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/clock.h> /* for DELAY */ 10841502Swpaul#include <machine/bus_memio.h> 10941502Swpaul#include <machine/bus_pio.h> 11041502Swpaul#include <machine/bus.h> 11149611Swpaul#include <machine/resource.h> 11249611Swpaul#include <sys/bus.h> 11349611Swpaul#include <sys/rman.h> 11441502Swpaul 11541502Swpaul#include <pci/pcireg.h> 11641502Swpaul#include <pci/pcivar.h> 11741502Swpaul 11850675Swpaul#include <dev/mii/mii.h> 11950675Swpaul#include <dev/mii/miivar.h> 12050675Swpaul 12151089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12250675Swpaul#include "miibus_if.h" 12350675Swpaul 12441502Swpaul#define WB_USEIOSPACE 12541502Swpaul 12641502Swpaul#include <pci/if_wbreg.h> 12741502Swpaul 12859758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 12959758Speter 13041502Swpaul#ifndef lint 13141633Sarchiestatic const char rcsid[] = 13250477Speter "$FreeBSD: head/sys/pci/if_wb.c 64837 2000-08-19 08:32:59Z dwmalone $"; 13341502Swpaul#endif 13441502Swpaul 13541502Swpaul/* 13641502Swpaul * Various supported device vendors/types and their names. 13741502Swpaul */ 13841502Swpaulstatic struct wb_type wb_devs[] = { 13941502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 14041502Swpaul "Winbond W89C840F 10/100BaseTX" }, 14141502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 14241502Swpaul "Compex RL100-ATX 10/100baseTX" }, 14341502Swpaul { 0, 0, NULL } 14441502Swpaul}; 14541502Swpaul 14649611Swpaulstatic int wb_probe __P((device_t)); 14749611Swpaulstatic int wb_attach __P((device_t)); 14849611Swpaulstatic int wb_detach __P((device_t)); 14941502Swpaul 15064837Sdwmalonestatic void wb_bfree __P((caddr_t, void *args)); 15141502Swpaulstatic int wb_newbuf __P((struct wb_softc *, 15248745Swpaul struct wb_chain_onefrag *, 15348745Swpaul struct mbuf *)); 15441502Swpaulstatic int wb_encap __P((struct wb_softc *, struct wb_chain *, 15550675Swpaul struct mbuf *)); 15641502Swpaul 15741502Swpaulstatic void wb_rxeof __P((struct wb_softc *)); 15841502Swpaulstatic void wb_rxeoc __P((struct wb_softc *)); 15941502Swpaulstatic void wb_txeof __P((struct wb_softc *)); 16041502Swpaulstatic void wb_txeoc __P((struct wb_softc *)); 16141502Swpaulstatic void wb_intr __P((void *)); 16250675Swpaulstatic void wb_tick __P((void *)); 16341502Swpaulstatic void wb_start __P((struct ifnet *)); 16441502Swpaulstatic int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 16541502Swpaulstatic void wb_init __P((void *)); 16641502Swpaulstatic void wb_stop __P((struct wb_softc *)); 16741502Swpaulstatic void wb_watchdog __P((struct ifnet *)); 16849611Swpaulstatic void wb_shutdown __P((device_t)); 16941502Swpaulstatic int wb_ifmedia_upd __P((struct ifnet *)); 17041502Swpaulstatic void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 17141502Swpaul 17242718Swpaulstatic void wb_eeprom_putbyte __P((struct wb_softc *, int)); 17342718Swpaulstatic void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 17441502Swpaulstatic void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 17541502Swpaul int, int)); 17641502Swpaulstatic void wb_mii_sync __P((struct wb_softc *)); 17741502Swpaulstatic void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 17841502Swpaulstatic int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 17941502Swpaulstatic int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 18041502Swpaul 18150675Swpaulstatic void wb_setcfg __P((struct wb_softc *, u_int32_t)); 18242718Swpaulstatic u_int8_t wb_calchash __P((caddr_t)); 18341502Swpaulstatic void wb_setmulti __P((struct wb_softc *)); 18441502Swpaulstatic void wb_reset __P((struct wb_softc *)); 18550675Swpaulstatic void wb_fixmedia __P((struct wb_softc *)); 18641502Swpaulstatic int wb_list_rx_init __P((struct wb_softc *)); 18741502Swpaulstatic int wb_list_tx_init __P((struct wb_softc *)); 18841502Swpaul 18950675Swpaulstatic int wb_miibus_readreg __P((device_t, int, int)); 19050675Swpaulstatic int wb_miibus_writereg __P((device_t, int, int, int)); 19150675Swpaulstatic void wb_miibus_statchg __P((device_t)); 19250675Swpaul 19349611Swpaul#ifdef WB_USEIOSPACE 19449611Swpaul#define WB_RES SYS_RES_IOPORT 19549611Swpaul#define WB_RID WB_PCI_LOIO 19649611Swpaul#else 19749611Swpaul#define WB_RES SYS_RES_MEMORY 19849611Swpaul#define WB_RID WB_PCI_LOMEM 19949611Swpaul#endif 20049611Swpaul 20149611Swpaulstatic device_method_t wb_methods[] = { 20249611Swpaul /* Device interface */ 20349611Swpaul DEVMETHOD(device_probe, wb_probe), 20449611Swpaul DEVMETHOD(device_attach, wb_attach), 20549611Swpaul DEVMETHOD(device_detach, wb_detach), 20649611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20750675Swpaul 20850675Swpaul /* bus interface, for miibus */ 20950675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 21050675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 21150675Swpaul 21250675Swpaul /* MII interface */ 21350675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 21450675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21550675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21649611Swpaul { 0, 0 } 21749611Swpaul}; 21849611Swpaul 21949611Swpaulstatic driver_t wb_driver = { 22051455Swpaul "wb", 22149611Swpaul wb_methods, 22249611Swpaul sizeof(struct wb_softc) 22349611Swpaul}; 22449611Swpaul 22549611Swpaulstatic devclass_t wb_devclass; 22649611Swpaul 22751533SwpaulDRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 22851473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22949611Swpaul 23041502Swpaul#define WB_SETBIT(sc, reg, x) \ 23141502Swpaul CSR_WRITE_4(sc, reg, \ 23241502Swpaul CSR_READ_4(sc, reg) | x) 23341502Swpaul 23441502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23541502Swpaul CSR_WRITE_4(sc, reg, \ 23641502Swpaul CSR_READ_4(sc, reg) & ~x) 23741502Swpaul 23841502Swpaul#define SIO_SET(x) \ 23941502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 24041502Swpaul CSR_READ_4(sc, WB_SIO) | x) 24141502Swpaul 24241502Swpaul#define SIO_CLR(x) \ 24341502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 24441502Swpaul CSR_READ_4(sc, WB_SIO) & ~x) 24541502Swpaul 24641502Swpaul/* 24741502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24841502Swpaul */ 24941502Swpaulstatic void wb_eeprom_putbyte(sc, addr) 25041502Swpaul struct wb_softc *sc; 25142718Swpaul int addr; 25241502Swpaul{ 25341502Swpaul register int d, i; 25441502Swpaul 25541502Swpaul d = addr | WB_EECMD_READ; 25641502Swpaul 25741502Swpaul /* 25841502Swpaul * Feed in each bit and stobe the clock. 25941502Swpaul */ 26041502Swpaul for (i = 0x400; i; i >>= 1) { 26141502Swpaul if (d & i) { 26241502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 26341502Swpaul } else { 26441502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26541502Swpaul } 26641502Swpaul DELAY(100); 26741502Swpaul SIO_SET(WB_SIO_EE_CLK); 26841502Swpaul DELAY(150); 26941502Swpaul SIO_CLR(WB_SIO_EE_CLK); 27041502Swpaul DELAY(100); 27141502Swpaul } 27241502Swpaul 27341502Swpaul return; 27441502Swpaul} 27541502Swpaul 27641502Swpaul/* 27741502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27841502Swpaul */ 27941502Swpaulstatic void wb_eeprom_getword(sc, addr, dest) 28041502Swpaul struct wb_softc *sc; 28142718Swpaul int addr; 28241502Swpaul u_int16_t *dest; 28341502Swpaul{ 28441502Swpaul register int i; 28541502Swpaul u_int16_t word = 0; 28641502Swpaul 28741502Swpaul /* Enter EEPROM access mode. */ 28841502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28941502Swpaul 29041502Swpaul /* 29141502Swpaul * Send address of word we want to read. 29241502Swpaul */ 29341502Swpaul wb_eeprom_putbyte(sc, addr); 29441502Swpaul 29541502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29641502Swpaul 29741502Swpaul /* 29841502Swpaul * Start reading bits from EEPROM. 29941502Swpaul */ 30041502Swpaul for (i = 0x8000; i; i >>= 1) { 30141502Swpaul SIO_SET(WB_SIO_EE_CLK); 30241502Swpaul DELAY(100); 30341502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30441502Swpaul word |= i; 30541502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30641502Swpaul DELAY(100); 30741502Swpaul } 30841502Swpaul 30941502Swpaul /* Turn off EEPROM access mode. */ 31041502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 31141502Swpaul 31241502Swpaul *dest = word; 31341502Swpaul 31441502Swpaul return; 31541502Swpaul} 31641502Swpaul 31741502Swpaul/* 31841502Swpaul * Read a sequence of words from the EEPROM. 31941502Swpaul */ 32041502Swpaulstatic void wb_read_eeprom(sc, dest, off, cnt, swap) 32141502Swpaul struct wb_softc *sc; 32241502Swpaul caddr_t dest; 32341502Swpaul int off; 32441502Swpaul int cnt; 32541502Swpaul int swap; 32641502Swpaul{ 32741502Swpaul int i; 32841502Swpaul u_int16_t word = 0, *ptr; 32941502Swpaul 33041502Swpaul for (i = 0; i < cnt; i++) { 33141502Swpaul wb_eeprom_getword(sc, off + i, &word); 33241502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33341502Swpaul if (swap) 33441502Swpaul *ptr = ntohs(word); 33541502Swpaul else 33641502Swpaul *ptr = word; 33741502Swpaul } 33841502Swpaul 33941502Swpaul return; 34041502Swpaul} 34141502Swpaul 34241502Swpaul/* 34341502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34441502Swpaul */ 34541502Swpaulstatic void wb_mii_sync(sc) 34641502Swpaul struct wb_softc *sc; 34741502Swpaul{ 34841502Swpaul register int i; 34941502Swpaul 35041502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35141502Swpaul 35241502Swpaul for (i = 0; i < 32; i++) { 35341502Swpaul SIO_SET(WB_SIO_MII_CLK); 35441502Swpaul DELAY(1); 35541502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35641502Swpaul DELAY(1); 35741502Swpaul } 35841502Swpaul 35941502Swpaul return; 36041502Swpaul} 36141502Swpaul 36241502Swpaul/* 36341502Swpaul * Clock a series of bits through the MII. 36441502Swpaul */ 36541502Swpaulstatic void wb_mii_send(sc, bits, cnt) 36641502Swpaul struct wb_softc *sc; 36741502Swpaul u_int32_t bits; 36841502Swpaul int cnt; 36941502Swpaul{ 37041502Swpaul int i; 37141502Swpaul 37241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37341502Swpaul 37441502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37541502Swpaul if (bits & i) { 37641502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37741502Swpaul } else { 37841502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37941502Swpaul } 38041502Swpaul DELAY(1); 38141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38241502Swpaul DELAY(1); 38341502Swpaul SIO_SET(WB_SIO_MII_CLK); 38441502Swpaul } 38541502Swpaul} 38641502Swpaul 38741502Swpaul/* 38841502Swpaul * Read an PHY register through the MII. 38941502Swpaul */ 39041502Swpaulstatic int wb_mii_readreg(sc, frame) 39141502Swpaul struct wb_softc *sc; 39241502Swpaul struct wb_mii_frame *frame; 39341502Swpaul 39441502Swpaul{ 39541502Swpaul int i, ack, s; 39641502Swpaul 39741502Swpaul s = splimp(); 39841502Swpaul 39941502Swpaul /* 40041502Swpaul * Set up frame for RX. 40141502Swpaul */ 40241502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40341502Swpaul frame->mii_opcode = WB_MII_READOP; 40441502Swpaul frame->mii_turnaround = 0; 40541502Swpaul frame->mii_data = 0; 40641502Swpaul 40741502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40841502Swpaul 40941502Swpaul /* 41041502Swpaul * Turn on data xmit. 41141502Swpaul */ 41241502Swpaul SIO_SET(WB_SIO_MII_DIR); 41341502Swpaul 41441502Swpaul wb_mii_sync(sc); 41541502Swpaul 41641502Swpaul /* 41741502Swpaul * Send command/address info. 41841502Swpaul */ 41941502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42041502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42141502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42241502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42341502Swpaul 42441502Swpaul /* Idle bit */ 42541502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42641502Swpaul DELAY(1); 42741502Swpaul SIO_SET(WB_SIO_MII_CLK); 42841502Swpaul DELAY(1); 42941502Swpaul 43041502Swpaul /* Turn off xmit. */ 43141502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43241502Swpaul /* Check for ack */ 43341502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43441502Swpaul DELAY(1); 43541502Swpaul SIO_SET(WB_SIO_MII_CLK); 43641502Swpaul DELAY(1); 43741502Swpaul ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43941502Swpaul DELAY(1); 44041502Swpaul SIO_SET(WB_SIO_MII_CLK); 44141502Swpaul DELAY(1); 44241502Swpaul 44341502Swpaul /* 44441502Swpaul * Now try reading data bits. If the ack failed, we still 44541502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44641502Swpaul */ 44741502Swpaul if (ack) { 44841502Swpaul for(i = 0; i < 16; i++) { 44941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45041502Swpaul DELAY(1); 45141502Swpaul SIO_SET(WB_SIO_MII_CLK); 45241502Swpaul DELAY(1); 45341502Swpaul } 45441502Swpaul goto fail; 45541502Swpaul } 45641502Swpaul 45741502Swpaul for (i = 0x8000; i; i >>= 1) { 45841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45941502Swpaul DELAY(1); 46041502Swpaul if (!ack) { 46141502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46241502Swpaul frame->mii_data |= i; 46341502Swpaul DELAY(1); 46441502Swpaul } 46541502Swpaul SIO_SET(WB_SIO_MII_CLK); 46641502Swpaul DELAY(1); 46741502Swpaul } 46841502Swpaul 46941502Swpaulfail: 47041502Swpaul 47141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47241502Swpaul DELAY(1); 47341502Swpaul SIO_SET(WB_SIO_MII_CLK); 47441502Swpaul DELAY(1); 47541502Swpaul 47641502Swpaul splx(s); 47741502Swpaul 47841502Swpaul if (ack) 47941502Swpaul return(1); 48041502Swpaul return(0); 48141502Swpaul} 48241502Swpaul 48341502Swpaul/* 48441502Swpaul * Write to a PHY register through the MII. 48541502Swpaul */ 48641502Swpaulstatic int wb_mii_writereg(sc, frame) 48741502Swpaul struct wb_softc *sc; 48841502Swpaul struct wb_mii_frame *frame; 48941502Swpaul 49041502Swpaul{ 49141502Swpaul int s; 49241502Swpaul 49341502Swpaul s = splimp(); 49441502Swpaul /* 49541502Swpaul * Set up frame for TX. 49641502Swpaul */ 49741502Swpaul 49841502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 49941502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50041502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50141502Swpaul 50241502Swpaul /* 50341502Swpaul * Turn on data output. 50441502Swpaul */ 50541502Swpaul SIO_SET(WB_SIO_MII_DIR); 50641502Swpaul 50741502Swpaul wb_mii_sync(sc); 50841502Swpaul 50941502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51041502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51141502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51241502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51341502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51441502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51541502Swpaul 51641502Swpaul /* Idle bit. */ 51741502Swpaul SIO_SET(WB_SIO_MII_CLK); 51841502Swpaul DELAY(1); 51941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52041502Swpaul DELAY(1); 52141502Swpaul 52241502Swpaul /* 52341502Swpaul * Turn off xmit. 52441502Swpaul */ 52541502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52641502Swpaul 52741502Swpaul splx(s); 52841502Swpaul 52941502Swpaul return(0); 53041502Swpaul} 53141502Swpaul 53250675Swpaulstatic int wb_miibus_readreg(dev, phy, reg) 53350675Swpaul device_t dev; 53450675Swpaul int phy, reg; 53550675Swpaul{ 53641502Swpaul struct wb_softc *sc; 53741502Swpaul struct wb_mii_frame frame; 53841502Swpaul 53950675Swpaul sc = device_get_softc(dev); 54050675Swpaul 54141502Swpaul bzero((char *)&frame, sizeof(frame)); 54241502Swpaul 54350675Swpaul frame.mii_phyaddr = phy; 54441502Swpaul frame.mii_regaddr = reg; 54541502Swpaul wb_mii_readreg(sc, &frame); 54641502Swpaul 54741502Swpaul return(frame.mii_data); 54841502Swpaul} 54941502Swpaul 55050675Swpaulstatic int wb_miibus_writereg(dev, phy, reg, data) 55150675Swpaul device_t dev; 55250675Swpaul int phy, reg, data; 55350675Swpaul{ 55441502Swpaul struct wb_softc *sc; 55541502Swpaul struct wb_mii_frame frame; 55641502Swpaul 55750675Swpaul sc = device_get_softc(dev); 55850675Swpaul 55941502Swpaul bzero((char *)&frame, sizeof(frame)); 56041502Swpaul 56150675Swpaul frame.mii_phyaddr = phy; 56241502Swpaul frame.mii_regaddr = reg; 56341502Swpaul frame.mii_data = data; 56441502Swpaul 56541502Swpaul wb_mii_writereg(sc, &frame); 56641502Swpaul 56750675Swpaul return(0); 56850675Swpaul} 56950675Swpaul 57050675Swpaulstatic void wb_miibus_statchg(dev) 57150675Swpaul device_t dev; 57250675Swpaul{ 57350675Swpaul struct wb_softc *sc; 57450675Swpaul struct mii_data *mii; 57550675Swpaul 57650675Swpaul sc = device_get_softc(dev); 57750675Swpaul mii = device_get_softc(sc->wb_miibus); 57850675Swpaul wb_setcfg(sc, mii->mii_media_active); 57950675Swpaul 58041502Swpaul return; 58141502Swpaul} 58241502Swpaul 58341502Swpaulstatic u_int8_t wb_calchash(addr) 58442718Swpaul caddr_t addr; 58541502Swpaul{ 58641502Swpaul u_int32_t crc, carry; 58741502Swpaul int i, j; 58841502Swpaul u_int8_t c; 58941502Swpaul 59041502Swpaul /* Compute CRC for the address value. */ 59141502Swpaul crc = 0xFFFFFFFF; /* initial value */ 59241502Swpaul 59341502Swpaul for (i = 0; i < 6; i++) { 59441502Swpaul c = *(addr + i); 59541502Swpaul for (j = 0; j < 8; j++) { 59641502Swpaul carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 59741502Swpaul crc <<= 1; 59841502Swpaul c >>= 1; 59941502Swpaul if (carry) 60041502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60141502Swpaul } 60241502Swpaul } 60341502Swpaul 60441502Swpaul /* 60541502Swpaul * return the filter bit position 60641502Swpaul * Note: I arrived at the following nonsense 60741502Swpaul * through experimentation. It's not the usual way to 60841502Swpaul * generate the bit position but it's the only thing 60941502Swpaul * I could come up with that works. 61041502Swpaul */ 61141502Swpaul return(~(crc >> 26) & 0x0000003F); 61241502Swpaul} 61341502Swpaul 61441502Swpaul/* 61541502Swpaul * Program the 64-bit multicast hash filter. 61641502Swpaul */ 61741502Swpaulstatic void wb_setmulti(sc) 61841502Swpaul struct wb_softc *sc; 61941502Swpaul{ 62041502Swpaul struct ifnet *ifp; 62141502Swpaul int h = 0; 62241502Swpaul u_int32_t hashes[2] = { 0, 0 }; 62341502Swpaul struct ifmultiaddr *ifma; 62441502Swpaul u_int32_t rxfilt; 62541502Swpaul int mcnt = 0; 62641502Swpaul 62741502Swpaul ifp = &sc->arpcom.ac_if; 62841502Swpaul 62941502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63041502Swpaul 63141502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 63241502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 63341502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 63441502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 63541502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 63641502Swpaul return; 63741502Swpaul } 63841502Swpaul 63941502Swpaul /* first, zot all the existing hash bits */ 64041502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64141502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 64241502Swpaul 64341502Swpaul /* now program new ones */ 64441502Swpaul for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 64541502Swpaul ifma = ifma->ifma_link.le_next) { 64641502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 64741502Swpaul continue; 64841502Swpaul h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 64941502Swpaul if (h < 32) 65041502Swpaul hashes[0] |= (1 << h); 65141502Swpaul else 65241502Swpaul hashes[1] |= (1 << (h - 32)); 65341502Swpaul mcnt++; 65441502Swpaul } 65541502Swpaul 65641502Swpaul if (mcnt) 65741502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 65841502Swpaul else 65941502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66041502Swpaul 66141502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66241502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 66341502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 66441502Swpaul 66541502Swpaul return; 66641502Swpaul} 66741502Swpaul 66841502Swpaul/* 66941502Swpaul * The Winbond manual states that in order to fiddle with the 67041502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67141502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67241502Swpaul */ 67350675Swpaulstatic void wb_setcfg(sc, media) 67441502Swpaul struct wb_softc *sc; 67550675Swpaul u_int32_t media; 67641502Swpaul{ 67741502Swpaul int i, restart = 0; 67841502Swpaul 67941502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 68041502Swpaul restart = 1; 68141502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 68241502Swpaul 68341502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 68441502Swpaul DELAY(10); 68541502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 68641502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 68741502Swpaul break; 68841502Swpaul } 68941502Swpaul 69041502Swpaul if (i == WB_TIMEOUT) 69141502Swpaul printf("wb%d: failed to force tx and " 69241502Swpaul "rx to idle state\n", sc->wb_unit); 69341502Swpaul } 69441502Swpaul 69550675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 69650675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 69750675Swpaul else 69841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 69941502Swpaul 70050675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70241502Swpaul else 70341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70441502Swpaul 70541502Swpaul if (restart) 70641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 70741502Swpaul 70841502Swpaul return; 70941502Swpaul} 71041502Swpaul 71141502Swpaulstatic void wb_reset(sc) 71241502Swpaul struct wb_softc *sc; 71341502Swpaul{ 71441502Swpaul register int i; 71550675Swpaul struct mii_data *mii; 71641502Swpaul 71750675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 71850675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 71950675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 72050675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 72150675Swpaul 72241502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 72350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 72441502Swpaul 72541502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 72641502Swpaul DELAY(10); 72741502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 72841502Swpaul break; 72941502Swpaul } 73041502Swpaul if (i == WB_TIMEOUT) 73141502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 73241502Swpaul 73341502Swpaul /* Wait a little while for the chip to get its brains in order. */ 73441502Swpaul DELAY(1000); 73541502Swpaul 73650675Swpaul if (sc->wb_miibus == NULL) 73750675Swpaul return; 73841502Swpaul 73950675Swpaul mii = device_get_softc(sc->wb_miibus); 74050675Swpaul if (mii == NULL) 74150675Swpaul return; 74250675Swpaul 74350675Swpaul if (mii->mii_instance) { 74450675Swpaul struct mii_softc *miisc; 74550675Swpaul for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 74650675Swpaul miisc = LIST_NEXT(miisc, mii_list)) 74750675Swpaul mii_phy_reset(miisc); 74850675Swpaul } 74950675Swpaul 75041502Swpaul return; 75141502Swpaul} 75241502Swpaul 75350675Swpaulstatic void wb_fixmedia(sc) 75450675Swpaul struct wb_softc *sc; 75550675Swpaul{ 75650675Swpaul struct mii_data *mii = NULL; 75750675Swpaul struct ifnet *ifp; 75850675Swpaul u_int32_t media; 75950675Swpaul 76050675Swpaul if (sc->wb_miibus == NULL) 76150675Swpaul return; 76250675Swpaul 76350675Swpaul mii = device_get_softc(sc->wb_miibus); 76450675Swpaul ifp = &sc->arpcom.ac_if; 76550675Swpaul 76650675Swpaul mii_pollstat(mii); 76750675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 76850675Swpaul media = mii->mii_media_active & ~IFM_10_T; 76950675Swpaul media |= IFM_100_TX; 77050675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 77150675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 77250675Swpaul media |= IFM_10_T; 77350675Swpaul } else 77450675Swpaul return; 77550675Swpaul 77650675Swpaul ifmedia_set(&mii->mii_media, media); 77750675Swpaul 77850675Swpaul return; 77950675Swpaul} 78050675Swpaul 78141502Swpaul/* 78241502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 78341502Swpaul * IDs against our list and return a device name if we find a match. 78441502Swpaul */ 78549611Swpaulstatic int wb_probe(dev) 78649611Swpaul device_t dev; 78741502Swpaul{ 78841502Swpaul struct wb_type *t; 78941502Swpaul 79041502Swpaul t = wb_devs; 79141502Swpaul 79241502Swpaul while(t->wb_name != NULL) { 79349611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 79449611Swpaul (pci_get_device(dev) == t->wb_did)) { 79549611Swpaul device_set_desc(dev, t->wb_name); 79649611Swpaul return(0); 79741502Swpaul } 79841502Swpaul t++; 79941502Swpaul } 80041502Swpaul 80149611Swpaul return(ENXIO); 80241502Swpaul} 80341502Swpaul 80441502Swpaul/* 80541502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 80641502Swpaul * setup and ethernet/BPF attach. 80741502Swpaul */ 80849611Swpaulstatic int wb_attach(dev) 80949611Swpaul device_t dev; 81041502Swpaul{ 81150675Swpaul int s; 81241502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 81341502Swpaul u_int32_t command; 81441502Swpaul struct wb_softc *sc; 81541502Swpaul struct ifnet *ifp; 81649611Swpaul int unit, error = 0, rid; 81741502Swpaul 81841502Swpaul s = splimp(); 81941502Swpaul 82049611Swpaul sc = device_get_softc(dev); 82149611Swpaul unit = device_get_unit(dev); 82241502Swpaul 82341502Swpaul /* 82441502Swpaul * Handle power management nonsense. 82541502Swpaul */ 82641502Swpaul 82749611Swpaul command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 82841502Swpaul if (command == 0x01) { 82941502Swpaul 83049611Swpaul command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 83141502Swpaul if (command & WB_PSTATE_MASK) { 83241502Swpaul u_int32_t iobase, membase, irq; 83341502Swpaul 83441502Swpaul /* Save important PCI config data. */ 83549611Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 83649611Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 83749611Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 83841502Swpaul 83941502Swpaul /* Reset the power state. */ 84041502Swpaul printf("wb%d: chip is in D%d power mode " 84141502Swpaul "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 84241502Swpaul command &= 0xFFFFFFFC; 84349611Swpaul pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 84441502Swpaul 84541502Swpaul /* Restore PCI config data. */ 84649611Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 84749611Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 84849611Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 84941502Swpaul } 85041502Swpaul } 85141502Swpaul 85241502Swpaul /* 85341502Swpaul * Map control/status registers. 85441502Swpaul */ 85561041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 85641502Swpaul command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 85761041Speter pci_write_config(dev, PCIR_COMMAND, command, 4); 85861041Speter command = pci_read_config(dev, PCIR_COMMAND, 4); 85941502Swpaul 86041502Swpaul#ifdef WB_USEIOSPACE 86141502Swpaul if (!(command & PCIM_CMD_PORTEN)) { 86241502Swpaul printf("wb%d: failed to enable I/O ports!\n", unit); 86349611Swpaul error = ENXIO; 86441502Swpaul goto fail; 86541502Swpaul } 86641502Swpaul#else 86741502Swpaul if (!(command & PCIM_CMD_MEMEN)) { 86841502Swpaul printf("wb%d: failed to enable memory mapping!\n", unit); 86949611Swpaul error = ENXIO; 87041502Swpaul goto fail; 87141502Swpaul } 87249611Swpaul#endif 87341502Swpaul 87449611Swpaul rid = WB_RID; 87549611Swpaul sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 87649611Swpaul 0, ~0, 1, RF_ACTIVE); 87749611Swpaul 87849611Swpaul if (sc->wb_res == NULL) { 87949611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 88049611Swpaul error = ENXIO; 88141502Swpaul goto fail; 88241502Swpaul } 88341502Swpaul 88449611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 88549611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 88649611Swpaul 88741502Swpaul /* Allocate interrupt */ 88849611Swpaul rid = 0; 88949611Swpaul sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 89049611Swpaul RF_SHAREABLE | RF_ACTIVE); 89149611Swpaul 89249611Swpaul if (sc->wb_irq == NULL) { 89341502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 89449611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 89549611Swpaul error = ENXIO; 89641502Swpaul goto fail; 89741502Swpaul } 89841502Swpaul 89949611Swpaul error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 90049611Swpaul wb_intr, sc, &sc->wb_intrhand); 90149611Swpaul 90249611Swpaul if (error) { 90349611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 90449611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 90549611Swpaul printf("wb%d: couldn't set up irq\n", unit); 90649611Swpaul goto fail; 90749611Swpaul } 90850675Swpaul 90950675Swpaul /* Save the cache line size. */ 91050675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 91150675Swpaul 91241502Swpaul /* Reset the adapter. */ 91341502Swpaul wb_reset(sc); 91441502Swpaul 91541502Swpaul /* 91641502Swpaul * Get station address from the EEPROM. 91741502Swpaul */ 91841502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 91941502Swpaul 92041502Swpaul /* 92141502Swpaul * A Winbond chip was detected. Inform the world. 92241502Swpaul */ 92341502Swpaul printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 92441502Swpaul 92541502Swpaul sc->wb_unit = unit; 92641502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 92741502Swpaul 92850675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 92951657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 93050675Swpaul 93150675Swpaul if (sc->wb_ldata == NULL) { 93241502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 93349611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 93449611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 93549611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 93649611Swpaul error = ENXIO; 93749611Swpaul goto fail; 93841502Swpaul } 93941502Swpaul 94041502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 94141502Swpaul 94241502Swpaul ifp = &sc->arpcom.ac_if; 94341502Swpaul ifp->if_softc = sc; 94441502Swpaul ifp->if_unit = unit; 94541502Swpaul ifp->if_name = "wb"; 94641502Swpaul ifp->if_mtu = ETHERMTU; 94741502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 94841502Swpaul ifp->if_ioctl = wb_ioctl; 94941502Swpaul ifp->if_output = ether_output; 95041502Swpaul ifp->if_start = wb_start; 95141502Swpaul ifp->if_watchdog = wb_watchdog; 95241502Swpaul ifp->if_init = wb_init; 95341502Swpaul ifp->if_baudrate = 10000000; 95443515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 95541502Swpaul 95650675Swpaul /* 95750675Swpaul * Do MII setup. 95850675Swpaul */ 95950675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 96050675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 96149611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 96249611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 96349611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 96449611Swpaul free(sc->wb_ldata_ptr, M_DEVBUF); 96549611Swpaul error = ENXIO; 96641502Swpaul goto fail; 96741502Swpaul } 96841502Swpaul 96941502Swpaul /* 97063090Sarchie * Call MI attach routine. 97141502Swpaul */ 97263090Sarchie ether_ifattach(ifp, ETHER_BPF_SUPPORTED); 97341502Swpaul 97441502Swpaulfail: 97550675Swpaul if (error) 97650675Swpaul device_delete_child(dev, sc->wb_miibus); 97741502Swpaul splx(s); 97850675Swpaul 97949611Swpaul return(error); 98041502Swpaul} 98141502Swpaul 98249611Swpaulstatic int wb_detach(dev) 98349611Swpaul device_t dev; 98449611Swpaul{ 98549611Swpaul struct wb_softc *sc; 98649611Swpaul struct ifnet *ifp; 98749611Swpaul int s; 98849611Swpaul 98949611Swpaul s = splimp(); 99049611Swpaul 99149611Swpaul sc = device_get_softc(dev); 99249611Swpaul ifp = &sc->arpcom.ac_if; 99349611Swpaul 99449611Swpaul wb_stop(sc); 99563090Sarchie ether_ifdetach(ifp, ETHER_BPF_SUPPORTED); 99649611Swpaul 99750675Swpaul /* Delete any miibus and phy devices attached to this interface */ 99850675Swpaul bus_generic_detach(dev); 99950675Swpaul device_delete_child(dev, sc->wb_miibus); 100050675Swpaul 100149611Swpaul bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 100249611Swpaul bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 100349611Swpaul bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 100449611Swpaul 100549611Swpaul free(sc->wb_ldata_ptr, M_DEVBUF); 100649611Swpaul 100749611Swpaul splx(s); 100849611Swpaul 100949611Swpaul return(0); 101049611Swpaul} 101149611Swpaul 101241502Swpaul/* 101341502Swpaul * Initialize the transmit descriptors. 101441502Swpaul */ 101541502Swpaulstatic int wb_list_tx_init(sc) 101641502Swpaul struct wb_softc *sc; 101741502Swpaul{ 101841502Swpaul struct wb_chain_data *cd; 101941502Swpaul struct wb_list_data *ld; 102041502Swpaul int i; 102141502Swpaul 102241502Swpaul cd = &sc->wb_cdata; 102341502Swpaul ld = sc->wb_ldata; 102441502Swpaul 102541502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 102641502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 102741502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 102841502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102941502Swpaul &cd->wb_tx_chain[0]; 103041502Swpaul } else { 103141502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 103241502Swpaul &cd->wb_tx_chain[i + 1]; 103341502Swpaul } 103441502Swpaul } 103541502Swpaul 103641502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 103741502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 103841502Swpaul 103941502Swpaul return(0); 104041502Swpaul} 104141502Swpaul 104241502Swpaul 104341502Swpaul/* 104441502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 104541502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 104641502Swpaul * points back to the first. 104741502Swpaul */ 104841502Swpaulstatic int wb_list_rx_init(sc) 104941502Swpaul struct wb_softc *sc; 105041502Swpaul{ 105141502Swpaul struct wb_chain_data *cd; 105241502Swpaul struct wb_list_data *ld; 105341502Swpaul int i; 105441502Swpaul 105541502Swpaul cd = &sc->wb_cdata; 105641502Swpaul ld = sc->wb_ldata; 105741502Swpaul 105841502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 105941502Swpaul cd->wb_rx_chain[i].wb_ptr = 106041502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 106150675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 106248745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 106341502Swpaul return(ENOBUFS); 106441502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 106541502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 106641502Swpaul ld->wb_rx_list[i].wb_next = 106741502Swpaul vtophys(&ld->wb_rx_list[0]); 106841502Swpaul } else { 106941502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 107041502Swpaul &cd->wb_rx_chain[i + 1]; 107141502Swpaul ld->wb_rx_list[i].wb_next = 107241502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 107341502Swpaul } 107441502Swpaul } 107541502Swpaul 107641502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 107741502Swpaul 107841502Swpaul return(0); 107941502Swpaul} 108041502Swpaul 108164837Sdwmalonestatic void wb_bfree(buf, args) 108250675Swpaul caddr_t buf; 108364837Sdwmalone void *args; 108450675Swpaul{ 108550675Swpaul return; 108650675Swpaul} 108750675Swpaul 108841502Swpaul/* 108941502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 109041502Swpaul */ 109148745Swpaulstatic int wb_newbuf(sc, c, m) 109241502Swpaul struct wb_softc *sc; 109341502Swpaul struct wb_chain_onefrag *c; 109448745Swpaul struct mbuf *m; 109541502Swpaul{ 109641502Swpaul struct mbuf *m_new = NULL; 109741502Swpaul 109848745Swpaul if (m == NULL) { 109948745Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 110048745Swpaul if (m_new == NULL) { 110148745Swpaul printf("wb%d: no memory for rx " 110248745Swpaul "list -- packet dropped!\n", sc->wb_unit); 110348745Swpaul return(ENOBUFS); 110448745Swpaul } 110564837Sdwmalone m_new->m_data = c->wb_buf; 110664837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 110764837Sdwmalone MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL); 110848745Swpaul } else { 110948745Swpaul m_new = m; 111050675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 111148745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 111241502Swpaul } 111341502Swpaul 111448745Swpaul m_adj(m_new, sizeof(u_int64_t)); 111548745Swpaul 111641502Swpaul c->wb_mbuf = m_new; 111741502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 111850675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 111941502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 112041502Swpaul 112141502Swpaul return(0); 112241502Swpaul} 112341502Swpaul 112441502Swpaul/* 112541502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 112641502Swpaul * the higher level protocols. 112741502Swpaul */ 112841502Swpaulstatic void wb_rxeof(sc) 112941502Swpaul struct wb_softc *sc; 113041502Swpaul{ 113141502Swpaul struct ether_header *eh; 113250675Swpaul struct mbuf *m = NULL; 113341502Swpaul struct ifnet *ifp; 113441502Swpaul struct wb_chain_onefrag *cur_rx; 113541502Swpaul int total_len = 0; 113641502Swpaul u_int32_t rxstat; 113741502Swpaul 113841502Swpaul ifp = &sc->arpcom.ac_if; 113941502Swpaul 114041502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 114141502Swpaul WB_RXSTAT_OWN)) { 114248745Swpaul struct mbuf *m0 = NULL; 114348745Swpaul 114441502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 114541502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 114650675Swpaul 114748745Swpaul m = cur_rx->wb_mbuf; 114841502Swpaul 114950675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 115050675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 115150675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 115250675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 115350675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 115441502Swpaul ifp->if_ierrors++; 115550675Swpaul wb_newbuf(sc, cur_rx, m); 115641502Swpaul printf("wb%x: receiver babbling: possible chip " 115741502Swpaul "bug, forcing reset\n", sc->wb_unit); 115850675Swpaul wb_fixmedia(sc); 115950675Swpaul wb_reset(sc); 116050675Swpaul wb_init(sc); 116141502Swpaul return; 116241502Swpaul } 116341502Swpaul 116442718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 116542718Swpaul ifp->if_ierrors++; 116648745Swpaul wb_newbuf(sc, cur_rx, m); 116750675Swpaul break; 116842718Swpaul } 116942718Swpaul 117041502Swpaul /* No errors; receive the packet. */ 117141502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 117241502Swpaul 117341502Swpaul /* 117441934Swpaul * XXX The Winbond chip includes the CRC with every 117541934Swpaul * received frame, and there's no way to turn this 117641934Swpaul * behavior off (at least, I can't find anything in 117741934Swpaul * the manual that explains how to do it) so we have 117841934Swpaul * to trim off the CRC manually. 117941934Swpaul */ 118041934Swpaul total_len -= ETHER_CRC_LEN; 118141934Swpaul 118248745Swpaul m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 118348745Swpaul total_len + ETHER_ALIGN, 0, ifp, NULL); 118448745Swpaul wb_newbuf(sc, cur_rx, m); 118548745Swpaul if (m0 == NULL) { 118648745Swpaul ifp->if_ierrors++; 118750675Swpaul break; 118841502Swpaul } 118948745Swpaul m_adj(m0, ETHER_ALIGN); 119048745Swpaul m = m0; 119141502Swpaul 119241502Swpaul ifp->if_ipackets++; 119341502Swpaul eh = mtod(m, struct ether_header *); 119441502Swpaul 119541502Swpaul /* Remove header from mbuf and pass it on. */ 119641502Swpaul m_adj(m, sizeof(struct ether_header)); 119741502Swpaul ether_input(ifp, eh, m); 119841502Swpaul } 119941502Swpaul} 120041502Swpaul 120141502Swpaulvoid wb_rxeoc(sc) 120241502Swpaul struct wb_softc *sc; 120341502Swpaul{ 120441502Swpaul wb_rxeof(sc); 120541502Swpaul 120641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120741502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 120841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 120941502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 121041502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 121141502Swpaul 121241502Swpaul return; 121341502Swpaul} 121441502Swpaul 121541502Swpaul/* 121641502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 121741502Swpaul * the list buffers. 121841502Swpaul */ 121941502Swpaulstatic void wb_txeof(sc) 122041502Swpaul struct wb_softc *sc; 122141502Swpaul{ 122241502Swpaul struct wb_chain *cur_tx; 122341502Swpaul struct ifnet *ifp; 122441502Swpaul 122541502Swpaul ifp = &sc->arpcom.ac_if; 122641502Swpaul 122741502Swpaul /* Clear the timeout timer. */ 122841502Swpaul ifp->if_timer = 0; 122941502Swpaul 123041502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 123141502Swpaul return; 123241502Swpaul 123341502Swpaul /* 123441502Swpaul * Go through our tx list and free mbufs for those 123541502Swpaul * frames that have been transmitted. 123641502Swpaul */ 123741502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 123841502Swpaul u_int32_t txstat; 123941502Swpaul 124041502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 124141502Swpaul txstat = WB_TXSTATUS(cur_tx); 124241502Swpaul 124341502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 124441502Swpaul break; 124541502Swpaul 124641502Swpaul if (txstat & WB_TXSTAT_TXERR) { 124741502Swpaul ifp->if_oerrors++; 124841502Swpaul if (txstat & WB_TXSTAT_ABORT) 124941502Swpaul ifp->if_collisions++; 125041502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 125141502Swpaul ifp->if_collisions++; 125241502Swpaul } 125341502Swpaul 125441502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 125541502Swpaul 125641502Swpaul ifp->if_opackets++; 125741502Swpaul m_freem(cur_tx->wb_mbuf); 125841502Swpaul cur_tx->wb_mbuf = NULL; 125941502Swpaul 126041502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 126141502Swpaul sc->wb_cdata.wb_tx_head = NULL; 126241502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 126341502Swpaul break; 126441502Swpaul } 126541502Swpaul 126641502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 126741502Swpaul } 126841502Swpaul 126941502Swpaul return; 127041502Swpaul} 127141502Swpaul 127241502Swpaul/* 127341502Swpaul * TX 'end of channel' interrupt handler. 127441502Swpaul */ 127541502Swpaulstatic void wb_txeoc(sc) 127641502Swpaul struct wb_softc *sc; 127741502Swpaul{ 127841502Swpaul struct ifnet *ifp; 127941502Swpaul 128041502Swpaul ifp = &sc->arpcom.ac_if; 128141502Swpaul 128241502Swpaul ifp->if_timer = 0; 128341502Swpaul 128441502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 128541502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 128641502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 128741502Swpaul } else { 128841502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 128941502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 129041502Swpaul ifp->if_timer = 5; 129141502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 129241502Swpaul } 129341502Swpaul } 129441502Swpaul 129541502Swpaul return; 129641502Swpaul} 129741502Swpaul 129841502Swpaulstatic void wb_intr(arg) 129941502Swpaul void *arg; 130041502Swpaul{ 130141502Swpaul struct wb_softc *sc; 130241502Swpaul struct ifnet *ifp; 130341502Swpaul u_int32_t status; 130441502Swpaul 130541502Swpaul sc = arg; 130641502Swpaul ifp = &sc->arpcom.ac_if; 130741502Swpaul 130841502Swpaul if (!(ifp->if_flags & IFF_UP)) 130941502Swpaul return; 131041502Swpaul 131141502Swpaul /* Disable interrupts. */ 131241502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 131341502Swpaul 131441502Swpaul for (;;) { 131541502Swpaul 131641502Swpaul status = CSR_READ_4(sc, WB_ISR); 131741502Swpaul if (status) 131841502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 131941502Swpaul 132041502Swpaul if ((status & WB_INTRS) == 0) 132141502Swpaul break; 132241502Swpaul 132341502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 132441502Swpaul ifp->if_ierrors++; 132541502Swpaul wb_reset(sc); 132650675Swpaul if (status & WB_ISR_RX_ERR) 132750675Swpaul wb_fixmedia(sc); 132841502Swpaul wb_init(sc); 132950675Swpaul continue; 133041502Swpaul } 133141502Swpaul 133250675Swpaul if (status & WB_ISR_RX_OK) 133350675Swpaul wb_rxeof(sc); 133450675Swpaul 133550675Swpaul if (status & WB_ISR_RX_IDLE) 133650675Swpaul wb_rxeoc(sc); 133750675Swpaul 133841502Swpaul if (status & WB_ISR_TX_OK) 133941502Swpaul wb_txeof(sc); 134041502Swpaul 134141502Swpaul if (status & WB_ISR_TX_NOBUF) 134241502Swpaul wb_txeoc(sc); 134341502Swpaul 134441502Swpaul if (status & WB_ISR_TX_IDLE) { 134541502Swpaul wb_txeof(sc); 134641502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 134741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 134841502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 134941502Swpaul } 135041502Swpaul } 135141502Swpaul 135241502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 135341502Swpaul ifp->if_oerrors++; 135441502Swpaul wb_txeof(sc); 135541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135641502Swpaul /* Jack up TX threshold */ 135741502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 135841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 135941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 136041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 136141502Swpaul } 136241502Swpaul 136341502Swpaul if (status & WB_ISR_BUS_ERR) { 136441502Swpaul wb_reset(sc); 136541502Swpaul wb_init(sc); 136641502Swpaul } 136741502Swpaul 136841502Swpaul } 136941502Swpaul 137041502Swpaul /* Re-enable interrupts. */ 137141502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 137241502Swpaul 137341502Swpaul if (ifp->if_snd.ifq_head != NULL) { 137441502Swpaul wb_start(ifp); 137541502Swpaul } 137641502Swpaul 137741502Swpaul return; 137841502Swpaul} 137941502Swpaul 138050675Swpaulstatic void wb_tick(xsc) 138150675Swpaul void *xsc; 138250675Swpaul{ 138350675Swpaul struct wb_softc *sc; 138450675Swpaul struct mii_data *mii; 138550685Swpaul int s; 138650675Swpaul 138750685Swpaul s = splimp(); 138850685Swpaul 138950675Swpaul sc = xsc; 139050675Swpaul mii = device_get_softc(sc->wb_miibus); 139150675Swpaul 139250675Swpaul mii_tick(mii); 139350675Swpaul 139450675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 139550675Swpaul 139650685Swpaul splx(s); 139750685Swpaul 139850675Swpaul return; 139950675Swpaul} 140050675Swpaul 140141502Swpaul/* 140241502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 140341502Swpaul * pointers to the fragment pointers. 140441502Swpaul */ 140541502Swpaulstatic int wb_encap(sc, c, m_head) 140641502Swpaul struct wb_softc *sc; 140741502Swpaul struct wb_chain *c; 140841502Swpaul struct mbuf *m_head; 140941502Swpaul{ 141041502Swpaul int frag = 0; 141141502Swpaul struct wb_desc *f = NULL; 141241502Swpaul int total_len; 141341502Swpaul struct mbuf *m; 141441502Swpaul 141541502Swpaul /* 141641502Swpaul * Start packing the mbufs in this chain into 141741502Swpaul * the fragment pointers. Stop when we run out 141841502Swpaul * of fragments or hit the end of the mbuf chain. 141941502Swpaul */ 142041502Swpaul m = m_head; 142141502Swpaul total_len = 0; 142241502Swpaul 142341502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 142441502Swpaul if (m->m_len != 0) { 142541502Swpaul if (frag == WB_MAXFRAGS) 142641502Swpaul break; 142741502Swpaul total_len += m->m_len; 142841502Swpaul f = &c->wb_ptr->wb_frag[frag]; 142941502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 143041502Swpaul if (frag == 0) { 143141502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 143241502Swpaul f->wb_status = 0; 143341502Swpaul } else 143441502Swpaul f->wb_status = WB_TXSTAT_OWN; 143541502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 143641502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 143741502Swpaul frag++; 143841502Swpaul } 143941502Swpaul } 144041502Swpaul 144141502Swpaul /* 144241502Swpaul * Handle special case: we used up all 16 fragments, 144341502Swpaul * but we have more mbufs left in the chain. Copy the 144441502Swpaul * data into an mbuf cluster. Note that we don't 144541502Swpaul * bother clearing the values in the other fragment 144641502Swpaul * pointers/counters; it wouldn't gain us anything, 144741502Swpaul * and would waste cycles. 144841502Swpaul */ 144941502Swpaul if (m != NULL) { 145041502Swpaul struct mbuf *m_new = NULL; 145141502Swpaul 145241502Swpaul MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145341502Swpaul if (m_new == NULL) { 145441502Swpaul printf("wb%d: no memory for tx list", sc->wb_unit); 145541502Swpaul return(1); 145641502Swpaul } 145741502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 145841502Swpaul MCLGET(m_new, M_DONTWAIT); 145941502Swpaul if (!(m_new->m_flags & M_EXT)) { 146041502Swpaul m_freem(m_new); 146141502Swpaul printf("wb%d: no memory for tx list", 146241502Swpaul sc->wb_unit); 146341502Swpaul return(1); 146441502Swpaul } 146541502Swpaul } 146641502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 146741502Swpaul mtod(m_new, caddr_t)); 146841502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 146941502Swpaul m_freem(m_head); 147041502Swpaul m_head = m_new; 147141502Swpaul f = &c->wb_ptr->wb_frag[0]; 147241502Swpaul f->wb_status = 0; 147341502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 147441502Swpaul f->wb_ctl = total_len = m_new->m_len; 147541502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 147641502Swpaul frag = 1; 147741502Swpaul } 147841502Swpaul 147941502Swpaul if (total_len < WB_MIN_FRAMELEN) { 148041502Swpaul f = &c->wb_ptr->wb_frag[frag]; 148141502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 148241502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 148341502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 148441502Swpaul f->wb_status = WB_TXSTAT_OWN; 148541502Swpaul frag++; 148641502Swpaul } 148741502Swpaul 148841502Swpaul c->wb_mbuf = m_head; 148941502Swpaul c->wb_lastdesc = frag - 1; 149041502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 149141502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 149241502Swpaul 149341502Swpaul return(0); 149441502Swpaul} 149541502Swpaul 149641502Swpaul/* 149741502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 149841502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 149941502Swpaul * copy of the pointers since the transmit list fragment pointers are 150041502Swpaul * physical addresses. 150141502Swpaul */ 150241502Swpaul 150341502Swpaulstatic void wb_start(ifp) 150441502Swpaul struct ifnet *ifp; 150541502Swpaul{ 150641502Swpaul struct wb_softc *sc; 150741502Swpaul struct mbuf *m_head = NULL; 150841502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 150941502Swpaul 151041502Swpaul sc = ifp->if_softc; 151141502Swpaul 151241502Swpaul /* 151341502Swpaul * Check for an available queue slot. If there are none, 151441502Swpaul * punt. 151541502Swpaul */ 151641502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 151741502Swpaul ifp->if_flags |= IFF_OACTIVE; 151841502Swpaul return; 151941502Swpaul } 152041502Swpaul 152141502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 152241502Swpaul 152341502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 152441502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 152541502Swpaul if (m_head == NULL) 152641502Swpaul break; 152741502Swpaul 152841502Swpaul /* Pick a descriptor off the free list. */ 152941502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 153041502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 153141502Swpaul 153241502Swpaul /* Pack the data into the descriptor. */ 153341502Swpaul wb_encap(sc, cur_tx, m_head); 153441502Swpaul 153541502Swpaul if (cur_tx != start_tx) 153641502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 153741502Swpaul 153841502Swpaul /* 153941502Swpaul * If there's a BPF listener, bounce a copy of this frame 154041502Swpaul * to him. 154141502Swpaul */ 154241502Swpaul if (ifp->if_bpf) 154341502Swpaul bpf_mtap(ifp, cur_tx->wb_mbuf); 154441502Swpaul } 154541502Swpaul 154641502Swpaul /* 154741526Swpaul * If there are no packets queued, bail. 154841526Swpaul */ 154941526Swpaul if (cur_tx == NULL) 155041526Swpaul return; 155141526Swpaul 155241526Swpaul /* 155341502Swpaul * Place the request for the upload interrupt 155441502Swpaul * in the last descriptor in the chain. This way, if 155541502Swpaul * we're chaining several packets at once, we'll only 155641502Swpaul * get an interupt once for the whole chain rather than 155741502Swpaul * once for each packet. 155841502Swpaul */ 155941502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 156042718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 156141502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 156241502Swpaul 156341502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 156441502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 156541502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 156641502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 156741502Swpaul } else { 156841502Swpaul /* 156941502Swpaul * We need to distinguish between the case where 157041502Swpaul * the own bit is clear because the chip cleared it 157141502Swpaul * and where the own bit is clear because we haven't 157241502Swpaul * set it yet. The magic value WB_UNSET is just some 157341502Swpaul * ramdomly chosen number which doesn't have the own 157441502Swpaul * bit set. When we actually transmit the frame, the 157541502Swpaul * status word will have _only_ the own bit set, so 157641502Swpaul * the txeoc handler will be able to tell if it needs 157741502Swpaul * to initiate another transmission to flush out pending 157841502Swpaul * frames. 157941502Swpaul */ 158041502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 158141502Swpaul } 158241502Swpaul 158341502Swpaul /* 158441502Swpaul * Set a timeout in case the chip goes out to lunch. 158541502Swpaul */ 158641502Swpaul ifp->if_timer = 5; 158741502Swpaul 158841502Swpaul return; 158941502Swpaul} 159041502Swpaul 159141502Swpaulstatic void wb_init(xsc) 159241502Swpaul void *xsc; 159341502Swpaul{ 159441502Swpaul struct wb_softc *sc = xsc; 159541502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 159641502Swpaul int s, i; 159750675Swpaul struct mii_data *mii; 159841502Swpaul 159941502Swpaul s = splimp(); 160041502Swpaul 160150675Swpaul mii = device_get_softc(sc->wb_miibus); 160241502Swpaul 160341502Swpaul /* 160441502Swpaul * Cancel pending I/O and free all RX/TX buffers. 160541502Swpaul */ 160641502Swpaul wb_stop(sc); 160741502Swpaul wb_reset(sc); 160841502Swpaul 160941502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 161041502Swpaul 161141502Swpaul /* 161241502Swpaul * Set cache alignment and burst length. 161341502Swpaul */ 161450675Swpaul#ifdef foo 161541502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 161641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 161741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 161850675Swpaul#endif 161941502Swpaul 162050675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 162150675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 162250675Swpaul switch(sc->wb_cachesize) { 162350675Swpaul case 32: 162450675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 162550675Swpaul break; 162650675Swpaul case 16: 162750675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 162850675Swpaul break; 162950675Swpaul case 8: 163050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 163150675Swpaul break; 163250675Swpaul case 0: 163350675Swpaul default: 163450675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 163550675Swpaul break; 163650675Swpaul } 163750675Swpaul 163841502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 163941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 164041502Swpaul 164141502Swpaul /* Init our MAC address */ 164241502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 164341502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 164441502Swpaul } 164541502Swpaul 164641502Swpaul /* Init circular RX list. */ 164741502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 164841502Swpaul printf("wb%d: initialization failed: no " 164941502Swpaul "memory for rx buffers\n", sc->wb_unit); 165041502Swpaul wb_stop(sc); 165141502Swpaul (void)splx(s); 165241502Swpaul return; 165341502Swpaul } 165441502Swpaul 165541502Swpaul /* Init TX descriptors. */ 165641502Swpaul wb_list_tx_init(sc); 165741502Swpaul 165841502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 165941502Swpaul if (ifp->if_flags & IFF_PROMISC) { 166041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166141502Swpaul } else { 166241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166341502Swpaul } 166441502Swpaul 166541502Swpaul /* 166641502Swpaul * Set capture broadcast bit to capture broadcast frames. 166741502Swpaul */ 166841502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 166941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167041502Swpaul } else { 167141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167241502Swpaul } 167341502Swpaul 167441502Swpaul /* 167541502Swpaul * Program the multicast filter, if necessary. 167641502Swpaul */ 167741502Swpaul wb_setmulti(sc); 167841502Swpaul 167941502Swpaul /* 168041502Swpaul * Load the address of the RX list. 168141502Swpaul */ 168241502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 168341502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 168441502Swpaul 168541502Swpaul /* 168641502Swpaul * Enable interrupts. 168741502Swpaul */ 168841502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 168941502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 169041502Swpaul 169141502Swpaul /* Enable receiver and transmitter. */ 169241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169341502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 169441502Swpaul 169541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 169641502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 169741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 169841502Swpaul 169950675Swpaul mii_mediachg(mii); 170041502Swpaul 170141502Swpaul ifp->if_flags |= IFF_RUNNING; 170241502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 170341502Swpaul 170441502Swpaul (void)splx(s); 170541502Swpaul 170650675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 170750675Swpaul 170841502Swpaul return; 170941502Swpaul} 171041502Swpaul 171141502Swpaul/* 171241502Swpaul * Set media options. 171341502Swpaul */ 171441502Swpaulstatic int wb_ifmedia_upd(ifp) 171541502Swpaul struct ifnet *ifp; 171641502Swpaul{ 171741502Swpaul struct wb_softc *sc; 171841502Swpaul 171941502Swpaul sc = ifp->if_softc; 172041502Swpaul 172150675Swpaul if (ifp->if_flags & IFF_UP) 172250675Swpaul wb_init(sc); 172341502Swpaul 172441502Swpaul return(0); 172541502Swpaul} 172641502Swpaul 172741502Swpaul/* 172841502Swpaul * Report current media status. 172941502Swpaul */ 173041502Swpaulstatic void wb_ifmedia_sts(ifp, ifmr) 173141502Swpaul struct ifnet *ifp; 173241502Swpaul struct ifmediareq *ifmr; 173341502Swpaul{ 173441502Swpaul struct wb_softc *sc; 173550675Swpaul struct mii_data *mii; 173641502Swpaul 173741502Swpaul sc = ifp->if_softc; 173841502Swpaul 173950675Swpaul mii = device_get_softc(sc->wb_miibus); 174041502Swpaul 174150675Swpaul mii_pollstat(mii); 174250675Swpaul ifmr->ifm_active = mii->mii_media_active; 174350675Swpaul ifmr->ifm_status = mii->mii_media_status; 174441502Swpaul 174541502Swpaul return; 174641502Swpaul} 174741502Swpaul 174841502Swpaulstatic int wb_ioctl(ifp, command, data) 174941502Swpaul struct ifnet *ifp; 175041502Swpaul u_long command; 175141502Swpaul caddr_t data; 175241502Swpaul{ 175341502Swpaul struct wb_softc *sc = ifp->if_softc; 175450675Swpaul struct mii_data *mii; 175541502Swpaul struct ifreq *ifr = (struct ifreq *) data; 175641502Swpaul int s, error = 0; 175741502Swpaul 175841502Swpaul s = splimp(); 175941502Swpaul 176041502Swpaul switch(command) { 176141502Swpaul case SIOCSIFADDR: 176241502Swpaul case SIOCGIFADDR: 176341502Swpaul case SIOCSIFMTU: 176441502Swpaul error = ether_ioctl(ifp, command, data); 176541502Swpaul break; 176641502Swpaul case SIOCSIFFLAGS: 176741502Swpaul if (ifp->if_flags & IFF_UP) { 176841502Swpaul wb_init(sc); 176941502Swpaul } else { 177041502Swpaul if (ifp->if_flags & IFF_RUNNING) 177141502Swpaul wb_stop(sc); 177241502Swpaul } 177341502Swpaul error = 0; 177441502Swpaul break; 177541502Swpaul case SIOCADDMULTI: 177641502Swpaul case SIOCDELMULTI: 177741502Swpaul wb_setmulti(sc); 177841502Swpaul error = 0; 177941502Swpaul break; 178041502Swpaul case SIOCGIFMEDIA: 178141502Swpaul case SIOCSIFMEDIA: 178250675Swpaul mii = device_get_softc(sc->wb_miibus); 178350675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 178441502Swpaul break; 178541502Swpaul default: 178641502Swpaul error = EINVAL; 178741502Swpaul break; 178841502Swpaul } 178941502Swpaul 179041502Swpaul (void)splx(s); 179141502Swpaul 179241502Swpaul return(error); 179341502Swpaul} 179441502Swpaul 179541502Swpaulstatic void wb_watchdog(ifp) 179641502Swpaul struct ifnet *ifp; 179741502Swpaul{ 179841502Swpaul struct wb_softc *sc; 179941502Swpaul 180041502Swpaul sc = ifp->if_softc; 180141502Swpaul 180241502Swpaul ifp->if_oerrors++; 180341502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 180450675Swpaul#ifdef foo 180541502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 180641502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 180741502Swpaul sc->wb_unit); 180850675Swpaul#endif 180941502Swpaul wb_stop(sc); 181041502Swpaul wb_reset(sc); 181141502Swpaul wb_init(sc); 181241502Swpaul 181341502Swpaul if (ifp->if_snd.ifq_head != NULL) 181441502Swpaul wb_start(ifp); 181541502Swpaul 181641502Swpaul return; 181741502Swpaul} 181841502Swpaul 181941502Swpaul/* 182041502Swpaul * Stop the adapter and free any mbufs allocated to the 182141502Swpaul * RX and TX lists. 182241502Swpaul */ 182341502Swpaulstatic void wb_stop(sc) 182441502Swpaul struct wb_softc *sc; 182541502Swpaul{ 182641502Swpaul register int i; 182741502Swpaul struct ifnet *ifp; 182841502Swpaul 182941502Swpaul ifp = &sc->arpcom.ac_if; 183041502Swpaul ifp->if_timer = 0; 183141502Swpaul 183250675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 183350675Swpaul 183441502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 183541502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 183641502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 183741502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 183841502Swpaul 183941502Swpaul /* 184041502Swpaul * Free data in the RX lists. 184141502Swpaul */ 184241502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 184341502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 184441502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 184541502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 184641502Swpaul } 184741502Swpaul } 184841502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 184941502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 185041502Swpaul 185141502Swpaul /* 185241502Swpaul * Free the TX list buffers. 185341502Swpaul */ 185441502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 185541502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 185641502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 185741502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 185841502Swpaul } 185941502Swpaul } 186041502Swpaul 186141502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 186241502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 186341502Swpaul 186441502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 186541502Swpaul 186641502Swpaul return; 186741502Swpaul} 186841502Swpaul 186941502Swpaul/* 187041502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 187141502Swpaul * get confused by errant DMAs when rebooting. 187241502Swpaul */ 187349611Swpaulstatic void wb_shutdown(dev) 187449611Swpaul device_t dev; 187541502Swpaul{ 187649611Swpaul struct wb_softc *sc; 187741502Swpaul 187849611Swpaul sc = device_get_softc(dev); 187941502Swpaul wb_stop(sc); 188041502Swpaul 188141502Swpaul return; 188241502Swpaul} 1883