if_wb.c revision 51657
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 51657 1999-09-25 17:29:02Z wpaul $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/kernel.h> 94#include <sys/socket.h> 95#include <sys/queue.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102 103#include <net/bpf.h> 104 105#ifdef BRIDGE 106#include <net/bridge.h> 107#endif 108 109#include <vm/vm.h> /* for vtophys */ 110#include <vm/pmap.h> /* for vtophys */ 111#include <machine/clock.h> /* for DELAY */ 112#include <machine/bus_memio.h> 113#include <machine/bus_pio.h> 114#include <machine/bus.h> 115#include <machine/resource.h> 116#include <sys/bus.h> 117#include <sys/rman.h> 118 119#include <pci/pcireg.h> 120#include <pci/pcivar.h> 121 122#include <dev/mii/mii.h> 123#include <dev/mii/miivar.h> 124 125/* "controller miibus0" required. See GENERIC if you get errors here. */ 126#include "miibus_if.h" 127 128#define WB_USEIOSPACE 129 130#include <pci/if_wbreg.h> 131 132#ifndef lint 133static const char rcsid[] = 134 "$FreeBSD: head/sys/pci/if_wb.c 51657 1999-09-25 17:29:02Z wpaul $"; 135#endif 136 137/* 138 * Various supported device vendors/types and their names. 139 */ 140static struct wb_type wb_devs[] = { 141 { WB_VENDORID, WB_DEVICEID_840F, 142 "Winbond W89C840F 10/100BaseTX" }, 143 { CP_VENDORID, CP_DEVICEID_RL100, 144 "Compex RL100-ATX 10/100baseTX" }, 145 { 0, 0, NULL } 146}; 147 148static int wb_probe __P((device_t)); 149static int wb_attach __P((device_t)); 150static int wb_detach __P((device_t)); 151 152static void wb_bfree __P((caddr_t, u_int)); 153static int wb_newbuf __P((struct wb_softc *, 154 struct wb_chain_onefrag *, 155 struct mbuf *)); 156static int wb_encap __P((struct wb_softc *, struct wb_chain *, 157 struct mbuf *)); 158 159static void wb_rxeof __P((struct wb_softc *)); 160static void wb_rxeoc __P((struct wb_softc *)); 161static void wb_txeof __P((struct wb_softc *)); 162static void wb_txeoc __P((struct wb_softc *)); 163static void wb_intr __P((void *)); 164static void wb_tick __P((void *)); 165static void wb_start __P((struct ifnet *)); 166static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 167static void wb_init __P((void *)); 168static void wb_stop __P((struct wb_softc *)); 169static void wb_watchdog __P((struct ifnet *)); 170static void wb_shutdown __P((device_t)); 171static int wb_ifmedia_upd __P((struct ifnet *)); 172static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 173 174static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 175static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 176static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 177 int, int)); 178static void wb_mii_sync __P((struct wb_softc *)); 179static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 180static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 181static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 182 183static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 184static u_int8_t wb_calchash __P((caddr_t)); 185static void wb_setmulti __P((struct wb_softc *)); 186static void wb_reset __P((struct wb_softc *)); 187static void wb_fixmedia __P((struct wb_softc *)); 188static int wb_list_rx_init __P((struct wb_softc *)); 189static int wb_list_tx_init __P((struct wb_softc *)); 190 191static int wb_miibus_readreg __P((device_t, int, int)); 192static int wb_miibus_writereg __P((device_t, int, int, int)); 193static void wb_miibus_statchg __P((device_t)); 194 195#ifdef WB_USEIOSPACE 196#define WB_RES SYS_RES_IOPORT 197#define WB_RID WB_PCI_LOIO 198#else 199#define WB_RES SYS_RES_MEMORY 200#define WB_RID WB_PCI_LOMEM 201#endif 202 203static device_method_t wb_methods[] = { 204 /* Device interface */ 205 DEVMETHOD(device_probe, wb_probe), 206 DEVMETHOD(device_attach, wb_attach), 207 DEVMETHOD(device_detach, wb_detach), 208 DEVMETHOD(device_shutdown, wb_shutdown), 209 210 /* bus interface, for miibus */ 211 DEVMETHOD(bus_print_child, bus_generic_print_child), 212 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 213 214 /* MII interface */ 215 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 216 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 217 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 218 { 0, 0 } 219}; 220 221static driver_t wb_driver = { 222 "wb", 223 wb_methods, 224 sizeof(struct wb_softc) 225}; 226 227static devclass_t wb_devclass; 228 229DRIVER_MODULE(if_wb, pci, wb_driver, wb_devclass, 0, 0); 230DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 231 232#define WB_SETBIT(sc, reg, x) \ 233 CSR_WRITE_4(sc, reg, \ 234 CSR_READ_4(sc, reg) | x) 235 236#define WB_CLRBIT(sc, reg, x) \ 237 CSR_WRITE_4(sc, reg, \ 238 CSR_READ_4(sc, reg) & ~x) 239 240#define SIO_SET(x) \ 241 CSR_WRITE_4(sc, WB_SIO, \ 242 CSR_READ_4(sc, WB_SIO) | x) 243 244#define SIO_CLR(x) \ 245 CSR_WRITE_4(sc, WB_SIO, \ 246 CSR_READ_4(sc, WB_SIO) & ~x) 247 248/* 249 * Send a read command and address to the EEPROM, check for ACK. 250 */ 251static void wb_eeprom_putbyte(sc, addr) 252 struct wb_softc *sc; 253 int addr; 254{ 255 register int d, i; 256 257 d = addr | WB_EECMD_READ; 258 259 /* 260 * Feed in each bit and stobe the clock. 261 */ 262 for (i = 0x400; i; i >>= 1) { 263 if (d & i) { 264 SIO_SET(WB_SIO_EE_DATAIN); 265 } else { 266 SIO_CLR(WB_SIO_EE_DATAIN); 267 } 268 DELAY(100); 269 SIO_SET(WB_SIO_EE_CLK); 270 DELAY(150); 271 SIO_CLR(WB_SIO_EE_CLK); 272 DELAY(100); 273 } 274 275 return; 276} 277 278/* 279 * Read a word of data stored in the EEPROM at address 'addr.' 280 */ 281static void wb_eeprom_getword(sc, addr, dest) 282 struct wb_softc *sc; 283 int addr; 284 u_int16_t *dest; 285{ 286 register int i; 287 u_int16_t word = 0; 288 289 /* Enter EEPROM access mode. */ 290 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 291 292 /* 293 * Send address of word we want to read. 294 */ 295 wb_eeprom_putbyte(sc, addr); 296 297 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 298 299 /* 300 * Start reading bits from EEPROM. 301 */ 302 for (i = 0x8000; i; i >>= 1) { 303 SIO_SET(WB_SIO_EE_CLK); 304 DELAY(100); 305 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 306 word |= i; 307 SIO_CLR(WB_SIO_EE_CLK); 308 DELAY(100); 309 } 310 311 /* Turn off EEPROM access mode. */ 312 CSR_WRITE_4(sc, WB_SIO, 0); 313 314 *dest = word; 315 316 return; 317} 318 319/* 320 * Read a sequence of words from the EEPROM. 321 */ 322static void wb_read_eeprom(sc, dest, off, cnt, swap) 323 struct wb_softc *sc; 324 caddr_t dest; 325 int off; 326 int cnt; 327 int swap; 328{ 329 int i; 330 u_int16_t word = 0, *ptr; 331 332 for (i = 0; i < cnt; i++) { 333 wb_eeprom_getword(sc, off + i, &word); 334 ptr = (u_int16_t *)(dest + (i * 2)); 335 if (swap) 336 *ptr = ntohs(word); 337 else 338 *ptr = word; 339 } 340 341 return; 342} 343 344/* 345 * Sync the PHYs by setting data bit and strobing the clock 32 times. 346 */ 347static void wb_mii_sync(sc) 348 struct wb_softc *sc; 349{ 350 register int i; 351 352 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 353 354 for (i = 0; i < 32; i++) { 355 SIO_SET(WB_SIO_MII_CLK); 356 DELAY(1); 357 SIO_CLR(WB_SIO_MII_CLK); 358 DELAY(1); 359 } 360 361 return; 362} 363 364/* 365 * Clock a series of bits through the MII. 366 */ 367static void wb_mii_send(sc, bits, cnt) 368 struct wb_softc *sc; 369 u_int32_t bits; 370 int cnt; 371{ 372 int i; 373 374 SIO_CLR(WB_SIO_MII_CLK); 375 376 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 377 if (bits & i) { 378 SIO_SET(WB_SIO_MII_DATAIN); 379 } else { 380 SIO_CLR(WB_SIO_MII_DATAIN); 381 } 382 DELAY(1); 383 SIO_CLR(WB_SIO_MII_CLK); 384 DELAY(1); 385 SIO_SET(WB_SIO_MII_CLK); 386 } 387} 388 389/* 390 * Read an PHY register through the MII. 391 */ 392static int wb_mii_readreg(sc, frame) 393 struct wb_softc *sc; 394 struct wb_mii_frame *frame; 395 396{ 397 int i, ack, s; 398 399 s = splimp(); 400 401 /* 402 * Set up frame for RX. 403 */ 404 frame->mii_stdelim = WB_MII_STARTDELIM; 405 frame->mii_opcode = WB_MII_READOP; 406 frame->mii_turnaround = 0; 407 frame->mii_data = 0; 408 409 CSR_WRITE_4(sc, WB_SIO, 0); 410 411 /* 412 * Turn on data xmit. 413 */ 414 SIO_SET(WB_SIO_MII_DIR); 415 416 wb_mii_sync(sc); 417 418 /* 419 * Send command/address info. 420 */ 421 wb_mii_send(sc, frame->mii_stdelim, 2); 422 wb_mii_send(sc, frame->mii_opcode, 2); 423 wb_mii_send(sc, frame->mii_phyaddr, 5); 424 wb_mii_send(sc, frame->mii_regaddr, 5); 425 426 /* Idle bit */ 427 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 428 DELAY(1); 429 SIO_SET(WB_SIO_MII_CLK); 430 DELAY(1); 431 432 /* Turn off xmit. */ 433 SIO_CLR(WB_SIO_MII_DIR); 434 /* Check for ack */ 435 SIO_CLR(WB_SIO_MII_CLK); 436 DELAY(1); 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 440 SIO_CLR(WB_SIO_MII_CLK); 441 DELAY(1); 442 SIO_SET(WB_SIO_MII_CLK); 443 DELAY(1); 444 445 /* 446 * Now try reading data bits. If the ack failed, we still 447 * need to clock through 16 cycles to keep the PHY(s) in sync. 448 */ 449 if (ack) { 450 for(i = 0; i < 16; i++) { 451 SIO_CLR(WB_SIO_MII_CLK); 452 DELAY(1); 453 SIO_SET(WB_SIO_MII_CLK); 454 DELAY(1); 455 } 456 goto fail; 457 } 458 459 for (i = 0x8000; i; i >>= 1) { 460 SIO_CLR(WB_SIO_MII_CLK); 461 DELAY(1); 462 if (!ack) { 463 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 464 frame->mii_data |= i; 465 DELAY(1); 466 } 467 SIO_SET(WB_SIO_MII_CLK); 468 DELAY(1); 469 } 470 471fail: 472 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 SIO_SET(WB_SIO_MII_CLK); 476 DELAY(1); 477 478 splx(s); 479 480 if (ack) 481 return(1); 482 return(0); 483} 484 485/* 486 * Write to a PHY register through the MII. 487 */ 488static int wb_mii_writereg(sc, frame) 489 struct wb_softc *sc; 490 struct wb_mii_frame *frame; 491 492{ 493 int s; 494 495 s = splimp(); 496 /* 497 * Set up frame for TX. 498 */ 499 500 frame->mii_stdelim = WB_MII_STARTDELIM; 501 frame->mii_opcode = WB_MII_WRITEOP; 502 frame->mii_turnaround = WB_MII_TURNAROUND; 503 504 /* 505 * Turn on data output. 506 */ 507 SIO_SET(WB_SIO_MII_DIR); 508 509 wb_mii_sync(sc); 510 511 wb_mii_send(sc, frame->mii_stdelim, 2); 512 wb_mii_send(sc, frame->mii_opcode, 2); 513 wb_mii_send(sc, frame->mii_phyaddr, 5); 514 wb_mii_send(sc, frame->mii_regaddr, 5); 515 wb_mii_send(sc, frame->mii_turnaround, 2); 516 wb_mii_send(sc, frame->mii_data, 16); 517 518 /* Idle bit. */ 519 SIO_SET(WB_SIO_MII_CLK); 520 DELAY(1); 521 SIO_CLR(WB_SIO_MII_CLK); 522 DELAY(1); 523 524 /* 525 * Turn off xmit. 526 */ 527 SIO_CLR(WB_SIO_MII_DIR); 528 529 splx(s); 530 531 return(0); 532} 533 534static int wb_miibus_readreg(dev, phy, reg) 535 device_t dev; 536 int phy, reg; 537{ 538 struct wb_softc *sc; 539 struct wb_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 wb_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550} 551 552static int wb_miibus_writereg(dev, phy, reg, data) 553 device_t dev; 554 int phy, reg, data; 555{ 556 struct wb_softc *sc; 557 struct wb_mii_frame frame; 558 559 sc = device_get_softc(dev); 560 561 bzero((char *)&frame, sizeof(frame)); 562 563 frame.mii_phyaddr = phy; 564 frame.mii_regaddr = reg; 565 frame.mii_data = data; 566 567 wb_mii_writereg(sc, &frame); 568 569 return(0); 570} 571 572static void wb_miibus_statchg(dev) 573 device_t dev; 574{ 575 struct wb_softc *sc; 576 struct mii_data *mii; 577 578 sc = device_get_softc(dev); 579 mii = device_get_softc(sc->wb_miibus); 580 wb_setcfg(sc, mii->mii_media_active); 581 582 return; 583} 584 585static u_int8_t wb_calchash(addr) 586 caddr_t addr; 587{ 588 u_int32_t crc, carry; 589 int i, j; 590 u_int8_t c; 591 592 /* Compute CRC for the address value. */ 593 crc = 0xFFFFFFFF; /* initial value */ 594 595 for (i = 0; i < 6; i++) { 596 c = *(addr + i); 597 for (j = 0; j < 8; j++) { 598 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 599 crc <<= 1; 600 c >>= 1; 601 if (carry) 602 crc = (crc ^ 0x04c11db6) | carry; 603 } 604 } 605 606 /* 607 * return the filter bit position 608 * Note: I arrived at the following nonsense 609 * through experimentation. It's not the usual way to 610 * generate the bit position but it's the only thing 611 * I could come up with that works. 612 */ 613 return(~(crc >> 26) & 0x0000003F); 614} 615 616/* 617 * Program the 64-bit multicast hash filter. 618 */ 619static void wb_setmulti(sc) 620 struct wb_softc *sc; 621{ 622 struct ifnet *ifp; 623 int h = 0; 624 u_int32_t hashes[2] = { 0, 0 }; 625 struct ifmultiaddr *ifma; 626 u_int32_t rxfilt; 627 int mcnt = 0; 628 629 ifp = &sc->arpcom.ac_if; 630 631 rxfilt = CSR_READ_4(sc, WB_NETCFG); 632 633 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 634 rxfilt |= WB_NETCFG_RX_MULTI; 635 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 636 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 637 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 638 return; 639 } 640 641 /* first, zot all the existing hash bits */ 642 CSR_WRITE_4(sc, WB_MAR0, 0); 643 CSR_WRITE_4(sc, WB_MAR1, 0); 644 645 /* now program new ones */ 646 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 647 ifma = ifma->ifma_link.le_next) { 648 if (ifma->ifma_addr->sa_family != AF_LINK) 649 continue; 650 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 651 if (h < 32) 652 hashes[0] |= (1 << h); 653 else 654 hashes[1] |= (1 << (h - 32)); 655 mcnt++; 656 } 657 658 if (mcnt) 659 rxfilt |= WB_NETCFG_RX_MULTI; 660 else 661 rxfilt &= ~WB_NETCFG_RX_MULTI; 662 663 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 664 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 665 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 666 667 return; 668} 669 670/* 671 * The Winbond manual states that in order to fiddle with the 672 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 673 * first have to put the transmit and/or receive logic in the idle state. 674 */ 675static void wb_setcfg(sc, media) 676 struct wb_softc *sc; 677 u_int32_t media; 678{ 679 int i, restart = 0; 680 681 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 682 restart = 1; 683 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 684 685 for (i = 0; i < WB_TIMEOUT; i++) { 686 DELAY(10); 687 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 688 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 689 break; 690 } 691 692 if (i == WB_TIMEOUT) 693 printf("wb%d: failed to force tx and " 694 "rx to idle state\n", sc->wb_unit); 695 } 696 697 if (IFM_SUBTYPE(media) == IFM_10_T) 698 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 699 else 700 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 701 702 if ((media & IFM_GMASK) == IFM_FDX) 703 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 704 else 705 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 706 707 if (restart) 708 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 709 710 return; 711} 712 713static void wb_reset(sc) 714 struct wb_softc *sc; 715{ 716 register int i; 717 struct mii_data *mii; 718 719 CSR_WRITE_4(sc, WB_NETCFG, 0); 720 CSR_WRITE_4(sc, WB_BUSCTL, 0); 721 CSR_WRITE_4(sc, WB_TXADDR, 0); 722 CSR_WRITE_4(sc, WB_RXADDR, 0); 723 724 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 725 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 726 727 for (i = 0; i < WB_TIMEOUT; i++) { 728 DELAY(10); 729 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 730 break; 731 } 732 if (i == WB_TIMEOUT) 733 printf("wb%d: reset never completed!\n", sc->wb_unit); 734 735 /* Wait a little while for the chip to get its brains in order. */ 736 DELAY(1000); 737 738 if (sc->wb_miibus == NULL) 739 return; 740 741 mii = device_get_softc(sc->wb_miibus); 742 if (mii == NULL) 743 return; 744 745 if (mii->mii_instance) { 746 struct mii_softc *miisc; 747 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 748 miisc = LIST_NEXT(miisc, mii_list)) 749 mii_phy_reset(miisc); 750 } 751 752 return; 753} 754 755static void wb_fixmedia(sc) 756 struct wb_softc *sc; 757{ 758 struct mii_data *mii = NULL; 759 struct ifnet *ifp; 760 u_int32_t media; 761 762 if (sc->wb_miibus == NULL) 763 return; 764 765 mii = device_get_softc(sc->wb_miibus); 766 ifp = &sc->arpcom.ac_if; 767 768 mii_pollstat(mii); 769 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 770 media = mii->mii_media_active & ~IFM_10_T; 771 media |= IFM_100_TX; 772 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 773 media = mii->mii_media_active & ~IFM_100_TX; 774 media |= IFM_10_T; 775 } else 776 return; 777 778 ifmedia_set(&mii->mii_media, media); 779 780 return; 781} 782 783/* 784 * Probe for a Winbond chip. Check the PCI vendor and device 785 * IDs against our list and return a device name if we find a match. 786 */ 787static int wb_probe(dev) 788 device_t dev; 789{ 790 struct wb_type *t; 791 792 t = wb_devs; 793 794 while(t->wb_name != NULL) { 795 if ((pci_get_vendor(dev) == t->wb_vid) && 796 (pci_get_device(dev) == t->wb_did)) { 797 device_set_desc(dev, t->wb_name); 798 return(0); 799 } 800 t++; 801 } 802 803 return(ENXIO); 804} 805 806/* 807 * Attach the interface. Allocate softc structures, do ifmedia 808 * setup and ethernet/BPF attach. 809 */ 810static int wb_attach(dev) 811 device_t dev; 812{ 813 int s; 814 u_char eaddr[ETHER_ADDR_LEN]; 815 u_int32_t command; 816 struct wb_softc *sc; 817 struct ifnet *ifp; 818 int unit, error = 0, rid; 819 820 s = splimp(); 821 822 sc = device_get_softc(dev); 823 unit = device_get_unit(dev); 824 825 /* 826 * Handle power management nonsense. 827 */ 828 829 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 830 if (command == 0x01) { 831 832 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 833 if (command & WB_PSTATE_MASK) { 834 u_int32_t iobase, membase, irq; 835 836 /* Save important PCI config data. */ 837 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 838 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 839 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 840 841 /* Reset the power state. */ 842 printf("wb%d: chip is in D%d power mode " 843 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 844 command &= 0xFFFFFFFC; 845 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 846 847 /* Restore PCI config data. */ 848 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 849 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 850 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 851 } 852 } 853 854 /* 855 * Map control/status registers. 856 */ 857 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 858 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 859 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 860 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 861 862#ifdef WB_USEIOSPACE 863 if (!(command & PCIM_CMD_PORTEN)) { 864 printf("wb%d: failed to enable I/O ports!\n", unit); 865 error = ENXIO; 866 goto fail; 867 } 868#else 869 if (!(command & PCIM_CMD_MEMEN)) { 870 printf("wb%d: failed to enable memory mapping!\n", unit); 871 error = ENXIO; 872 goto fail; 873 } 874#endif 875 876 rid = WB_RID; 877 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 878 0, ~0, 1, RF_ACTIVE); 879 880 if (sc->wb_res == NULL) { 881 printf("wb%d: couldn't map ports/memory\n", unit); 882 error = ENXIO; 883 goto fail; 884 } 885 886 sc->wb_btag = rman_get_bustag(sc->wb_res); 887 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 888 889 /* Allocate interrupt */ 890 rid = 0; 891 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 892 RF_SHAREABLE | RF_ACTIVE); 893 894 if (sc->wb_irq == NULL) { 895 printf("wb%d: couldn't map interrupt\n", unit); 896 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 897 error = ENXIO; 898 goto fail; 899 } 900 901 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 902 wb_intr, sc, &sc->wb_intrhand); 903 904 if (error) { 905 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 906 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 907 printf("wb%d: couldn't set up irq\n", unit); 908 goto fail; 909 } 910 911 /* Save the cache line size. */ 912 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 913 914 /* Reset the adapter. */ 915 wb_reset(sc); 916 917 /* 918 * Get station address from the EEPROM. 919 */ 920 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 921 922 /* 923 * A Winbond chip was detected. Inform the world. 924 */ 925 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 926 927 sc->wb_unit = unit; 928 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 929 930 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 931 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 932 933 if (sc->wb_ldata == NULL) { 934 printf("wb%d: no memory for list buffers!\n", unit); 935 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 936 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 937 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 938 error = ENXIO; 939 goto fail; 940 } 941 942 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 943 944 ifp = &sc->arpcom.ac_if; 945 ifp->if_softc = sc; 946 ifp->if_unit = unit; 947 ifp->if_name = "wb"; 948 ifp->if_mtu = ETHERMTU; 949 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 950 ifp->if_ioctl = wb_ioctl; 951 ifp->if_output = ether_output; 952 ifp->if_start = wb_start; 953 ifp->if_watchdog = wb_watchdog; 954 ifp->if_init = wb_init; 955 ifp->if_baudrate = 10000000; 956 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 957 958 /* 959 * Do MII setup. 960 */ 961 if (mii_phy_probe(dev, &sc->wb_miibus, 962 wb_ifmedia_upd, wb_ifmedia_sts)) { 963 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 964 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 965 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 966 free(sc->wb_ldata_ptr, M_DEVBUF); 967 error = ENXIO; 968 goto fail; 969 } 970 971 /* 972 * Call MI attach routines. 973 */ 974 if_attach(ifp); 975 ether_ifattach(ifp); 976 977 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 978 979fail: 980 if (error) 981 device_delete_child(dev, sc->wb_miibus); 982 splx(s); 983 984 return(error); 985} 986 987static int wb_detach(dev) 988 device_t dev; 989{ 990 struct wb_softc *sc; 991 struct ifnet *ifp; 992 int s; 993 994 s = splimp(); 995 996 sc = device_get_softc(dev); 997 ifp = &sc->arpcom.ac_if; 998 999 wb_stop(sc); 1000 if_detach(ifp); 1001 1002 /* Delete any miibus and phy devices attached to this interface */ 1003 bus_generic_detach(dev); 1004 device_delete_child(dev, sc->wb_miibus); 1005 1006 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1007 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1008 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1009 1010 free(sc->wb_ldata_ptr, M_DEVBUF); 1011 1012 splx(s); 1013 1014 return(0); 1015} 1016 1017/* 1018 * Initialize the transmit descriptors. 1019 */ 1020static int wb_list_tx_init(sc) 1021 struct wb_softc *sc; 1022{ 1023 struct wb_chain_data *cd; 1024 struct wb_list_data *ld; 1025 int i; 1026 1027 cd = &sc->wb_cdata; 1028 ld = sc->wb_ldata; 1029 1030 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1031 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1032 if (i == (WB_TX_LIST_CNT - 1)) { 1033 cd->wb_tx_chain[i].wb_nextdesc = 1034 &cd->wb_tx_chain[0]; 1035 } else { 1036 cd->wb_tx_chain[i].wb_nextdesc = 1037 &cd->wb_tx_chain[i + 1]; 1038 } 1039 } 1040 1041 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1042 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1043 1044 return(0); 1045} 1046 1047 1048/* 1049 * Initialize the RX descriptors and allocate mbufs for them. Note that 1050 * we arrange the descriptors in a closed ring, so that the last descriptor 1051 * points back to the first. 1052 */ 1053static int wb_list_rx_init(sc) 1054 struct wb_softc *sc; 1055{ 1056 struct wb_chain_data *cd; 1057 struct wb_list_data *ld; 1058 int i; 1059 1060 cd = &sc->wb_cdata; 1061 ld = sc->wb_ldata; 1062 1063 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1064 cd->wb_rx_chain[i].wb_ptr = 1065 (struct wb_desc *)&ld->wb_rx_list[i]; 1066 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1067 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1068 return(ENOBUFS); 1069 if (i == (WB_RX_LIST_CNT - 1)) { 1070 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1071 ld->wb_rx_list[i].wb_next = 1072 vtophys(&ld->wb_rx_list[0]); 1073 } else { 1074 cd->wb_rx_chain[i].wb_nextdesc = 1075 &cd->wb_rx_chain[i + 1]; 1076 ld->wb_rx_list[i].wb_next = 1077 vtophys(&ld->wb_rx_list[i + 1]); 1078 } 1079 } 1080 1081 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1082 1083 return(0); 1084} 1085 1086static void wb_bfree(buf, size) 1087 caddr_t buf; 1088 u_int size; 1089{ 1090 return; 1091} 1092 1093/* 1094 * Initialize an RX descriptor and attach an MBUF cluster. 1095 */ 1096static int wb_newbuf(sc, c, m) 1097 struct wb_softc *sc; 1098 struct wb_chain_onefrag *c; 1099 struct mbuf *m; 1100{ 1101 struct mbuf *m_new = NULL; 1102 1103 if (m == NULL) { 1104 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1105 if (m_new == NULL) { 1106 printf("wb%d: no memory for rx " 1107 "list -- packet dropped!\n", sc->wb_unit); 1108 return(ENOBUFS); 1109 } 1110 1111 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1112 m_new->m_flags |= M_EXT; 1113 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1114 m_new->m_len = WB_BUFBYTES; 1115 m_new->m_ext.ext_free = wb_bfree; 1116 m_new->m_ext.ext_ref = wb_bfree; 1117 } else { 1118 m_new = m; 1119 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1120 m_new->m_data = m_new->m_ext.ext_buf; 1121 } 1122 1123 m_adj(m_new, sizeof(u_int64_t)); 1124 1125 c->wb_mbuf = m_new; 1126 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1127 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1128 c->wb_ptr->wb_status = WB_RXSTAT; 1129 1130 return(0); 1131} 1132 1133/* 1134 * A frame has been uploaded: pass the resulting mbuf chain up to 1135 * the higher level protocols. 1136 */ 1137static void wb_rxeof(sc) 1138 struct wb_softc *sc; 1139{ 1140 struct ether_header *eh; 1141 struct mbuf *m = NULL; 1142 struct ifnet *ifp; 1143 struct wb_chain_onefrag *cur_rx; 1144 int total_len = 0; 1145 u_int32_t rxstat; 1146 1147 ifp = &sc->arpcom.ac_if; 1148 1149 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1150 WB_RXSTAT_OWN)) { 1151 struct mbuf *m0 = NULL; 1152 1153 cur_rx = sc->wb_cdata.wb_rx_head; 1154 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1155 1156 m = cur_rx->wb_mbuf; 1157 1158 if ((rxstat & WB_RXSTAT_MIIERR) || 1159 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1160 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1161 !(rxstat & WB_RXSTAT_LASTFRAG) || 1162 !(rxstat & WB_RXSTAT_RXCMP)) { 1163 ifp->if_ierrors++; 1164 wb_newbuf(sc, cur_rx, m); 1165 printf("wb%x: receiver babbling: possible chip " 1166 "bug, forcing reset\n", sc->wb_unit); 1167 wb_fixmedia(sc); 1168 wb_reset(sc); 1169 wb_init(sc); 1170 return; 1171 } 1172 1173 if (rxstat & WB_RXSTAT_RXERR) { 1174 ifp->if_ierrors++; 1175 wb_newbuf(sc, cur_rx, m); 1176 break; 1177 } 1178 1179 /* No errors; receive the packet. */ 1180 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1181 1182 /* 1183 * XXX The Winbond chip includes the CRC with every 1184 * received frame, and there's no way to turn this 1185 * behavior off (at least, I can't find anything in 1186 * the manual that explains how to do it) so we have 1187 * to trim off the CRC manually. 1188 */ 1189 total_len -= ETHER_CRC_LEN; 1190 1191 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1192 total_len + ETHER_ALIGN, 0, ifp, NULL); 1193 wb_newbuf(sc, cur_rx, m); 1194 if (m0 == NULL) { 1195 ifp->if_ierrors++; 1196 break; 1197 } 1198 m_adj(m0, ETHER_ALIGN); 1199 m = m0; 1200 1201 ifp->if_ipackets++; 1202 eh = mtod(m, struct ether_header *); 1203 1204#ifdef BRIDGE 1205 if (do_bridge) { 1206 struct ifnet *bdg_ifp; 1207 bdg_ifp = bridge_in(m); 1208 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 1209 bdg_forward(&m, bdg_ifp); 1210 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 1211 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 1212 m_freem(m); 1213 break; 1214 } 1215 } 1216#endif 1217 1218 /* 1219 * Handle BPF listeners. Let the BPF user see the packet, but 1220 * don't pass it up to the ether_input() layer unless it's 1221 * a broadcast packet, multicast packet, matches our ethernet 1222 * address or the interface is in promiscuous mode. 1223 */ 1224 if (ifp->if_bpf) { 1225 bpf_mtap(ifp, m); 1226 if (ifp->if_flags & IFF_PROMISC && 1227 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1228 ETHER_ADDR_LEN) && 1229 (eh->ether_dhost[0] & 1) == 0)) { 1230 m_freem(m); 1231 break; 1232 } 1233 } 1234 1235 /* Remove header from mbuf and pass it on. */ 1236 m_adj(m, sizeof(struct ether_header)); 1237 ether_input(ifp, eh, m); 1238 } 1239 1240 return; 1241} 1242 1243void wb_rxeoc(sc) 1244 struct wb_softc *sc; 1245{ 1246 wb_rxeof(sc); 1247 1248 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1249 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1250 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1251 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1252 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1253 1254 return; 1255} 1256 1257/* 1258 * A frame was downloaded to the chip. It's safe for us to clean up 1259 * the list buffers. 1260 */ 1261static void wb_txeof(sc) 1262 struct wb_softc *sc; 1263{ 1264 struct wb_chain *cur_tx; 1265 struct ifnet *ifp; 1266 1267 ifp = &sc->arpcom.ac_if; 1268 1269 /* Clear the timeout timer. */ 1270 ifp->if_timer = 0; 1271 1272 if (sc->wb_cdata.wb_tx_head == NULL) 1273 return; 1274 1275 /* 1276 * Go through our tx list and free mbufs for those 1277 * frames that have been transmitted. 1278 */ 1279 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1280 u_int32_t txstat; 1281 1282 cur_tx = sc->wb_cdata.wb_tx_head; 1283 txstat = WB_TXSTATUS(cur_tx); 1284 1285 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1286 break; 1287 1288 if (txstat & WB_TXSTAT_TXERR) { 1289 ifp->if_oerrors++; 1290 if (txstat & WB_TXSTAT_ABORT) 1291 ifp->if_collisions++; 1292 if (txstat & WB_TXSTAT_LATECOLL) 1293 ifp->if_collisions++; 1294 } 1295 1296 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1297 1298 ifp->if_opackets++; 1299 m_freem(cur_tx->wb_mbuf); 1300 cur_tx->wb_mbuf = NULL; 1301 1302 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1303 sc->wb_cdata.wb_tx_head = NULL; 1304 sc->wb_cdata.wb_tx_tail = NULL; 1305 break; 1306 } 1307 1308 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1309 } 1310 1311 return; 1312} 1313 1314/* 1315 * TX 'end of channel' interrupt handler. 1316 */ 1317static void wb_txeoc(sc) 1318 struct wb_softc *sc; 1319{ 1320 struct ifnet *ifp; 1321 1322 ifp = &sc->arpcom.ac_if; 1323 1324 ifp->if_timer = 0; 1325 1326 if (sc->wb_cdata.wb_tx_head == NULL) { 1327 ifp->if_flags &= ~IFF_OACTIVE; 1328 sc->wb_cdata.wb_tx_tail = NULL; 1329 } else { 1330 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1331 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1332 ifp->if_timer = 5; 1333 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1334 } 1335 } 1336 1337 return; 1338} 1339 1340static void wb_intr(arg) 1341 void *arg; 1342{ 1343 struct wb_softc *sc; 1344 struct ifnet *ifp; 1345 u_int32_t status; 1346 1347 sc = arg; 1348 ifp = &sc->arpcom.ac_if; 1349 1350 if (!(ifp->if_flags & IFF_UP)) 1351 return; 1352 1353 /* Disable interrupts. */ 1354 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1355 1356 for (;;) { 1357 1358 status = CSR_READ_4(sc, WB_ISR); 1359 if (status) 1360 CSR_WRITE_4(sc, WB_ISR, status); 1361 1362 if ((status & WB_INTRS) == 0) 1363 break; 1364 1365 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1366 ifp->if_ierrors++; 1367 wb_reset(sc); 1368 if (status & WB_ISR_RX_ERR) 1369 wb_fixmedia(sc); 1370 wb_init(sc); 1371 continue; 1372 } 1373 1374 if (status & WB_ISR_RX_OK) 1375 wb_rxeof(sc); 1376 1377 if (status & WB_ISR_RX_IDLE) 1378 wb_rxeoc(sc); 1379 1380 if (status & WB_ISR_TX_OK) 1381 wb_txeof(sc); 1382 1383 if (status & WB_ISR_TX_NOBUF) 1384 wb_txeoc(sc); 1385 1386 if (status & WB_ISR_TX_IDLE) { 1387 wb_txeof(sc); 1388 if (sc->wb_cdata.wb_tx_head != NULL) { 1389 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1390 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1391 } 1392 } 1393 1394 if (status & WB_ISR_TX_UNDERRUN) { 1395 ifp->if_oerrors++; 1396 wb_txeof(sc); 1397 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1398 /* Jack up TX threshold */ 1399 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1400 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1401 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1402 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1403 } 1404 1405 if (status & WB_ISR_BUS_ERR) { 1406 wb_reset(sc); 1407 wb_init(sc); 1408 } 1409 1410 } 1411 1412 /* Re-enable interrupts. */ 1413 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1414 1415 if (ifp->if_snd.ifq_head != NULL) { 1416 wb_start(ifp); 1417 } 1418 1419 return; 1420} 1421 1422static void wb_tick(xsc) 1423 void *xsc; 1424{ 1425 struct wb_softc *sc; 1426 struct mii_data *mii; 1427 int s; 1428 1429 s = splimp(); 1430 1431 sc = xsc; 1432 mii = device_get_softc(sc->wb_miibus); 1433 1434 mii_tick(mii); 1435 1436 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1437 1438 splx(s); 1439 1440 return; 1441} 1442 1443/* 1444 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1445 * pointers to the fragment pointers. 1446 */ 1447static int wb_encap(sc, c, m_head) 1448 struct wb_softc *sc; 1449 struct wb_chain *c; 1450 struct mbuf *m_head; 1451{ 1452 int frag = 0; 1453 struct wb_desc *f = NULL; 1454 int total_len; 1455 struct mbuf *m; 1456 1457 /* 1458 * Start packing the mbufs in this chain into 1459 * the fragment pointers. Stop when we run out 1460 * of fragments or hit the end of the mbuf chain. 1461 */ 1462 m = m_head; 1463 total_len = 0; 1464 1465 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1466 if (m->m_len != 0) { 1467 if (frag == WB_MAXFRAGS) 1468 break; 1469 total_len += m->m_len; 1470 f = &c->wb_ptr->wb_frag[frag]; 1471 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1472 if (frag == 0) { 1473 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1474 f->wb_status = 0; 1475 } else 1476 f->wb_status = WB_TXSTAT_OWN; 1477 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1478 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1479 frag++; 1480 } 1481 } 1482 1483 /* 1484 * Handle special case: we used up all 16 fragments, 1485 * but we have more mbufs left in the chain. Copy the 1486 * data into an mbuf cluster. Note that we don't 1487 * bother clearing the values in the other fragment 1488 * pointers/counters; it wouldn't gain us anything, 1489 * and would waste cycles. 1490 */ 1491 if (m != NULL) { 1492 struct mbuf *m_new = NULL; 1493 1494 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1495 if (m_new == NULL) { 1496 printf("wb%d: no memory for tx list", sc->wb_unit); 1497 return(1); 1498 } 1499 if (m_head->m_pkthdr.len > MHLEN) { 1500 MCLGET(m_new, M_DONTWAIT); 1501 if (!(m_new->m_flags & M_EXT)) { 1502 m_freem(m_new); 1503 printf("wb%d: no memory for tx list", 1504 sc->wb_unit); 1505 return(1); 1506 } 1507 } 1508 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1509 mtod(m_new, caddr_t)); 1510 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1511 m_freem(m_head); 1512 m_head = m_new; 1513 f = &c->wb_ptr->wb_frag[0]; 1514 f->wb_status = 0; 1515 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1516 f->wb_ctl = total_len = m_new->m_len; 1517 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1518 frag = 1; 1519 } 1520 1521 if (total_len < WB_MIN_FRAMELEN) { 1522 f = &c->wb_ptr->wb_frag[frag]; 1523 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1524 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1525 f->wb_ctl |= WB_TXCTL_TLINK; 1526 f->wb_status = WB_TXSTAT_OWN; 1527 frag++; 1528 } 1529 1530 c->wb_mbuf = m_head; 1531 c->wb_lastdesc = frag - 1; 1532 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1533 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1534 1535 return(0); 1536} 1537 1538/* 1539 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1540 * to the mbuf data regions directly in the transmit lists. We also save a 1541 * copy of the pointers since the transmit list fragment pointers are 1542 * physical addresses. 1543 */ 1544 1545static void wb_start(ifp) 1546 struct ifnet *ifp; 1547{ 1548 struct wb_softc *sc; 1549 struct mbuf *m_head = NULL; 1550 struct wb_chain *cur_tx = NULL, *start_tx; 1551 1552 sc = ifp->if_softc; 1553 1554 /* 1555 * Check for an available queue slot. If there are none, 1556 * punt. 1557 */ 1558 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1559 ifp->if_flags |= IFF_OACTIVE; 1560 return; 1561 } 1562 1563 start_tx = sc->wb_cdata.wb_tx_free; 1564 1565 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1566 IF_DEQUEUE(&ifp->if_snd, m_head); 1567 if (m_head == NULL) 1568 break; 1569 1570 /* Pick a descriptor off the free list. */ 1571 cur_tx = sc->wb_cdata.wb_tx_free; 1572 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1573 1574 /* Pack the data into the descriptor. */ 1575 wb_encap(sc, cur_tx, m_head); 1576 1577 if (cur_tx != start_tx) 1578 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1579 1580 /* 1581 * If there's a BPF listener, bounce a copy of this frame 1582 * to him. 1583 */ 1584 if (ifp->if_bpf) 1585 bpf_mtap(ifp, cur_tx->wb_mbuf); 1586 } 1587 1588 /* 1589 * If there are no packets queued, bail. 1590 */ 1591 if (cur_tx == NULL) 1592 return; 1593 1594 /* 1595 * Place the request for the upload interrupt 1596 * in the last descriptor in the chain. This way, if 1597 * we're chaining several packets at once, we'll only 1598 * get an interupt once for the whole chain rather than 1599 * once for each packet. 1600 */ 1601 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1602 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1603 sc->wb_cdata.wb_tx_tail = cur_tx; 1604 1605 if (sc->wb_cdata.wb_tx_head == NULL) { 1606 sc->wb_cdata.wb_tx_head = start_tx; 1607 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1608 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1609 } else { 1610 /* 1611 * We need to distinguish between the case where 1612 * the own bit is clear because the chip cleared it 1613 * and where the own bit is clear because we haven't 1614 * set it yet. The magic value WB_UNSET is just some 1615 * ramdomly chosen number which doesn't have the own 1616 * bit set. When we actually transmit the frame, the 1617 * status word will have _only_ the own bit set, so 1618 * the txeoc handler will be able to tell if it needs 1619 * to initiate another transmission to flush out pending 1620 * frames. 1621 */ 1622 WB_TXOWN(start_tx) = WB_UNSENT; 1623 } 1624 1625 /* 1626 * Set a timeout in case the chip goes out to lunch. 1627 */ 1628 ifp->if_timer = 5; 1629 1630 return; 1631} 1632 1633static void wb_init(xsc) 1634 void *xsc; 1635{ 1636 struct wb_softc *sc = xsc; 1637 struct ifnet *ifp = &sc->arpcom.ac_if; 1638 int s, i; 1639 struct mii_data *mii; 1640 1641 s = splimp(); 1642 1643 mii = device_get_softc(sc->wb_miibus); 1644 1645 /* 1646 * Cancel pending I/O and free all RX/TX buffers. 1647 */ 1648 wb_stop(sc); 1649 wb_reset(sc); 1650 1651 sc->wb_txthresh = WB_TXTHRESH_INIT; 1652 1653 /* 1654 * Set cache alignment and burst length. 1655 */ 1656#ifdef foo 1657 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1658 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1659 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1660#endif 1661 1662 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1663 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1664 switch(sc->wb_cachesize) { 1665 case 32: 1666 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1667 break; 1668 case 16: 1669 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1670 break; 1671 case 8: 1672 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1673 break; 1674 case 0: 1675 default: 1676 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1677 break; 1678 } 1679 1680 /* This doesn't tend to work too well at 100Mbps. */ 1681 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1682 1683 /* Init our MAC address */ 1684 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1685 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1686 } 1687 1688 /* Init circular RX list. */ 1689 if (wb_list_rx_init(sc) == ENOBUFS) { 1690 printf("wb%d: initialization failed: no " 1691 "memory for rx buffers\n", sc->wb_unit); 1692 wb_stop(sc); 1693 (void)splx(s); 1694 return; 1695 } 1696 1697 /* Init TX descriptors. */ 1698 wb_list_tx_init(sc); 1699 1700 /* If we want promiscuous mode, set the allframes bit. */ 1701 if (ifp->if_flags & IFF_PROMISC) { 1702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1703 } else { 1704 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1705 } 1706 1707 /* 1708 * Set capture broadcast bit to capture broadcast frames. 1709 */ 1710 if (ifp->if_flags & IFF_BROADCAST) { 1711 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1712 } else { 1713 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1714 } 1715 1716 /* 1717 * Program the multicast filter, if necessary. 1718 */ 1719 wb_setmulti(sc); 1720 1721 /* 1722 * Load the address of the RX list. 1723 */ 1724 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1725 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1726 1727 /* 1728 * Enable interrupts. 1729 */ 1730 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1731 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1732 1733 /* Enable receiver and transmitter. */ 1734 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1735 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1736 1737 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1738 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1739 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1740 1741 mii_mediachg(mii); 1742 1743 ifp->if_flags |= IFF_RUNNING; 1744 ifp->if_flags &= ~IFF_OACTIVE; 1745 1746 (void)splx(s); 1747 1748 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1749 1750 return; 1751} 1752 1753/* 1754 * Set media options. 1755 */ 1756static int wb_ifmedia_upd(ifp) 1757 struct ifnet *ifp; 1758{ 1759 struct wb_softc *sc; 1760 1761 sc = ifp->if_softc; 1762 1763 if (ifp->if_flags & IFF_UP) 1764 wb_init(sc); 1765 1766 return(0); 1767} 1768 1769/* 1770 * Report current media status. 1771 */ 1772static void wb_ifmedia_sts(ifp, ifmr) 1773 struct ifnet *ifp; 1774 struct ifmediareq *ifmr; 1775{ 1776 struct wb_softc *sc; 1777 struct mii_data *mii; 1778 1779 sc = ifp->if_softc; 1780 1781 mii = device_get_softc(sc->wb_miibus); 1782 1783 mii_pollstat(mii); 1784 ifmr->ifm_active = mii->mii_media_active; 1785 ifmr->ifm_status = mii->mii_media_status; 1786 1787 return; 1788} 1789 1790static int wb_ioctl(ifp, command, data) 1791 struct ifnet *ifp; 1792 u_long command; 1793 caddr_t data; 1794{ 1795 struct wb_softc *sc = ifp->if_softc; 1796 struct mii_data *mii; 1797 struct ifreq *ifr = (struct ifreq *) data; 1798 int s, error = 0; 1799 1800 s = splimp(); 1801 1802 switch(command) { 1803 case SIOCSIFADDR: 1804 case SIOCGIFADDR: 1805 case SIOCSIFMTU: 1806 error = ether_ioctl(ifp, command, data); 1807 break; 1808 case SIOCSIFFLAGS: 1809 if (ifp->if_flags & IFF_UP) { 1810 wb_init(sc); 1811 } else { 1812 if (ifp->if_flags & IFF_RUNNING) 1813 wb_stop(sc); 1814 } 1815 error = 0; 1816 break; 1817 case SIOCADDMULTI: 1818 case SIOCDELMULTI: 1819 wb_setmulti(sc); 1820 error = 0; 1821 break; 1822 case SIOCGIFMEDIA: 1823 case SIOCSIFMEDIA: 1824 mii = device_get_softc(sc->wb_miibus); 1825 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1826 break; 1827 default: 1828 error = EINVAL; 1829 break; 1830 } 1831 1832 (void)splx(s); 1833 1834 return(error); 1835} 1836 1837static void wb_watchdog(ifp) 1838 struct ifnet *ifp; 1839{ 1840 struct wb_softc *sc; 1841 1842 sc = ifp->if_softc; 1843 1844 ifp->if_oerrors++; 1845 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1846#ifdef foo 1847 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1848 printf("wb%d: no carrier - transceiver cable problem?\n", 1849 sc->wb_unit); 1850#endif 1851 wb_stop(sc); 1852 wb_reset(sc); 1853 wb_init(sc); 1854 1855 if (ifp->if_snd.ifq_head != NULL) 1856 wb_start(ifp); 1857 1858 return; 1859} 1860 1861/* 1862 * Stop the adapter and free any mbufs allocated to the 1863 * RX and TX lists. 1864 */ 1865static void wb_stop(sc) 1866 struct wb_softc *sc; 1867{ 1868 register int i; 1869 struct ifnet *ifp; 1870 1871 ifp = &sc->arpcom.ac_if; 1872 ifp->if_timer = 0; 1873 1874 untimeout(wb_tick, sc, sc->wb_stat_ch); 1875 1876 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1877 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1878 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1879 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1880 1881 /* 1882 * Free data in the RX lists. 1883 */ 1884 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1885 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1886 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1887 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1888 } 1889 } 1890 bzero((char *)&sc->wb_ldata->wb_rx_list, 1891 sizeof(sc->wb_ldata->wb_rx_list)); 1892 1893 /* 1894 * Free the TX list buffers. 1895 */ 1896 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1897 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1898 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1899 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1900 } 1901 } 1902 1903 bzero((char *)&sc->wb_ldata->wb_tx_list, 1904 sizeof(sc->wb_ldata->wb_tx_list)); 1905 1906 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1907 1908 return; 1909} 1910 1911/* 1912 * Stop all chip I/O so that the kernel's probe routines don't 1913 * get confused by errant DMAs when rebooting. 1914 */ 1915static void wb_shutdown(dev) 1916 device_t dev; 1917{ 1918 struct wb_softc *sc; 1919 1920 sc = device_get_softc(dev); 1921 wb_stop(sc); 1922 1923 return; 1924} 1925