if_wb.c revision 51473
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 * 32 * $FreeBSD: head/sys/pci/if_wb.c 51473 1999-09-20 19:06:45Z wpaul $ 33 */ 34 35/* 36 * Winbond fast ethernet PCI NIC driver 37 * 38 * Supports various cheap network adapters based on the Winbond W89C840F 39 * fast ethernet controller chip. This includes adapters manufactured by 40 * Winbond itself and some made by Linksys. 41 * 42 * Written by Bill Paul <wpaul@ctr.columbia.edu> 43 * Electrical Engineering Department 44 * Columbia University, New York City 45 */ 46 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "bpf.h" 87#include "opt_bdg.h" 88 89#include <sys/param.h> 90#include <sys/systm.h> 91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#if NBPF > 0 105#include <net/bpf.h> 106#endif 107 108#ifdef BRIDGE 109#include <net/bridge.h> 110#endif 111 112#include <vm/vm.h> /* for vtophys */ 113#include <vm/pmap.h> /* for vtophys */ 114#include <machine/clock.h> /* for DELAY */ 115#include <machine/bus_memio.h> 116#include <machine/bus_pio.h> 117#include <machine/bus.h> 118#include <machine/resource.h> 119#include <sys/bus.h> 120#include <sys/rman.h> 121 122#include <pci/pcireg.h> 123#include <pci/pcivar.h> 124 125#include <dev/mii/mii.h> 126#include <dev/mii/miivar.h> 127 128/* "controller miibus0" required. See GENERIC if you get errors here. */ 129#include "miibus_if.h" 130 131#define WB_USEIOSPACE 132 133#include <pci/if_wbreg.h> 134 135#ifndef lint 136static const char rcsid[] = 137 "$FreeBSD: head/sys/pci/if_wb.c 51473 1999-09-20 19:06:45Z wpaul $"; 138#endif 139 140/* 141 * Various supported device vendors/types and their names. 142 */ 143static struct wb_type wb_devs[] = { 144 { WB_VENDORID, WB_DEVICEID_840F, 145 "Winbond W89C840F 10/100BaseTX" }, 146 { CP_VENDORID, CP_DEVICEID_RL100, 147 "Compex RL100-ATX 10/100baseTX" }, 148 { 0, 0, NULL } 149}; 150 151static int wb_probe __P((device_t)); 152static int wb_attach __P((device_t)); 153static int wb_detach __P((device_t)); 154 155static void wb_bfree __P((caddr_t, u_int)); 156static int wb_newbuf __P((struct wb_softc *, 157 struct wb_chain_onefrag *, 158 struct mbuf *)); 159static int wb_encap __P((struct wb_softc *, struct wb_chain *, 160 struct mbuf *)); 161 162static void wb_rxeof __P((struct wb_softc *)); 163static void wb_rxeoc __P((struct wb_softc *)); 164static void wb_txeof __P((struct wb_softc *)); 165static void wb_txeoc __P((struct wb_softc *)); 166static void wb_intr __P((void *)); 167static void wb_tick __P((void *)); 168static void wb_start __P((struct ifnet *)); 169static int wb_ioctl __P((struct ifnet *, u_long, caddr_t)); 170static void wb_init __P((void *)); 171static void wb_stop __P((struct wb_softc *)); 172static void wb_watchdog __P((struct ifnet *)); 173static void wb_shutdown __P((device_t)); 174static int wb_ifmedia_upd __P((struct ifnet *)); 175static void wb_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 176 177static void wb_eeprom_putbyte __P((struct wb_softc *, int)); 178static void wb_eeprom_getword __P((struct wb_softc *, int, u_int16_t *)); 179static void wb_read_eeprom __P((struct wb_softc *, caddr_t, int, 180 int, int)); 181static void wb_mii_sync __P((struct wb_softc *)); 182static void wb_mii_send __P((struct wb_softc *, u_int32_t, int)); 183static int wb_mii_readreg __P((struct wb_softc *, struct wb_mii_frame *)); 184static int wb_mii_writereg __P((struct wb_softc *, struct wb_mii_frame *)); 185 186static void wb_setcfg __P((struct wb_softc *, u_int32_t)); 187static u_int8_t wb_calchash __P((caddr_t)); 188static void wb_setmulti __P((struct wb_softc *)); 189static void wb_reset __P((struct wb_softc *)); 190static void wb_fixmedia __P((struct wb_softc *)); 191static int wb_list_rx_init __P((struct wb_softc *)); 192static int wb_list_tx_init __P((struct wb_softc *)); 193 194static int wb_miibus_readreg __P((device_t, int, int)); 195static int wb_miibus_writereg __P((device_t, int, int, int)); 196static void wb_miibus_statchg __P((device_t)); 197 198#ifdef WB_USEIOSPACE 199#define WB_RES SYS_RES_IOPORT 200#define WB_RID WB_PCI_LOIO 201#else 202#define WB_RES SYS_RES_MEMORY 203#define WB_RID WB_PCI_LOMEM 204#endif 205 206static device_method_t wb_methods[] = { 207 /* Device interface */ 208 DEVMETHOD(device_probe, wb_probe), 209 DEVMETHOD(device_attach, wb_attach), 210 DEVMETHOD(device_detach, wb_detach), 211 DEVMETHOD(device_shutdown, wb_shutdown), 212 213 /* bus interface, for miibus */ 214 DEVMETHOD(bus_print_child, bus_generic_print_child), 215 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 216 217 /* MII interface */ 218 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 219 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 220 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 221 { 0, 0 } 222}; 223 224static driver_t wb_driver = { 225 "wb", 226 wb_methods, 227 sizeof(struct wb_softc) 228}; 229 230static devclass_t wb_devclass; 231 232DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 233DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 234 235#define WB_SETBIT(sc, reg, x) \ 236 CSR_WRITE_4(sc, reg, \ 237 CSR_READ_4(sc, reg) | x) 238 239#define WB_CLRBIT(sc, reg, x) \ 240 CSR_WRITE_4(sc, reg, \ 241 CSR_READ_4(sc, reg) & ~x) 242 243#define SIO_SET(x) \ 244 CSR_WRITE_4(sc, WB_SIO, \ 245 CSR_READ_4(sc, WB_SIO) | x) 246 247#define SIO_CLR(x) \ 248 CSR_WRITE_4(sc, WB_SIO, \ 249 CSR_READ_4(sc, WB_SIO) & ~x) 250 251/* 252 * Send a read command and address to the EEPROM, check for ACK. 253 */ 254static void wb_eeprom_putbyte(sc, addr) 255 struct wb_softc *sc; 256 int addr; 257{ 258 register int d, i; 259 260 d = addr | WB_EECMD_READ; 261 262 /* 263 * Feed in each bit and stobe the clock. 264 */ 265 for (i = 0x400; i; i >>= 1) { 266 if (d & i) { 267 SIO_SET(WB_SIO_EE_DATAIN); 268 } else { 269 SIO_CLR(WB_SIO_EE_DATAIN); 270 } 271 DELAY(100); 272 SIO_SET(WB_SIO_EE_CLK); 273 DELAY(150); 274 SIO_CLR(WB_SIO_EE_CLK); 275 DELAY(100); 276 } 277 278 return; 279} 280 281/* 282 * Read a word of data stored in the EEPROM at address 'addr.' 283 */ 284static void wb_eeprom_getword(sc, addr, dest) 285 struct wb_softc *sc; 286 int addr; 287 u_int16_t *dest; 288{ 289 register int i; 290 u_int16_t word = 0; 291 292 /* Enter EEPROM access mode. */ 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Send address of word we want to read. 297 */ 298 wb_eeprom_putbyte(sc, addr); 299 300 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 301 302 /* 303 * Start reading bits from EEPROM. 304 */ 305 for (i = 0x8000; i; i >>= 1) { 306 SIO_SET(WB_SIO_EE_CLK); 307 DELAY(100); 308 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 309 word |= i; 310 SIO_CLR(WB_SIO_EE_CLK); 311 DELAY(100); 312 } 313 314 /* Turn off EEPROM access mode. */ 315 CSR_WRITE_4(sc, WB_SIO, 0); 316 317 *dest = word; 318 319 return; 320} 321 322/* 323 * Read a sequence of words from the EEPROM. 324 */ 325static void wb_read_eeprom(sc, dest, off, cnt, swap) 326 struct wb_softc *sc; 327 caddr_t dest; 328 int off; 329 int cnt; 330 int swap; 331{ 332 int i; 333 u_int16_t word = 0, *ptr; 334 335 for (i = 0; i < cnt; i++) { 336 wb_eeprom_getword(sc, off + i, &word); 337 ptr = (u_int16_t *)(dest + (i * 2)); 338 if (swap) 339 *ptr = ntohs(word); 340 else 341 *ptr = word; 342 } 343 344 return; 345} 346 347/* 348 * Sync the PHYs by setting data bit and strobing the clock 32 times. 349 */ 350static void wb_mii_sync(sc) 351 struct wb_softc *sc; 352{ 353 register int i; 354 355 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 356 357 for (i = 0; i < 32; i++) { 358 SIO_SET(WB_SIO_MII_CLK); 359 DELAY(1); 360 SIO_CLR(WB_SIO_MII_CLK); 361 DELAY(1); 362 } 363 364 return; 365} 366 367/* 368 * Clock a series of bits through the MII. 369 */ 370static void wb_mii_send(sc, bits, cnt) 371 struct wb_softc *sc; 372 u_int32_t bits; 373 int cnt; 374{ 375 int i; 376 377 SIO_CLR(WB_SIO_MII_CLK); 378 379 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 380 if (bits & i) { 381 SIO_SET(WB_SIO_MII_DATAIN); 382 } else { 383 SIO_CLR(WB_SIO_MII_DATAIN); 384 } 385 DELAY(1); 386 SIO_CLR(WB_SIO_MII_CLK); 387 DELAY(1); 388 SIO_SET(WB_SIO_MII_CLK); 389 } 390} 391 392/* 393 * Read an PHY register through the MII. 394 */ 395static int wb_mii_readreg(sc, frame) 396 struct wb_softc *sc; 397 struct wb_mii_frame *frame; 398 399{ 400 int i, ack, s; 401 402 s = splimp(); 403 404 /* 405 * Set up frame for RX. 406 */ 407 frame->mii_stdelim = WB_MII_STARTDELIM; 408 frame->mii_opcode = WB_MII_READOP; 409 frame->mii_turnaround = 0; 410 frame->mii_data = 0; 411 412 CSR_WRITE_4(sc, WB_SIO, 0); 413 414 /* 415 * Turn on data xmit. 416 */ 417 SIO_SET(WB_SIO_MII_DIR); 418 419 wb_mii_sync(sc); 420 421 /* 422 * Send command/address info. 423 */ 424 wb_mii_send(sc, frame->mii_stdelim, 2); 425 wb_mii_send(sc, frame->mii_opcode, 2); 426 wb_mii_send(sc, frame->mii_phyaddr, 5); 427 wb_mii_send(sc, frame->mii_regaddr, 5); 428 429 /* Idle bit */ 430 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 431 DELAY(1); 432 SIO_SET(WB_SIO_MII_CLK); 433 DELAY(1); 434 435 /* Turn off xmit. */ 436 SIO_CLR(WB_SIO_MII_DIR); 437 /* Check for ack */ 438 SIO_CLR(WB_SIO_MII_CLK); 439 DELAY(1); 440 SIO_SET(WB_SIO_MII_CLK); 441 DELAY(1); 442 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 443 SIO_CLR(WB_SIO_MII_CLK); 444 DELAY(1); 445 SIO_SET(WB_SIO_MII_CLK); 446 DELAY(1); 447 448 /* 449 * Now try reading data bits. If the ack failed, we still 450 * need to clock through 16 cycles to keep the PHY(s) in sync. 451 */ 452 if (ack) { 453 for(i = 0; i < 16; i++) { 454 SIO_CLR(WB_SIO_MII_CLK); 455 DELAY(1); 456 SIO_SET(WB_SIO_MII_CLK); 457 DELAY(1); 458 } 459 goto fail; 460 } 461 462 for (i = 0x8000; i; i >>= 1) { 463 SIO_CLR(WB_SIO_MII_CLK); 464 DELAY(1); 465 if (!ack) { 466 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 467 frame->mii_data |= i; 468 DELAY(1); 469 } 470 SIO_SET(WB_SIO_MII_CLK); 471 DELAY(1); 472 } 473 474fail: 475 476 SIO_CLR(WB_SIO_MII_CLK); 477 DELAY(1); 478 SIO_SET(WB_SIO_MII_CLK); 479 DELAY(1); 480 481 splx(s); 482 483 if (ack) 484 return(1); 485 return(0); 486} 487 488/* 489 * Write to a PHY register through the MII. 490 */ 491static int wb_mii_writereg(sc, frame) 492 struct wb_softc *sc; 493 struct wb_mii_frame *frame; 494 495{ 496 int s; 497 498 s = splimp(); 499 /* 500 * Set up frame for TX. 501 */ 502 503 frame->mii_stdelim = WB_MII_STARTDELIM; 504 frame->mii_opcode = WB_MII_WRITEOP; 505 frame->mii_turnaround = WB_MII_TURNAROUND; 506 507 /* 508 * Turn on data output. 509 */ 510 SIO_SET(WB_SIO_MII_DIR); 511 512 wb_mii_sync(sc); 513 514 wb_mii_send(sc, frame->mii_stdelim, 2); 515 wb_mii_send(sc, frame->mii_opcode, 2); 516 wb_mii_send(sc, frame->mii_phyaddr, 5); 517 wb_mii_send(sc, frame->mii_regaddr, 5); 518 wb_mii_send(sc, frame->mii_turnaround, 2); 519 wb_mii_send(sc, frame->mii_data, 16); 520 521 /* Idle bit. */ 522 SIO_SET(WB_SIO_MII_CLK); 523 DELAY(1); 524 SIO_CLR(WB_SIO_MII_CLK); 525 DELAY(1); 526 527 /* 528 * Turn off xmit. 529 */ 530 SIO_CLR(WB_SIO_MII_DIR); 531 532 splx(s); 533 534 return(0); 535} 536 537static int wb_miibus_readreg(dev, phy, reg) 538 device_t dev; 539 int phy, reg; 540{ 541 struct wb_softc *sc; 542 struct wb_mii_frame frame; 543 544 sc = device_get_softc(dev); 545 546 bzero((char *)&frame, sizeof(frame)); 547 548 frame.mii_phyaddr = phy; 549 frame.mii_regaddr = reg; 550 wb_mii_readreg(sc, &frame); 551 552 return(frame.mii_data); 553} 554 555static int wb_miibus_writereg(dev, phy, reg, data) 556 device_t dev; 557 int phy, reg, data; 558{ 559 struct wb_softc *sc; 560 struct wb_mii_frame frame; 561 562 sc = device_get_softc(dev); 563 564 bzero((char *)&frame, sizeof(frame)); 565 566 frame.mii_phyaddr = phy; 567 frame.mii_regaddr = reg; 568 frame.mii_data = data; 569 570 wb_mii_writereg(sc, &frame); 571 572 return(0); 573} 574 575static void wb_miibus_statchg(dev) 576 device_t dev; 577{ 578 struct wb_softc *sc; 579 struct mii_data *mii; 580 581 sc = device_get_softc(dev); 582 mii = device_get_softc(sc->wb_miibus); 583 wb_setcfg(sc, mii->mii_media_active); 584 585 return; 586} 587 588static u_int8_t wb_calchash(addr) 589 caddr_t addr; 590{ 591 u_int32_t crc, carry; 592 int i, j; 593 u_int8_t c; 594 595 /* Compute CRC for the address value. */ 596 crc = 0xFFFFFFFF; /* initial value */ 597 598 for (i = 0; i < 6; i++) { 599 c = *(addr + i); 600 for (j = 0; j < 8; j++) { 601 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 602 crc <<= 1; 603 c >>= 1; 604 if (carry) 605 crc = (crc ^ 0x04c11db6) | carry; 606 } 607 } 608 609 /* 610 * return the filter bit position 611 * Note: I arrived at the following nonsense 612 * through experimentation. It's not the usual way to 613 * generate the bit position but it's the only thing 614 * I could come up with that works. 615 */ 616 return(~(crc >> 26) & 0x0000003F); 617} 618 619/* 620 * Program the 64-bit multicast hash filter. 621 */ 622static void wb_setmulti(sc) 623 struct wb_softc *sc; 624{ 625 struct ifnet *ifp; 626 int h = 0; 627 u_int32_t hashes[2] = { 0, 0 }; 628 struct ifmultiaddr *ifma; 629 u_int32_t rxfilt; 630 int mcnt = 0; 631 632 ifp = &sc->arpcom.ac_if; 633 634 rxfilt = CSR_READ_4(sc, WB_NETCFG); 635 636 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 637 rxfilt |= WB_NETCFG_RX_MULTI; 638 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 639 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 640 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 641 return; 642 } 643 644 /* first, zot all the existing hash bits */ 645 CSR_WRITE_4(sc, WB_MAR0, 0); 646 CSR_WRITE_4(sc, WB_MAR1, 0); 647 648 /* now program new ones */ 649 for (ifma = ifp->if_multiaddrs.lh_first; ifma != NULL; 650 ifma = ifma->ifma_link.le_next) { 651 if (ifma->ifma_addr->sa_family != AF_LINK) 652 continue; 653 h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 654 if (h < 32) 655 hashes[0] |= (1 << h); 656 else 657 hashes[1] |= (1 << (h - 32)); 658 mcnt++; 659 } 660 661 if (mcnt) 662 rxfilt |= WB_NETCFG_RX_MULTI; 663 else 664 rxfilt &= ~WB_NETCFG_RX_MULTI; 665 666 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 667 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 668 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 669 670 return; 671} 672 673/* 674 * The Winbond manual states that in order to fiddle with the 675 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 676 * first have to put the transmit and/or receive logic in the idle state. 677 */ 678static void wb_setcfg(sc, media) 679 struct wb_softc *sc; 680 u_int32_t media; 681{ 682 int i, restart = 0; 683 684 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 685 restart = 1; 686 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 687 688 for (i = 0; i < WB_TIMEOUT; i++) { 689 DELAY(10); 690 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 691 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 692 break; 693 } 694 695 if (i == WB_TIMEOUT) 696 printf("wb%d: failed to force tx and " 697 "rx to idle state\n", sc->wb_unit); 698 } 699 700 if (IFM_SUBTYPE(media) == IFM_10_T) 701 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 702 else 703 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 704 705 if ((media & IFM_GMASK) == IFM_FDX) 706 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 707 else 708 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 709 710 if (restart) 711 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 712 713 return; 714} 715 716static void wb_reset(sc) 717 struct wb_softc *sc; 718{ 719 register int i; 720 struct mii_data *mii; 721 722 CSR_WRITE_4(sc, WB_NETCFG, 0); 723 CSR_WRITE_4(sc, WB_BUSCTL, 0); 724 CSR_WRITE_4(sc, WB_TXADDR, 0); 725 CSR_WRITE_4(sc, WB_RXADDR, 0); 726 727 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 728 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 729 730 for (i = 0; i < WB_TIMEOUT; i++) { 731 DELAY(10); 732 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 733 break; 734 } 735 if (i == WB_TIMEOUT) 736 printf("wb%d: reset never completed!\n", sc->wb_unit); 737 738 /* Wait a little while for the chip to get its brains in order. */ 739 DELAY(1000); 740 741 if (sc->wb_miibus == NULL) 742 return; 743 744 mii = device_get_softc(sc->wb_miibus); 745 if (mii == NULL) 746 return; 747 748 if (mii->mii_instance) { 749 struct mii_softc *miisc; 750 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 751 miisc = LIST_NEXT(miisc, mii_list)) 752 mii_phy_reset(miisc); 753 } 754 755 return; 756} 757 758static void wb_fixmedia(sc) 759 struct wb_softc *sc; 760{ 761 struct mii_data *mii = NULL; 762 struct ifnet *ifp; 763 u_int32_t media; 764 765 if (sc->wb_miibus == NULL) 766 return; 767 768 mii = device_get_softc(sc->wb_miibus); 769 ifp = &sc->arpcom.ac_if; 770 771 mii_pollstat(mii); 772 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 773 media = mii->mii_media_active & ~IFM_10_T; 774 media |= IFM_100_TX; 775 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 776 media = mii->mii_media_active & ~IFM_100_TX; 777 media |= IFM_10_T; 778 } else 779 return; 780 781 ifmedia_set(&mii->mii_media, media); 782 783 return; 784} 785 786/* 787 * Probe for a Winbond chip. Check the PCI vendor and device 788 * IDs against our list and return a device name if we find a match. 789 */ 790static int wb_probe(dev) 791 device_t dev; 792{ 793 struct wb_type *t; 794 795 t = wb_devs; 796 797 while(t->wb_name != NULL) { 798 if ((pci_get_vendor(dev) == t->wb_vid) && 799 (pci_get_device(dev) == t->wb_did)) { 800 device_set_desc(dev, t->wb_name); 801 return(0); 802 } 803 t++; 804 } 805 806 return(ENXIO); 807} 808 809/* 810 * Attach the interface. Allocate softc structures, do ifmedia 811 * setup and ethernet/BPF attach. 812 */ 813static int wb_attach(dev) 814 device_t dev; 815{ 816 int s; 817 u_char eaddr[ETHER_ADDR_LEN]; 818 u_int32_t command; 819 struct wb_softc *sc; 820 struct ifnet *ifp; 821 int unit, error = 0, rid; 822 823 s = splimp(); 824 825 sc = device_get_softc(dev); 826 unit = device_get_unit(dev); 827 828 /* 829 * Handle power management nonsense. 830 */ 831 832 command = pci_read_config(dev, WB_PCI_CAPID, 4) & 0x000000FF; 833 if (command == 0x01) { 834 835 command = pci_read_config(dev, WB_PCI_PWRMGMTCTRL, 4); 836 if (command & WB_PSTATE_MASK) { 837 u_int32_t iobase, membase, irq; 838 839 /* Save important PCI config data. */ 840 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 841 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 842 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 843 844 /* Reset the power state. */ 845 printf("wb%d: chip is in D%d power mode " 846 "-- setting to D0\n", unit, command & WB_PSTATE_MASK); 847 command &= 0xFFFFFFFC; 848 pci_write_config(dev, WB_PCI_PWRMGMTCTRL, command, 4); 849 850 /* Restore PCI config data. */ 851 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 852 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 853 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 854 } 855 } 856 857 /* 858 * Map control/status registers. 859 */ 860 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 861 command |= (PCIM_CMD_PORTEN|PCIM_CMD_MEMEN|PCIM_CMD_BUSMASTEREN); 862 pci_write_config(dev, PCI_COMMAND_STATUS_REG, command, 4); 863 command = pci_read_config(dev, PCI_COMMAND_STATUS_REG, 4); 864 865#ifdef WB_USEIOSPACE 866 if (!(command & PCIM_CMD_PORTEN)) { 867 printf("wb%d: failed to enable I/O ports!\n", unit); 868 error = ENXIO; 869 goto fail; 870 } 871#else 872 if (!(command & PCIM_CMD_MEMEN)) { 873 printf("wb%d: failed to enable memory mapping!\n", unit); 874 error = ENXIO; 875 goto fail; 876 } 877#endif 878 879 rid = WB_RID; 880 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 881 0, ~0, 1, RF_ACTIVE); 882 883 if (sc->wb_res == NULL) { 884 printf("wb%d: couldn't map ports/memory\n", unit); 885 error = ENXIO; 886 goto fail; 887 } 888 889 sc->wb_btag = rman_get_bustag(sc->wb_res); 890 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 891 892 /* Allocate interrupt */ 893 rid = 0; 894 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 895 RF_SHAREABLE | RF_ACTIVE); 896 897 if (sc->wb_irq == NULL) { 898 printf("wb%d: couldn't map interrupt\n", unit); 899 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 900 error = ENXIO; 901 goto fail; 902 } 903 904 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 905 wb_intr, sc, &sc->wb_intrhand); 906 907 if (error) { 908 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 909 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 910 printf("wb%d: couldn't set up irq\n", unit); 911 goto fail; 912 } 913 914 /* Save the cache line size. */ 915 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 916 917 /* Reset the adapter. */ 918 wb_reset(sc); 919 920 /* 921 * Get station address from the EEPROM. 922 */ 923 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 924 925 /* 926 * A Winbond chip was detected. Inform the world. 927 */ 928 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 929 930 sc->wb_unit = unit; 931 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 932 933 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 934 M_NOWAIT, 0x100000, 0xffffffff, PAGE_SIZE, 0); 935 936 if (sc->wb_ldata == NULL) { 937 printf("wb%d: no memory for list buffers!\n", unit); 938 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 939 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 940 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 941 error = ENXIO; 942 goto fail; 943 } 944 945 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 946 947 ifp = &sc->arpcom.ac_if; 948 ifp->if_softc = sc; 949 ifp->if_unit = unit; 950 ifp->if_name = "wb"; 951 ifp->if_mtu = ETHERMTU; 952 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 953 ifp->if_ioctl = wb_ioctl; 954 ifp->if_output = ether_output; 955 ifp->if_start = wb_start; 956 ifp->if_watchdog = wb_watchdog; 957 ifp->if_init = wb_init; 958 ifp->if_baudrate = 10000000; 959 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 960 961 /* 962 * Do MII setup. 963 */ 964 if (mii_phy_probe(dev, &sc->wb_miibus, 965 wb_ifmedia_upd, wb_ifmedia_sts)) { 966 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 967 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 968 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 969 free(sc->wb_ldata_ptr, M_DEVBUF); 970 error = ENXIO; 971 goto fail; 972 } 973 974 /* 975 * Call MI attach routines. 976 */ 977 if_attach(ifp); 978 ether_ifattach(ifp); 979 980#if NBPF > 0 981 bpfattach(ifp, DLT_EN10MB, sizeof(struct ether_header)); 982#endif 983 984fail: 985 if (error) 986 device_delete_child(dev, sc->wb_miibus); 987 splx(s); 988 989 return(error); 990} 991 992static int wb_detach(dev) 993 device_t dev; 994{ 995 struct wb_softc *sc; 996 struct ifnet *ifp; 997 int s; 998 999 s = splimp(); 1000 1001 sc = device_get_softc(dev); 1002 ifp = &sc->arpcom.ac_if; 1003 1004 wb_stop(sc); 1005 if_detach(ifp); 1006 1007 /* Delete any miibus and phy devices attached to this interface */ 1008 bus_generic_detach(dev); 1009 device_delete_child(dev, sc->wb_miibus); 1010 1011 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 1012 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 1013 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 1014 1015 free(sc->wb_ldata_ptr, M_DEVBUF); 1016 1017 splx(s); 1018 1019 return(0); 1020} 1021 1022/* 1023 * Initialize the transmit descriptors. 1024 */ 1025static int wb_list_tx_init(sc) 1026 struct wb_softc *sc; 1027{ 1028 struct wb_chain_data *cd; 1029 struct wb_list_data *ld; 1030 int i; 1031 1032 cd = &sc->wb_cdata; 1033 ld = sc->wb_ldata; 1034 1035 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1036 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1037 if (i == (WB_TX_LIST_CNT - 1)) { 1038 cd->wb_tx_chain[i].wb_nextdesc = 1039 &cd->wb_tx_chain[0]; 1040 } else { 1041 cd->wb_tx_chain[i].wb_nextdesc = 1042 &cd->wb_tx_chain[i + 1]; 1043 } 1044 } 1045 1046 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1047 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1048 1049 return(0); 1050} 1051 1052 1053/* 1054 * Initialize the RX descriptors and allocate mbufs for them. Note that 1055 * we arrange the descriptors in a closed ring, so that the last descriptor 1056 * points back to the first. 1057 */ 1058static int wb_list_rx_init(sc) 1059 struct wb_softc *sc; 1060{ 1061 struct wb_chain_data *cd; 1062 struct wb_list_data *ld; 1063 int i; 1064 1065 cd = &sc->wb_cdata; 1066 ld = sc->wb_ldata; 1067 1068 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1069 cd->wb_rx_chain[i].wb_ptr = 1070 (struct wb_desc *)&ld->wb_rx_list[i]; 1071 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1072 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1073 return(ENOBUFS); 1074 if (i == (WB_RX_LIST_CNT - 1)) { 1075 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1076 ld->wb_rx_list[i].wb_next = 1077 vtophys(&ld->wb_rx_list[0]); 1078 } else { 1079 cd->wb_rx_chain[i].wb_nextdesc = 1080 &cd->wb_rx_chain[i + 1]; 1081 ld->wb_rx_list[i].wb_next = 1082 vtophys(&ld->wb_rx_list[i + 1]); 1083 } 1084 } 1085 1086 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1087 1088 return(0); 1089} 1090 1091static void wb_bfree(buf, size) 1092 caddr_t buf; 1093 u_int size; 1094{ 1095 return; 1096} 1097 1098/* 1099 * Initialize an RX descriptor and attach an MBUF cluster. 1100 */ 1101static int wb_newbuf(sc, c, m) 1102 struct wb_softc *sc; 1103 struct wb_chain_onefrag *c; 1104 struct mbuf *m; 1105{ 1106 struct mbuf *m_new = NULL; 1107 1108 if (m == NULL) { 1109 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1110 if (m_new == NULL) { 1111 printf("wb%d: no memory for rx " 1112 "list -- packet dropped!\n", sc->wb_unit); 1113 return(ENOBUFS); 1114 } 1115 1116 m_new->m_data = m_new->m_ext.ext_buf = c->wb_buf; 1117 m_new->m_flags |= M_EXT; 1118 m_new->m_ext.ext_size = m_new->m_pkthdr.len = 1119 m_new->m_len = WB_BUFBYTES; 1120 m_new->m_ext.ext_free = wb_bfree; 1121 m_new->m_ext.ext_ref = wb_bfree; 1122 } else { 1123 m_new = m; 1124 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1125 m_new->m_data = m_new->m_ext.ext_buf; 1126 } 1127 1128 m_adj(m_new, sizeof(u_int64_t)); 1129 1130 c->wb_mbuf = m_new; 1131 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1132 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1133 c->wb_ptr->wb_status = WB_RXSTAT; 1134 1135 return(0); 1136} 1137 1138/* 1139 * A frame has been uploaded: pass the resulting mbuf chain up to 1140 * the higher level protocols. 1141 */ 1142static void wb_rxeof(sc) 1143 struct wb_softc *sc; 1144{ 1145 struct ether_header *eh; 1146 struct mbuf *m = NULL; 1147 struct ifnet *ifp; 1148 struct wb_chain_onefrag *cur_rx; 1149 int total_len = 0; 1150 u_int32_t rxstat; 1151 1152 ifp = &sc->arpcom.ac_if; 1153 1154 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1155 WB_RXSTAT_OWN)) { 1156 struct mbuf *m0 = NULL; 1157 1158 cur_rx = sc->wb_cdata.wb_rx_head; 1159 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1160 1161 m = cur_rx->wb_mbuf; 1162 1163 if ((rxstat & WB_RXSTAT_MIIERR) || 1164 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1165 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1166 !(rxstat & WB_RXSTAT_LASTFRAG) || 1167 !(rxstat & WB_RXSTAT_RXCMP)) { 1168 ifp->if_ierrors++; 1169 wb_newbuf(sc, cur_rx, m); 1170 printf("wb%x: receiver babbling: possible chip " 1171 "bug, forcing reset\n", sc->wb_unit); 1172 wb_fixmedia(sc); 1173 wb_reset(sc); 1174 wb_init(sc); 1175 return; 1176 } 1177 1178 if (rxstat & WB_RXSTAT_RXERR) { 1179 ifp->if_ierrors++; 1180 wb_newbuf(sc, cur_rx, m); 1181 break; 1182 } 1183 1184 /* No errors; receive the packet. */ 1185 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1186 1187 /* 1188 * XXX The Winbond chip includes the CRC with every 1189 * received frame, and there's no way to turn this 1190 * behavior off (at least, I can't find anything in 1191 * the manual that explains how to do it) so we have 1192 * to trim off the CRC manually. 1193 */ 1194 total_len -= ETHER_CRC_LEN; 1195 1196 m0 = m_devget(mtod(m, char *) - ETHER_ALIGN, 1197 total_len + ETHER_ALIGN, 0, ifp, NULL); 1198 wb_newbuf(sc, cur_rx, m); 1199 if (m0 == NULL) { 1200 ifp->if_ierrors++; 1201 break; 1202 } 1203 m_adj(m0, ETHER_ALIGN); 1204 m = m0; 1205 1206 ifp->if_ipackets++; 1207 eh = mtod(m, struct ether_header *); 1208 1209#ifdef BRIDGE 1210 if (do_bridge) { 1211 struct ifnet *bdg_ifp; 1212 bdg_ifp = bridge_in(m); 1213 if (bdg_ifp != BDG_LOCAL && bdg_ifp != BDG_DROP) 1214 bdg_forward(&m, bdg_ifp); 1215 if (((bdg_ifp != BDG_LOCAL) && (bdg_ifp != BDG_BCAST) && 1216 (bdg_ifp != BDG_MCAST)) || bdg_ifp == BDG_DROP) { 1217 m_freem(m); 1218 break; 1219 } 1220 } 1221#endif 1222 1223#if NBPF > 0 1224 /* 1225 * Handle BPF listeners. Let the BPF user see the packet, but 1226 * don't pass it up to the ether_input() layer unless it's 1227 * a broadcast packet, multicast packet, matches our ethernet 1228 * address or the interface is in promiscuous mode. 1229 */ 1230 if (ifp->if_bpf) { 1231 bpf_mtap(ifp, m); 1232 if (ifp->if_flags & IFF_PROMISC && 1233 (bcmp(eh->ether_dhost, sc->arpcom.ac_enaddr, 1234 ETHER_ADDR_LEN) && 1235 (eh->ether_dhost[0] & 1) == 0)) { 1236 m_freem(m); 1237 break; 1238 } 1239 } 1240#endif 1241 /* Remove header from mbuf and pass it on. */ 1242 m_adj(m, sizeof(struct ether_header)); 1243 ether_input(ifp, eh, m); 1244 } 1245 1246 return; 1247} 1248 1249void wb_rxeoc(sc) 1250 struct wb_softc *sc; 1251{ 1252 wb_rxeof(sc); 1253 1254 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1255 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1256 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1257 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1258 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1259 1260 return; 1261} 1262 1263/* 1264 * A frame was downloaded to the chip. It's safe for us to clean up 1265 * the list buffers. 1266 */ 1267static void wb_txeof(sc) 1268 struct wb_softc *sc; 1269{ 1270 struct wb_chain *cur_tx; 1271 struct ifnet *ifp; 1272 1273 ifp = &sc->arpcom.ac_if; 1274 1275 /* Clear the timeout timer. */ 1276 ifp->if_timer = 0; 1277 1278 if (sc->wb_cdata.wb_tx_head == NULL) 1279 return; 1280 1281 /* 1282 * Go through our tx list and free mbufs for those 1283 * frames that have been transmitted. 1284 */ 1285 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1286 u_int32_t txstat; 1287 1288 cur_tx = sc->wb_cdata.wb_tx_head; 1289 txstat = WB_TXSTATUS(cur_tx); 1290 1291 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1292 break; 1293 1294 if (txstat & WB_TXSTAT_TXERR) { 1295 ifp->if_oerrors++; 1296 if (txstat & WB_TXSTAT_ABORT) 1297 ifp->if_collisions++; 1298 if (txstat & WB_TXSTAT_LATECOLL) 1299 ifp->if_collisions++; 1300 } 1301 1302 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1303 1304 ifp->if_opackets++; 1305 m_freem(cur_tx->wb_mbuf); 1306 cur_tx->wb_mbuf = NULL; 1307 1308 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1309 sc->wb_cdata.wb_tx_head = NULL; 1310 sc->wb_cdata.wb_tx_tail = NULL; 1311 break; 1312 } 1313 1314 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1315 } 1316 1317 return; 1318} 1319 1320/* 1321 * TX 'end of channel' interrupt handler. 1322 */ 1323static void wb_txeoc(sc) 1324 struct wb_softc *sc; 1325{ 1326 struct ifnet *ifp; 1327 1328 ifp = &sc->arpcom.ac_if; 1329 1330 ifp->if_timer = 0; 1331 1332 if (sc->wb_cdata.wb_tx_head == NULL) { 1333 ifp->if_flags &= ~IFF_OACTIVE; 1334 sc->wb_cdata.wb_tx_tail = NULL; 1335 } else { 1336 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1337 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1338 ifp->if_timer = 5; 1339 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1340 } 1341 } 1342 1343 return; 1344} 1345 1346static void wb_intr(arg) 1347 void *arg; 1348{ 1349 struct wb_softc *sc; 1350 struct ifnet *ifp; 1351 u_int32_t status; 1352 1353 sc = arg; 1354 ifp = &sc->arpcom.ac_if; 1355 1356 if (!(ifp->if_flags & IFF_UP)) 1357 return; 1358 1359 /* Disable interrupts. */ 1360 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1361 1362 for (;;) { 1363 1364 status = CSR_READ_4(sc, WB_ISR); 1365 if (status) 1366 CSR_WRITE_4(sc, WB_ISR, status); 1367 1368 if ((status & WB_INTRS) == 0) 1369 break; 1370 1371 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1372 ifp->if_ierrors++; 1373 wb_reset(sc); 1374 if (status & WB_ISR_RX_ERR) 1375 wb_fixmedia(sc); 1376 wb_init(sc); 1377 continue; 1378 } 1379 1380 if (status & WB_ISR_RX_OK) 1381 wb_rxeof(sc); 1382 1383 if (status & WB_ISR_RX_IDLE) 1384 wb_rxeoc(sc); 1385 1386 if (status & WB_ISR_TX_OK) 1387 wb_txeof(sc); 1388 1389 if (status & WB_ISR_TX_NOBUF) 1390 wb_txeoc(sc); 1391 1392 if (status & WB_ISR_TX_IDLE) { 1393 wb_txeof(sc); 1394 if (sc->wb_cdata.wb_tx_head != NULL) { 1395 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1396 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1397 } 1398 } 1399 1400 if (status & WB_ISR_TX_UNDERRUN) { 1401 ifp->if_oerrors++; 1402 wb_txeof(sc); 1403 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1404 /* Jack up TX threshold */ 1405 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1406 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1407 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1408 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1409 } 1410 1411 if (status & WB_ISR_BUS_ERR) { 1412 wb_reset(sc); 1413 wb_init(sc); 1414 } 1415 1416 } 1417 1418 /* Re-enable interrupts. */ 1419 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1420 1421 if (ifp->if_snd.ifq_head != NULL) { 1422 wb_start(ifp); 1423 } 1424 1425 return; 1426} 1427 1428static void wb_tick(xsc) 1429 void *xsc; 1430{ 1431 struct wb_softc *sc; 1432 struct mii_data *mii; 1433 int s; 1434 1435 s = splimp(); 1436 1437 sc = xsc; 1438 mii = device_get_softc(sc->wb_miibus); 1439 1440 mii_tick(mii); 1441 1442 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1443 1444 splx(s); 1445 1446 return; 1447} 1448 1449/* 1450 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1451 * pointers to the fragment pointers. 1452 */ 1453static int wb_encap(sc, c, m_head) 1454 struct wb_softc *sc; 1455 struct wb_chain *c; 1456 struct mbuf *m_head; 1457{ 1458 int frag = 0; 1459 struct wb_desc *f = NULL; 1460 int total_len; 1461 struct mbuf *m; 1462 1463 /* 1464 * Start packing the mbufs in this chain into 1465 * the fragment pointers. Stop when we run out 1466 * of fragments or hit the end of the mbuf chain. 1467 */ 1468 m = m_head; 1469 total_len = 0; 1470 1471 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1472 if (m->m_len != 0) { 1473 if (frag == WB_MAXFRAGS) 1474 break; 1475 total_len += m->m_len; 1476 f = &c->wb_ptr->wb_frag[frag]; 1477 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1478 if (frag == 0) { 1479 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1480 f->wb_status = 0; 1481 } else 1482 f->wb_status = WB_TXSTAT_OWN; 1483 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1484 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1485 frag++; 1486 } 1487 } 1488 1489 /* 1490 * Handle special case: we used up all 16 fragments, 1491 * but we have more mbufs left in the chain. Copy the 1492 * data into an mbuf cluster. Note that we don't 1493 * bother clearing the values in the other fragment 1494 * pointers/counters; it wouldn't gain us anything, 1495 * and would waste cycles. 1496 */ 1497 if (m != NULL) { 1498 struct mbuf *m_new = NULL; 1499 1500 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1501 if (m_new == NULL) { 1502 printf("wb%d: no memory for tx list", sc->wb_unit); 1503 return(1); 1504 } 1505 if (m_head->m_pkthdr.len > MHLEN) { 1506 MCLGET(m_new, M_DONTWAIT); 1507 if (!(m_new->m_flags & M_EXT)) { 1508 m_freem(m_new); 1509 printf("wb%d: no memory for tx list", 1510 sc->wb_unit); 1511 return(1); 1512 } 1513 } 1514 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1515 mtod(m_new, caddr_t)); 1516 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1517 m_freem(m_head); 1518 m_head = m_new; 1519 f = &c->wb_ptr->wb_frag[0]; 1520 f->wb_status = 0; 1521 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1522 f->wb_ctl = total_len = m_new->m_len; 1523 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1524 frag = 1; 1525 } 1526 1527 if (total_len < WB_MIN_FRAMELEN) { 1528 f = &c->wb_ptr->wb_frag[frag]; 1529 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1530 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1531 f->wb_ctl |= WB_TXCTL_TLINK; 1532 f->wb_status = WB_TXSTAT_OWN; 1533 frag++; 1534 } 1535 1536 c->wb_mbuf = m_head; 1537 c->wb_lastdesc = frag - 1; 1538 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1539 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1540 1541 return(0); 1542} 1543 1544/* 1545 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1546 * to the mbuf data regions directly in the transmit lists. We also save a 1547 * copy of the pointers since the transmit list fragment pointers are 1548 * physical addresses. 1549 */ 1550 1551static void wb_start(ifp) 1552 struct ifnet *ifp; 1553{ 1554 struct wb_softc *sc; 1555 struct mbuf *m_head = NULL; 1556 struct wb_chain *cur_tx = NULL, *start_tx; 1557 1558 sc = ifp->if_softc; 1559 1560 /* 1561 * Check for an available queue slot. If there are none, 1562 * punt. 1563 */ 1564 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1565 ifp->if_flags |= IFF_OACTIVE; 1566 return; 1567 } 1568 1569 start_tx = sc->wb_cdata.wb_tx_free; 1570 1571 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1572 IF_DEQUEUE(&ifp->if_snd, m_head); 1573 if (m_head == NULL) 1574 break; 1575 1576 /* Pick a descriptor off the free list. */ 1577 cur_tx = sc->wb_cdata.wb_tx_free; 1578 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1579 1580 /* Pack the data into the descriptor. */ 1581 wb_encap(sc, cur_tx, m_head); 1582 1583 if (cur_tx != start_tx) 1584 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1585 1586#if NBPF > 0 1587 /* 1588 * If there's a BPF listener, bounce a copy of this frame 1589 * to him. 1590 */ 1591 if (ifp->if_bpf) 1592 bpf_mtap(ifp, cur_tx->wb_mbuf); 1593#endif 1594 } 1595 1596 /* 1597 * If there are no packets queued, bail. 1598 */ 1599 if (cur_tx == NULL) 1600 return; 1601 1602 /* 1603 * Place the request for the upload interrupt 1604 * in the last descriptor in the chain. This way, if 1605 * we're chaining several packets at once, we'll only 1606 * get an interupt once for the whole chain rather than 1607 * once for each packet. 1608 */ 1609 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1610 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1611 sc->wb_cdata.wb_tx_tail = cur_tx; 1612 1613 if (sc->wb_cdata.wb_tx_head == NULL) { 1614 sc->wb_cdata.wb_tx_head = start_tx; 1615 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1616 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1617 } else { 1618 /* 1619 * We need to distinguish between the case where 1620 * the own bit is clear because the chip cleared it 1621 * and where the own bit is clear because we haven't 1622 * set it yet. The magic value WB_UNSET is just some 1623 * ramdomly chosen number which doesn't have the own 1624 * bit set. When we actually transmit the frame, the 1625 * status word will have _only_ the own bit set, so 1626 * the txeoc handler will be able to tell if it needs 1627 * to initiate another transmission to flush out pending 1628 * frames. 1629 */ 1630 WB_TXOWN(start_tx) = WB_UNSENT; 1631 } 1632 1633 /* 1634 * Set a timeout in case the chip goes out to lunch. 1635 */ 1636 ifp->if_timer = 5; 1637 1638 return; 1639} 1640 1641static void wb_init(xsc) 1642 void *xsc; 1643{ 1644 struct wb_softc *sc = xsc; 1645 struct ifnet *ifp = &sc->arpcom.ac_if; 1646 int s, i; 1647 struct mii_data *mii; 1648 1649 s = splimp(); 1650 1651 mii = device_get_softc(sc->wb_miibus); 1652 1653 /* 1654 * Cancel pending I/O and free all RX/TX buffers. 1655 */ 1656 wb_stop(sc); 1657 wb_reset(sc); 1658 1659 sc->wb_txthresh = WB_TXTHRESH_INIT; 1660 1661 /* 1662 * Set cache alignment and burst length. 1663 */ 1664#ifdef foo 1665 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1666 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1667 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1668#endif 1669 1670 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1671 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1672 switch(sc->wb_cachesize) { 1673 case 32: 1674 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1675 break; 1676 case 16: 1677 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1678 break; 1679 case 8: 1680 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1681 break; 1682 case 0: 1683 default: 1684 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1685 break; 1686 } 1687 1688 /* This doesn't tend to work too well at 100Mbps. */ 1689 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1690 1691 /* Init our MAC address */ 1692 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1693 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1694 } 1695 1696 /* Init circular RX list. */ 1697 if (wb_list_rx_init(sc) == ENOBUFS) { 1698 printf("wb%d: initialization failed: no " 1699 "memory for rx buffers\n", sc->wb_unit); 1700 wb_stop(sc); 1701 (void)splx(s); 1702 return; 1703 } 1704 1705 /* Init TX descriptors. */ 1706 wb_list_tx_init(sc); 1707 1708 /* If we want promiscuous mode, set the allframes bit. */ 1709 if (ifp->if_flags & IFF_PROMISC) { 1710 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1711 } else { 1712 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1713 } 1714 1715 /* 1716 * Set capture broadcast bit to capture broadcast frames. 1717 */ 1718 if (ifp->if_flags & IFF_BROADCAST) { 1719 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1720 } else { 1721 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1722 } 1723 1724 /* 1725 * Program the multicast filter, if necessary. 1726 */ 1727 wb_setmulti(sc); 1728 1729 /* 1730 * Load the address of the RX list. 1731 */ 1732 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1733 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1734 1735 /* 1736 * Enable interrupts. 1737 */ 1738 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1739 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1740 1741 /* Enable receiver and transmitter. */ 1742 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1743 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1744 1745 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1746 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1747 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1748 1749 mii_mediachg(mii); 1750 1751 ifp->if_flags |= IFF_RUNNING; 1752 ifp->if_flags &= ~IFF_OACTIVE; 1753 1754 (void)splx(s); 1755 1756 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1757 1758 return; 1759} 1760 1761/* 1762 * Set media options. 1763 */ 1764static int wb_ifmedia_upd(ifp) 1765 struct ifnet *ifp; 1766{ 1767 struct wb_softc *sc; 1768 1769 sc = ifp->if_softc; 1770 1771 if (ifp->if_flags & IFF_UP) 1772 wb_init(sc); 1773 1774 return(0); 1775} 1776 1777/* 1778 * Report current media status. 1779 */ 1780static void wb_ifmedia_sts(ifp, ifmr) 1781 struct ifnet *ifp; 1782 struct ifmediareq *ifmr; 1783{ 1784 struct wb_softc *sc; 1785 struct mii_data *mii; 1786 1787 sc = ifp->if_softc; 1788 1789 mii = device_get_softc(sc->wb_miibus); 1790 1791 mii_pollstat(mii); 1792 ifmr->ifm_active = mii->mii_media_active; 1793 ifmr->ifm_status = mii->mii_media_status; 1794 1795 return; 1796} 1797 1798static int wb_ioctl(ifp, command, data) 1799 struct ifnet *ifp; 1800 u_long command; 1801 caddr_t data; 1802{ 1803 struct wb_softc *sc = ifp->if_softc; 1804 struct mii_data *mii; 1805 struct ifreq *ifr = (struct ifreq *) data; 1806 int s, error = 0; 1807 1808 s = splimp(); 1809 1810 switch(command) { 1811 case SIOCSIFADDR: 1812 case SIOCGIFADDR: 1813 case SIOCSIFMTU: 1814 error = ether_ioctl(ifp, command, data); 1815 break; 1816 case SIOCSIFFLAGS: 1817 if (ifp->if_flags & IFF_UP) { 1818 wb_init(sc); 1819 } else { 1820 if (ifp->if_flags & IFF_RUNNING) 1821 wb_stop(sc); 1822 } 1823 error = 0; 1824 break; 1825 case SIOCADDMULTI: 1826 case SIOCDELMULTI: 1827 wb_setmulti(sc); 1828 error = 0; 1829 break; 1830 case SIOCGIFMEDIA: 1831 case SIOCSIFMEDIA: 1832 mii = device_get_softc(sc->wb_miibus); 1833 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1834 break; 1835 default: 1836 error = EINVAL; 1837 break; 1838 } 1839 1840 (void)splx(s); 1841 1842 return(error); 1843} 1844 1845static void wb_watchdog(ifp) 1846 struct ifnet *ifp; 1847{ 1848 struct wb_softc *sc; 1849 1850 sc = ifp->if_softc; 1851 1852 ifp->if_oerrors++; 1853 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1854#ifdef foo 1855 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1856 printf("wb%d: no carrier - transceiver cable problem?\n", 1857 sc->wb_unit); 1858#endif 1859 wb_stop(sc); 1860 wb_reset(sc); 1861 wb_init(sc); 1862 1863 if (ifp->if_snd.ifq_head != NULL) 1864 wb_start(ifp); 1865 1866 return; 1867} 1868 1869/* 1870 * Stop the adapter and free any mbufs allocated to the 1871 * RX and TX lists. 1872 */ 1873static void wb_stop(sc) 1874 struct wb_softc *sc; 1875{ 1876 register int i; 1877 struct ifnet *ifp; 1878 1879 ifp = &sc->arpcom.ac_if; 1880 ifp->if_timer = 0; 1881 1882 untimeout(wb_tick, sc, sc->wb_stat_ch); 1883 1884 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1885 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1886 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1887 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1888 1889 /* 1890 * Free data in the RX lists. 1891 */ 1892 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1893 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1894 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1895 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1896 } 1897 } 1898 bzero((char *)&sc->wb_ldata->wb_rx_list, 1899 sizeof(sc->wb_ldata->wb_rx_list)); 1900 1901 /* 1902 * Free the TX list buffers. 1903 */ 1904 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1905 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1906 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1907 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1908 } 1909 } 1910 1911 bzero((char *)&sc->wb_ldata->wb_tx_list, 1912 sizeof(sc->wb_ldata->wb_tx_list)); 1913 1914 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1915 1916 return; 1917} 1918 1919/* 1920 * Stop all chip I/O so that the kernel's probe routines don't 1921 * get confused by errant DMAs when rebooting. 1922 */ 1923static void wb_shutdown(dev) 1924 device_t dev; 1925{ 1926 struct wb_softc *sc; 1927 1928 sc = device_get_softc(dev); 1929 wb_stop(sc); 1930 1931 return; 1932} 1933