if_wb.c revision 149677
1139825Simp/*- 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 149677 2005-08-31 18:03:18Z jhb $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * Winbond fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 4041502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4141502Swpaul * Winbond itself and some made by Linksys. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8648745Swpaul#include "opt_bdg.h" 8741502Swpaul 8841502Swpaul#include <sys/param.h> 8941502Swpaul#include <sys/systm.h> 9041502Swpaul#include <sys/sockio.h> 9141502Swpaul#include <sys/mbuf.h> 9241502Swpaul#include <sys/malloc.h> 93129878Sphk#include <sys/module.h> 9441502Swpaul#include <sys/kernel.h> 9541502Swpaul#include <sys/socket.h> 9650675Swpaul#include <sys/queue.h> 9741502Swpaul 9841502Swpaul#include <net/if.h> 9941502Swpaul#include <net/if_arp.h> 10041502Swpaul#include <net/ethernet.h> 10141502Swpaul#include <net/if_dl.h> 10241502Swpaul#include <net/if_media.h> 103147256Sbrooks#include <net/if_types.h> 10441502Swpaul 10541502Swpaul#include <net/bpf.h> 10641502Swpaul 10741502Swpaul#include <vm/vm.h> /* for vtophys */ 10841502Swpaul#include <vm/pmap.h> /* for vtophys */ 10941502Swpaul#include <machine/bus.h> 11049611Swpaul#include <machine/resource.h> 11149611Swpaul#include <sys/bus.h> 11249611Swpaul#include <sys/rman.h> 11341502Swpaul 114119288Simp#include <dev/pci/pcireg.h> 115119288Simp#include <dev/pci/pcivar.h> 11641502Swpaul 11750675Swpaul#include <dev/mii/mii.h> 11850675Swpaul#include <dev/mii/miivar.h> 11950675Swpaul 12051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12150675Swpaul#include "miibus_if.h" 12250675Swpaul 12341502Swpaul#define WB_USEIOSPACE 12441502Swpaul 12541502Swpaul#include <pci/if_wbreg.h> 12641502Swpaul 127113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 128113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 12959758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 13059758Speter 13141502Swpaul/* 13241502Swpaul * Various supported device vendors/types and their names. 13341502Swpaul */ 13441502Swpaulstatic struct wb_type wb_devs[] = { 13541502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13641502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13741502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13841502Swpaul "Compex RL100-ATX 10/100baseTX" }, 13941502Swpaul { 0, 0, NULL } 14041502Swpaul}; 14141502Swpaul 142142407Simpstatic int wb_probe(device_t); 143142407Simpstatic int wb_attach(device_t); 144142407Simpstatic int wb_detach(device_t); 14541502Swpaul 146142407Simpstatic void wb_bfree(void *addr, void *args); 147142407Simpstatic int wb_newbuf(struct wb_softc *, struct wb_chain_onefrag *, 148142407Simp struct mbuf *); 149142407Simpstatic int wb_encap(struct wb_softc *, struct wb_chain *, struct mbuf *); 15041502Swpaul 151142407Simpstatic void wb_rxeof(struct wb_softc *); 152142407Simpstatic void wb_rxeoc(struct wb_softc *); 153142407Simpstatic void wb_txeof(struct wb_softc *); 154142407Simpstatic void wb_txeoc(struct wb_softc *); 155142407Simpstatic void wb_intr(void *); 156142407Simpstatic void wb_tick(void *); 157142407Simpstatic void wb_start(struct ifnet *); 158142407Simpstatic int wb_ioctl(struct ifnet *, u_long, caddr_t); 159142407Simpstatic void wb_init(void *); 160142407Simpstatic void wb_stop(struct wb_softc *); 161142407Simpstatic void wb_watchdog(struct ifnet *); 162142407Simpstatic void wb_shutdown(device_t); 163142407Simpstatic int wb_ifmedia_upd(struct ifnet *); 164142407Simpstatic void wb_ifmedia_sts(struct ifnet *, struct ifmediareq *); 16541502Swpaul 166142407Simpstatic void wb_eeprom_putbyte(struct wb_softc *, int); 167142407Simpstatic void wb_eeprom_getword(struct wb_softc *, int, u_int16_t *); 168142407Simpstatic void wb_read_eeprom(struct wb_softc *, caddr_t, int, int, int); 169142407Simpstatic void wb_mii_sync(struct wb_softc *); 170142407Simpstatic void wb_mii_send(struct wb_softc *, u_int32_t, int); 171142407Simpstatic int wb_mii_readreg(struct wb_softc *, struct wb_mii_frame *); 172142407Simpstatic int wb_mii_writereg(struct wb_softc *, struct wb_mii_frame *); 17341502Swpaul 174142407Simpstatic void wb_setcfg(struct wb_softc *, u_int32_t); 175142407Simpstatic void wb_setmulti(struct wb_softc *); 176142407Simpstatic void wb_reset(struct wb_softc *); 177142407Simpstatic void wb_fixmedia(struct wb_softc *); 178142407Simpstatic int wb_list_rx_init(struct wb_softc *); 179142407Simpstatic int wb_list_tx_init(struct wb_softc *); 18041502Swpaul 181142407Simpstatic int wb_miibus_readreg(device_t, int, int); 182142407Simpstatic int wb_miibus_writereg(device_t, int, int, int); 183142407Simpstatic void wb_miibus_statchg(device_t); 18450675Swpaul 18549611Swpaul#ifdef WB_USEIOSPACE 18649611Swpaul#define WB_RES SYS_RES_IOPORT 18749611Swpaul#define WB_RID WB_PCI_LOIO 18849611Swpaul#else 18949611Swpaul#define WB_RES SYS_RES_MEMORY 19049611Swpaul#define WB_RID WB_PCI_LOMEM 19149611Swpaul#endif 19249611Swpaul 19349611Swpaulstatic device_method_t wb_methods[] = { 19449611Swpaul /* Device interface */ 19549611Swpaul DEVMETHOD(device_probe, wb_probe), 19649611Swpaul DEVMETHOD(device_attach, wb_attach), 19749611Swpaul DEVMETHOD(device_detach, wb_detach), 19849611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 19950675Swpaul 20050675Swpaul /* bus interface, for miibus */ 20150675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20250675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20350675Swpaul 20450675Swpaul /* MII interface */ 20550675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 20650675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 20750675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 20849611Swpaul { 0, 0 } 20949611Swpaul}; 21049611Swpaul 21149611Swpaulstatic driver_t wb_driver = { 21251455Swpaul "wb", 21349611Swpaul wb_methods, 21449611Swpaul sizeof(struct wb_softc) 21549611Swpaul}; 21649611Swpaul 21749611Swpaulstatic devclass_t wb_devclass; 21849611Swpaul 219113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22051473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22149611Swpaul 22241502Swpaul#define WB_SETBIT(sc, reg, x) \ 22341502Swpaul CSR_WRITE_4(sc, reg, \ 224105221Sphk CSR_READ_4(sc, reg) | (x)) 22541502Swpaul 22641502Swpaul#define WB_CLRBIT(sc, reg, x) \ 22741502Swpaul CSR_WRITE_4(sc, reg, \ 228105221Sphk CSR_READ_4(sc, reg) & ~(x)) 22941502Swpaul 23041502Swpaul#define SIO_SET(x) \ 23141502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 232105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23341502Swpaul 23441502Swpaul#define SIO_CLR(x) \ 23541502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 236105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 23741502Swpaul 23841502Swpaul/* 23941502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24041502Swpaul */ 241102336Salfredstatic void 242102336Salfredwb_eeprom_putbyte(sc, addr) 24341502Swpaul struct wb_softc *sc; 24442718Swpaul int addr; 24541502Swpaul{ 24641502Swpaul register int d, i; 24741502Swpaul 24841502Swpaul d = addr | WB_EECMD_READ; 24941502Swpaul 25041502Swpaul /* 25141502Swpaul * Feed in each bit and stobe the clock. 25241502Swpaul */ 25341502Swpaul for (i = 0x400; i; i >>= 1) { 25441502Swpaul if (d & i) { 25541502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 25641502Swpaul } else { 25741502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 25841502Swpaul } 25941502Swpaul DELAY(100); 26041502Swpaul SIO_SET(WB_SIO_EE_CLK); 26141502Swpaul DELAY(150); 26241502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26341502Swpaul DELAY(100); 26441502Swpaul } 26541502Swpaul 26641502Swpaul return; 26741502Swpaul} 26841502Swpaul 26941502Swpaul/* 27041502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27141502Swpaul */ 272102336Salfredstatic void 273102336Salfredwb_eeprom_getword(sc, addr, dest) 27441502Swpaul struct wb_softc *sc; 27542718Swpaul int addr; 27641502Swpaul u_int16_t *dest; 27741502Swpaul{ 27841502Swpaul register int i; 27941502Swpaul u_int16_t word = 0; 28041502Swpaul 28141502Swpaul /* Enter EEPROM access mode. */ 28241502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28341502Swpaul 28441502Swpaul /* 28541502Swpaul * Send address of word we want to read. 28641502Swpaul */ 28741502Swpaul wb_eeprom_putbyte(sc, addr); 28841502Swpaul 28941502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29041502Swpaul 29141502Swpaul /* 29241502Swpaul * Start reading bits from EEPROM. 29341502Swpaul */ 29441502Swpaul for (i = 0x8000; i; i >>= 1) { 29541502Swpaul SIO_SET(WB_SIO_EE_CLK); 29641502Swpaul DELAY(100); 29741502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 29841502Swpaul word |= i; 29941502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30041502Swpaul DELAY(100); 30141502Swpaul } 30241502Swpaul 30341502Swpaul /* Turn off EEPROM access mode. */ 30441502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30541502Swpaul 30641502Swpaul *dest = word; 30741502Swpaul 30841502Swpaul return; 30941502Swpaul} 31041502Swpaul 31141502Swpaul/* 31241502Swpaul * Read a sequence of words from the EEPROM. 31341502Swpaul */ 314102336Salfredstatic void 315102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 31641502Swpaul struct wb_softc *sc; 31741502Swpaul caddr_t dest; 31841502Swpaul int off; 31941502Swpaul int cnt; 32041502Swpaul int swap; 32141502Swpaul{ 32241502Swpaul int i; 32341502Swpaul u_int16_t word = 0, *ptr; 32441502Swpaul 32541502Swpaul for (i = 0; i < cnt; i++) { 32641502Swpaul wb_eeprom_getword(sc, off + i, &word); 32741502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 32841502Swpaul if (swap) 32941502Swpaul *ptr = ntohs(word); 33041502Swpaul else 33141502Swpaul *ptr = word; 33241502Swpaul } 33341502Swpaul 33441502Swpaul return; 33541502Swpaul} 33641502Swpaul 33741502Swpaul/* 33841502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 33941502Swpaul */ 340102336Salfredstatic void 341102336Salfredwb_mii_sync(sc) 34241502Swpaul struct wb_softc *sc; 34341502Swpaul{ 34441502Swpaul register int i; 34541502Swpaul 34641502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 34741502Swpaul 34841502Swpaul for (i = 0; i < 32; i++) { 34941502Swpaul SIO_SET(WB_SIO_MII_CLK); 35041502Swpaul DELAY(1); 35141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35241502Swpaul DELAY(1); 35341502Swpaul } 35441502Swpaul 35541502Swpaul return; 35641502Swpaul} 35741502Swpaul 35841502Swpaul/* 35941502Swpaul * Clock a series of bits through the MII. 36041502Swpaul */ 361102336Salfredstatic void 362102336Salfredwb_mii_send(sc, bits, cnt) 36341502Swpaul struct wb_softc *sc; 36441502Swpaul u_int32_t bits; 36541502Swpaul int cnt; 36641502Swpaul{ 36741502Swpaul int i; 36841502Swpaul 36941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37041502Swpaul 37141502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37241502Swpaul if (bits & i) { 37341502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37441502Swpaul } else { 37541502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37641502Swpaul } 37741502Swpaul DELAY(1); 37841502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37941502Swpaul DELAY(1); 38041502Swpaul SIO_SET(WB_SIO_MII_CLK); 38141502Swpaul } 38241502Swpaul} 38341502Swpaul 38441502Swpaul/* 38541502Swpaul * Read an PHY register through the MII. 38641502Swpaul */ 387102336Salfredstatic int 388102336Salfredwb_mii_readreg(sc, frame) 38941502Swpaul struct wb_softc *sc; 39041502Swpaul struct wb_mii_frame *frame; 39141502Swpaul 39241502Swpaul{ 39367087Swpaul int i, ack; 39441502Swpaul 39567087Swpaul WB_LOCK(sc); 39641502Swpaul 39741502Swpaul /* 39841502Swpaul * Set up frame for RX. 39941502Swpaul */ 40041502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40141502Swpaul frame->mii_opcode = WB_MII_READOP; 40241502Swpaul frame->mii_turnaround = 0; 40341502Swpaul frame->mii_data = 0; 40441502Swpaul 40541502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40641502Swpaul 40741502Swpaul /* 40841502Swpaul * Turn on data xmit. 40941502Swpaul */ 41041502Swpaul SIO_SET(WB_SIO_MII_DIR); 41141502Swpaul 41241502Swpaul wb_mii_sync(sc); 41341502Swpaul 41441502Swpaul /* 41541502Swpaul * Send command/address info. 41641502Swpaul */ 41741502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 41841502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 41941502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42041502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42141502Swpaul 42241502Swpaul /* Idle bit */ 42341502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42441502Swpaul DELAY(1); 42541502Swpaul SIO_SET(WB_SIO_MII_CLK); 42641502Swpaul DELAY(1); 42741502Swpaul 42841502Swpaul /* Turn off xmit. */ 42941502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43041502Swpaul /* Check for ack */ 43141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43241502Swpaul DELAY(1); 433109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43441502Swpaul SIO_SET(WB_SIO_MII_CLK); 43541502Swpaul DELAY(1); 43641502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43741502Swpaul DELAY(1); 43841502Swpaul SIO_SET(WB_SIO_MII_CLK); 43941502Swpaul DELAY(1); 44041502Swpaul 44141502Swpaul /* 44241502Swpaul * Now try reading data bits. If the ack failed, we still 44341502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44441502Swpaul */ 44541502Swpaul if (ack) { 44641502Swpaul for(i = 0; i < 16; i++) { 44741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44841502Swpaul DELAY(1); 44941502Swpaul SIO_SET(WB_SIO_MII_CLK); 45041502Swpaul DELAY(1); 45141502Swpaul } 45241502Swpaul goto fail; 45341502Swpaul } 45441502Swpaul 45541502Swpaul for (i = 0x8000; i; i >>= 1) { 45641502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45741502Swpaul DELAY(1); 45841502Swpaul if (!ack) { 45941502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46041502Swpaul frame->mii_data |= i; 46141502Swpaul DELAY(1); 46241502Swpaul } 46341502Swpaul SIO_SET(WB_SIO_MII_CLK); 46441502Swpaul DELAY(1); 46541502Swpaul } 46641502Swpaul 46741502Swpaulfail: 46841502Swpaul 46941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47041502Swpaul DELAY(1); 47141502Swpaul SIO_SET(WB_SIO_MII_CLK); 47241502Swpaul DELAY(1); 47341502Swpaul 47467087Swpaul WB_UNLOCK(sc); 47541502Swpaul 47641502Swpaul if (ack) 47741502Swpaul return(1); 47841502Swpaul return(0); 47941502Swpaul} 48041502Swpaul 48141502Swpaul/* 48241502Swpaul * Write to a PHY register through the MII. 48341502Swpaul */ 484102336Salfredstatic int 485102336Salfredwb_mii_writereg(sc, frame) 48641502Swpaul struct wb_softc *sc; 48741502Swpaul struct wb_mii_frame *frame; 48841502Swpaul 48941502Swpaul{ 49067087Swpaul WB_LOCK(sc); 49141502Swpaul 49241502Swpaul /* 49341502Swpaul * Set up frame for TX. 49441502Swpaul */ 49541502Swpaul 49641502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 49741502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 49841502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 49941502Swpaul 50041502Swpaul /* 50141502Swpaul * Turn on data output. 50241502Swpaul */ 50341502Swpaul SIO_SET(WB_SIO_MII_DIR); 50441502Swpaul 50541502Swpaul wb_mii_sync(sc); 50641502Swpaul 50741502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 50841502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 50941502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51041502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51141502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51341502Swpaul 51441502Swpaul /* Idle bit. */ 51541502Swpaul SIO_SET(WB_SIO_MII_CLK); 51641502Swpaul DELAY(1); 51741502Swpaul SIO_CLR(WB_SIO_MII_CLK); 51841502Swpaul DELAY(1); 51941502Swpaul 52041502Swpaul /* 52141502Swpaul * Turn off xmit. 52241502Swpaul */ 52341502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52441502Swpaul 52567087Swpaul WB_UNLOCK(sc); 52641502Swpaul 52741502Swpaul return(0); 52841502Swpaul} 52941502Swpaul 530102336Salfredstatic int 531102336Salfredwb_miibus_readreg(dev, phy, reg) 53250675Swpaul device_t dev; 53350675Swpaul int phy, reg; 53450675Swpaul{ 53541502Swpaul struct wb_softc *sc; 53641502Swpaul struct wb_mii_frame frame; 53741502Swpaul 53850675Swpaul sc = device_get_softc(dev); 53950675Swpaul 54041502Swpaul bzero((char *)&frame, sizeof(frame)); 54141502Swpaul 54250675Swpaul frame.mii_phyaddr = phy; 54341502Swpaul frame.mii_regaddr = reg; 54441502Swpaul wb_mii_readreg(sc, &frame); 54541502Swpaul 54641502Swpaul return(frame.mii_data); 54741502Swpaul} 54841502Swpaul 549102336Salfredstatic int 550102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55150675Swpaul device_t dev; 55250675Swpaul int phy, reg, data; 55350675Swpaul{ 55441502Swpaul struct wb_softc *sc; 55541502Swpaul struct wb_mii_frame frame; 55641502Swpaul 55750675Swpaul sc = device_get_softc(dev); 55850675Swpaul 55941502Swpaul bzero((char *)&frame, sizeof(frame)); 56041502Swpaul 56150675Swpaul frame.mii_phyaddr = phy; 56241502Swpaul frame.mii_regaddr = reg; 56341502Swpaul frame.mii_data = data; 56441502Swpaul 56541502Swpaul wb_mii_writereg(sc, &frame); 56641502Swpaul 56750675Swpaul return(0); 56850675Swpaul} 56950675Swpaul 570102336Salfredstatic void 571102336Salfredwb_miibus_statchg(dev) 57250675Swpaul device_t dev; 57350675Swpaul{ 57450675Swpaul struct wb_softc *sc; 57550675Swpaul struct mii_data *mii; 57650675Swpaul 57750675Swpaul sc = device_get_softc(dev); 57867087Swpaul WB_LOCK(sc); 57950675Swpaul mii = device_get_softc(sc->wb_miibus); 58050675Swpaul wb_setcfg(sc, mii->mii_media_active); 58167087Swpaul WB_UNLOCK(sc); 58250675Swpaul 58341502Swpaul return; 58441502Swpaul} 58541502Swpaul 58641502Swpaul/* 58741502Swpaul * Program the 64-bit multicast hash filter. 58841502Swpaul */ 589102336Salfredstatic void 590102336Salfredwb_setmulti(sc) 59141502Swpaul struct wb_softc *sc; 59241502Swpaul{ 59341502Swpaul struct ifnet *ifp; 59441502Swpaul int h = 0; 59541502Swpaul u_int32_t hashes[2] = { 0, 0 }; 59641502Swpaul struct ifmultiaddr *ifma; 59741502Swpaul u_int32_t rxfilt; 59841502Swpaul int mcnt = 0; 59941502Swpaul 600147256Sbrooks ifp = sc->wb_ifp; 60141502Swpaul 60241502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 60341502Swpaul 60441502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 60541502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 60641502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 60741502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 60841502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 60941502Swpaul return; 61041502Swpaul } 61141502Swpaul 61241502Swpaul /* first, zot all the existing hash bits */ 61341502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 61441502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 61541502Swpaul 61641502Swpaul /* now program new ones */ 617148654Srwatson IF_ADDR_LOCK(ifp); 61872084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 61941502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 62041502Swpaul continue; 621130270Snaddy h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 622130270Snaddy ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 62341502Swpaul if (h < 32) 62441502Swpaul hashes[0] |= (1 << h); 62541502Swpaul else 62641502Swpaul hashes[1] |= (1 << (h - 32)); 62741502Swpaul mcnt++; 62841502Swpaul } 629148654Srwatson IF_ADDR_UNLOCK(ifp); 63041502Swpaul 63141502Swpaul if (mcnt) 63241502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 63341502Swpaul else 63441502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 63541502Swpaul 63641502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 63741502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 63841502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 63941502Swpaul 64041502Swpaul return; 64141502Swpaul} 64241502Swpaul 64341502Swpaul/* 64441502Swpaul * The Winbond manual states that in order to fiddle with the 64541502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 64641502Swpaul * first have to put the transmit and/or receive logic in the idle state. 64741502Swpaul */ 648102336Salfredstatic void 649102336Salfredwb_setcfg(sc, media) 65041502Swpaul struct wb_softc *sc; 65150675Swpaul u_int32_t media; 65241502Swpaul{ 65341502Swpaul int i, restart = 0; 65441502Swpaul 65541502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 65641502Swpaul restart = 1; 65741502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 65841502Swpaul 65941502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 66041502Swpaul DELAY(10); 66141502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 66241502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 66341502Swpaul break; 66441502Swpaul } 66541502Swpaul 66641502Swpaul if (i == WB_TIMEOUT) 667149677Sjhb if_printf(sc->wb_ifp, 668149677Sjhb "failed to force tx and rx to idle state\n"); 66941502Swpaul } 67041502Swpaul 67150675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 67250675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 67350675Swpaul else 67441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 67541502Swpaul 67650675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 67741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 67841502Swpaul else 67941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 68041502Swpaul 68141502Swpaul if (restart) 68241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 68341502Swpaul 68441502Swpaul return; 68541502Swpaul} 68641502Swpaul 687102336Salfredstatic void 688102336Salfredwb_reset(sc) 68941502Swpaul struct wb_softc *sc; 69041502Swpaul{ 69141502Swpaul register int i; 69250675Swpaul struct mii_data *mii; 69341502Swpaul 69450675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 69550675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 69650675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 69750675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 69850675Swpaul 69941502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 70050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 70141502Swpaul 70241502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 70341502Swpaul DELAY(10); 70441502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 70541502Swpaul break; 70641502Swpaul } 70741502Swpaul if (i == WB_TIMEOUT) 708149677Sjhb if_printf(sc->wb_ifp, "reset never completed!\n"); 70941502Swpaul 71041502Swpaul /* Wait a little while for the chip to get its brains in order. */ 71141502Swpaul DELAY(1000); 71241502Swpaul 71350675Swpaul if (sc->wb_miibus == NULL) 71450675Swpaul return; 71541502Swpaul 71650675Swpaul mii = device_get_softc(sc->wb_miibus); 71750675Swpaul if (mii == NULL) 71850675Swpaul return; 71950675Swpaul 72050675Swpaul if (mii->mii_instance) { 72150675Swpaul struct mii_softc *miisc; 72272012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 72350675Swpaul mii_phy_reset(miisc); 72450675Swpaul } 72550675Swpaul 72641502Swpaul return; 72741502Swpaul} 72841502Swpaul 729102336Salfredstatic void 730102336Salfredwb_fixmedia(sc) 73150675Swpaul struct wb_softc *sc; 73250675Swpaul{ 73350675Swpaul struct mii_data *mii = NULL; 73450675Swpaul struct ifnet *ifp; 73550675Swpaul u_int32_t media; 73650675Swpaul 73750675Swpaul if (sc->wb_miibus == NULL) 73850675Swpaul return; 73950675Swpaul 74050675Swpaul mii = device_get_softc(sc->wb_miibus); 741147256Sbrooks ifp = sc->wb_ifp; 74250675Swpaul 74350675Swpaul mii_pollstat(mii); 74450675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 74550675Swpaul media = mii->mii_media_active & ~IFM_10_T; 74650675Swpaul media |= IFM_100_TX; 74750675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 74850675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 74950675Swpaul media |= IFM_10_T; 75050675Swpaul } else 75150675Swpaul return; 75250675Swpaul 75350675Swpaul ifmedia_set(&mii->mii_media, media); 75450675Swpaul 75550675Swpaul return; 75650675Swpaul} 75750675Swpaul 75841502Swpaul/* 75941502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 76041502Swpaul * IDs against our list and return a device name if we find a match. 76141502Swpaul */ 762102336Salfredstatic int 763102336Salfredwb_probe(dev) 76449611Swpaul device_t dev; 76541502Swpaul{ 76641502Swpaul struct wb_type *t; 76741502Swpaul 76841502Swpaul t = wb_devs; 76941502Swpaul 77041502Swpaul while(t->wb_name != NULL) { 77149611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 77249611Swpaul (pci_get_device(dev) == t->wb_did)) { 77349611Swpaul device_set_desc(dev, t->wb_name); 774142398Simp return (BUS_PROBE_DEFAULT); 77541502Swpaul } 77641502Swpaul t++; 77741502Swpaul } 77841502Swpaul 77949611Swpaul return(ENXIO); 78041502Swpaul} 78141502Swpaul 78241502Swpaul/* 78341502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 78441502Swpaul * setup and ethernet/BPF attach. 78541502Swpaul */ 786102336Salfredstatic int 787102336Salfredwb_attach(dev) 78849611Swpaul device_t dev; 78941502Swpaul{ 79041502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 79141502Swpaul struct wb_softc *sc; 79241502Swpaul struct ifnet *ifp; 793149677Sjhb int error = 0, rid; 79441502Swpaul 79549611Swpaul sc = device_get_softc(dev); 79641502Swpaul 79793818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 79893818Sjhb MTX_DEF | MTX_RECURSE); 79941502Swpaul /* 80041502Swpaul * Map control/status registers. 80141502Swpaul */ 80272813Swpaul pci_enable_busmaster(dev); 80341502Swpaul 80449611Swpaul rid = WB_RID; 805127135Snjl sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 80649611Swpaul 80749611Swpaul if (sc->wb_res == NULL) { 808149677Sjhb device_printf(dev, "couldn't map ports/memory\n"); 80949611Swpaul error = ENXIO; 81041502Swpaul goto fail; 81141502Swpaul } 81241502Swpaul 81349611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 81449611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 81549611Swpaul 81641502Swpaul /* Allocate interrupt */ 81749611Swpaul rid = 0; 818127135Snjl sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 81949611Swpaul RF_SHAREABLE | RF_ACTIVE); 82049611Swpaul 82149611Swpaul if (sc->wb_irq == NULL) { 822149677Sjhb device_printf(dev, "couldn't map interrupt\n"); 82349611Swpaul error = ENXIO; 82441502Swpaul goto fail; 82541502Swpaul } 82641502Swpaul 82750675Swpaul /* Save the cache line size. */ 82850675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 82950675Swpaul 83041502Swpaul /* Reset the adapter. */ 83141502Swpaul wb_reset(sc); 83241502Swpaul 83341502Swpaul /* 83441502Swpaul * Get station address from the EEPROM. 83541502Swpaul */ 83641502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 83741502Swpaul 83850675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 83951657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 84050675Swpaul 84150675Swpaul if (sc->wb_ldata == NULL) { 842149677Sjhb device_printf(dev, "no memory for list buffers!\n"); 84349611Swpaul error = ENXIO; 84449611Swpaul goto fail; 84541502Swpaul } 84641502Swpaul 84741502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 84841502Swpaul 849147256Sbrooks ifp = sc->wb_ifp = if_alloc(IFT_ETHER); 850147256Sbrooks if (ifp == NULL) { 851149677Sjhb device_printf(dev, "can not if_alloc()\n"); 852147256Sbrooks error = ENOSPC; 853147256Sbrooks goto fail; 854147256Sbrooks } 85541502Swpaul ifp->if_softc = sc; 856121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 85741502Swpaul ifp->if_mtu = ETHERMTU; 858134442Srwatson ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 859134442Srwatson IFF_NEEDSGIANT; 86041502Swpaul ifp->if_ioctl = wb_ioctl; 86141502Swpaul ifp->if_start = wb_start; 86241502Swpaul ifp->if_watchdog = wb_watchdog; 86341502Swpaul ifp->if_init = wb_init; 86441502Swpaul ifp->if_baudrate = 10000000; 86543515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 86641502Swpaul 86750675Swpaul /* 86850675Swpaul * Do MII setup. 86950675Swpaul */ 87050675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 87150675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 87249611Swpaul error = ENXIO; 87341502Swpaul goto fail; 87441502Swpaul } 87541502Swpaul 87641502Swpaul /* 87763090Sarchie * Call MI attach routine. 87841502Swpaul */ 879106936Ssam ether_ifattach(ifp, eaddr); 88041502Swpaul 881113609Snjl /* Hook interrupt last to avoid having to lock softc */ 882112872Snjl error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 883112872Snjl wb_intr, sc, &sc->wb_intrhand); 884112872Snjl 885112872Snjl if (error) { 886149677Sjhb device_printf(dev, "couldn't set up irq\n"); 887113609Snjl ether_ifdetach(ifp); 888147256Sbrooks if_free(ifp); 889112872Snjl goto fail; 890112872Snjl } 891112872Snjl 89241502Swpaulfail: 89350675Swpaul if (error) 894112872Snjl wb_detach(dev); 89550675Swpaul 89649611Swpaul return(error); 89741502Swpaul} 89841502Swpaul 899113609Snjl/* 900113609Snjl * Shutdown hardware and free up resources. This can be called any 901113609Snjl * time after the mutex has been initialized. It is called in both 902113609Snjl * the error case in attach and the normal detach case so it needs 903113609Snjl * to be careful about only freeing resources that have actually been 904113609Snjl * allocated. 905113609Snjl */ 906102336Salfredstatic int 907102336Salfredwb_detach(dev) 90849611Swpaul device_t dev; 90949611Swpaul{ 91049611Swpaul struct wb_softc *sc; 91149611Swpaul struct ifnet *ifp; 91249611Swpaul 91349611Swpaul sc = device_get_softc(dev); 914112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 91567087Swpaul WB_LOCK(sc); 916147256Sbrooks ifp = sc->wb_ifp; 91749611Swpaul 918113609Snjl /* 919113609Snjl * Delete any miibus and phy devices attached to this interface. 920113609Snjl * This should only be done if attach succeeded. 921113609Snjl */ 922113812Simp if (device_is_attached(dev)) { 923113609Snjl wb_stop(sc); 924112872Snjl ether_ifdetach(ifp); 925147256Sbrooks if_free(ifp); 926113609Snjl } 927113609Snjl if (sc->wb_miibus) 928112872Snjl device_delete_child(dev, sc->wb_miibus); 929113609Snjl bus_generic_detach(dev); 93050675Swpaul 931112872Snjl if (sc->wb_intrhand) 932112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 933112872Snjl if (sc->wb_irq) 934112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 935112872Snjl if (sc->wb_res) 936112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 93749611Swpaul 938112872Snjl if (sc->wb_ldata) { 939112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 940112872Snjl M_DEVBUF); 941112872Snjl } 94249611Swpaul 94367087Swpaul WB_UNLOCK(sc); 94467087Swpaul mtx_destroy(&sc->wb_mtx); 94549611Swpaul 94649611Swpaul return(0); 94749611Swpaul} 94849611Swpaul 94941502Swpaul/* 95041502Swpaul * Initialize the transmit descriptors. 95141502Swpaul */ 952102336Salfredstatic int 953102336Salfredwb_list_tx_init(sc) 95441502Swpaul struct wb_softc *sc; 95541502Swpaul{ 95641502Swpaul struct wb_chain_data *cd; 95741502Swpaul struct wb_list_data *ld; 95841502Swpaul int i; 95941502Swpaul 96041502Swpaul cd = &sc->wb_cdata; 96141502Swpaul ld = sc->wb_ldata; 96241502Swpaul 96341502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 96441502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 96541502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 96641502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 96741502Swpaul &cd->wb_tx_chain[0]; 96841502Swpaul } else { 96941502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 97041502Swpaul &cd->wb_tx_chain[i + 1]; 97141502Swpaul } 97241502Swpaul } 97341502Swpaul 97441502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 97541502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 97641502Swpaul 97741502Swpaul return(0); 97841502Swpaul} 97941502Swpaul 98041502Swpaul 98141502Swpaul/* 98241502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 98341502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 98441502Swpaul * points back to the first. 98541502Swpaul */ 986102336Salfredstatic int 987102336Salfredwb_list_rx_init(sc) 98841502Swpaul struct wb_softc *sc; 98941502Swpaul{ 99041502Swpaul struct wb_chain_data *cd; 99141502Swpaul struct wb_list_data *ld; 99241502Swpaul int i; 99341502Swpaul 99441502Swpaul cd = &sc->wb_cdata; 99541502Swpaul ld = sc->wb_ldata; 99641502Swpaul 99741502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 99841502Swpaul cd->wb_rx_chain[i].wb_ptr = 99941502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 100050675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 100148745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 100241502Swpaul return(ENOBUFS); 100341502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 100441502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 100541502Swpaul ld->wb_rx_list[i].wb_next = 100641502Swpaul vtophys(&ld->wb_rx_list[0]); 100741502Swpaul } else { 100841502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 100941502Swpaul &cd->wb_rx_chain[i + 1]; 101041502Swpaul ld->wb_rx_list[i].wb_next = 101141502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 101241502Swpaul } 101341502Swpaul } 101441502Swpaul 101541502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 101641502Swpaul 101741502Swpaul return(0); 101841502Swpaul} 101941502Swpaul 1020102336Salfredstatic void 1021102336Salfredwb_bfree(buf, args) 102298995Salfred void *buf; 102364837Sdwmalone void *args; 102450675Swpaul{ 102550675Swpaul return; 102650675Swpaul} 102750675Swpaul 102841502Swpaul/* 102941502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 103041502Swpaul */ 1031102336Salfredstatic int 1032102336Salfredwb_newbuf(sc, c, m) 103341502Swpaul struct wb_softc *sc; 103441502Swpaul struct wb_chain_onefrag *c; 103548745Swpaul struct mbuf *m; 103641502Swpaul{ 103741502Swpaul struct mbuf *m_new = NULL; 103841502Swpaul 103948745Swpaul if (m == NULL) { 1040111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 104187846Sluigi if (m_new == NULL) 104248745Swpaul return(ENOBUFS); 104364837Sdwmalone m_new->m_data = c->wb_buf; 104464837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 104568621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 104668621Sbmilekic EXT_NET_DRV); 104748745Swpaul } else { 104848745Swpaul m_new = m; 104950675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 105048745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 105141502Swpaul } 105241502Swpaul 105348745Swpaul m_adj(m_new, sizeof(u_int64_t)); 105448745Swpaul 105541502Swpaul c->wb_mbuf = m_new; 105641502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 105750675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 105841502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 105941502Swpaul 106041502Swpaul return(0); 106141502Swpaul} 106241502Swpaul 106341502Swpaul/* 106441502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 106541502Swpaul * the higher level protocols. 106641502Swpaul */ 1067102336Salfredstatic void 1068102336Salfredwb_rxeof(sc) 106941502Swpaul struct wb_softc *sc; 107041502Swpaul{ 107150675Swpaul struct mbuf *m = NULL; 107241502Swpaul struct ifnet *ifp; 107341502Swpaul struct wb_chain_onefrag *cur_rx; 107441502Swpaul int total_len = 0; 107541502Swpaul u_int32_t rxstat; 107641502Swpaul 1077122689Ssam WB_LOCK_ASSERT(sc); 1078122689Ssam 1079147256Sbrooks ifp = sc->wb_ifp; 108041502Swpaul 108141502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 108241502Swpaul WB_RXSTAT_OWN)) { 108348745Swpaul struct mbuf *m0 = NULL; 108448745Swpaul 108541502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 108641502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 108750675Swpaul 108848745Swpaul m = cur_rx->wb_mbuf; 108941502Swpaul 109050675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 109150675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 109250675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 109350675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 109450675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 109541502Swpaul ifp->if_ierrors++; 109650675Swpaul wb_newbuf(sc, cur_rx, m); 1097149677Sjhb if_printf(ifp, "receiver babbling: possible chip " 1098149677Sjhb "bug, forcing reset\n"); 109950675Swpaul wb_fixmedia(sc); 110050675Swpaul wb_reset(sc); 110150675Swpaul wb_init(sc); 110241502Swpaul return; 110341502Swpaul } 110441502Swpaul 110542718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 110642718Swpaul ifp->if_ierrors++; 110748745Swpaul wb_newbuf(sc, cur_rx, m); 110850675Swpaul break; 110942718Swpaul } 111042718Swpaul 111141502Swpaul /* No errors; receive the packet. */ 111241502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 111341502Swpaul 111441502Swpaul /* 111541934Swpaul * XXX The Winbond chip includes the CRC with every 111641934Swpaul * received frame, and there's no way to turn this 111741934Swpaul * behavior off (at least, I can't find anything in 111841934Swpaul * the manual that explains how to do it) so we have 111941934Swpaul * to trim off the CRC manually. 112041934Swpaul */ 112141934Swpaul total_len -= ETHER_CRC_LEN; 112241934Swpaul 112378508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 112478508Sbmilekic NULL); 112548745Swpaul wb_newbuf(sc, cur_rx, m); 112648745Swpaul if (m0 == NULL) { 112748745Swpaul ifp->if_ierrors++; 112850675Swpaul break; 112941502Swpaul } 113048745Swpaul m = m0; 113141502Swpaul 113241502Swpaul ifp->if_ipackets++; 1133122689Ssam WB_UNLOCK(sc); 1134106936Ssam (*ifp->if_input)(ifp, m); 1135122689Ssam WB_LOCK(sc); 113641502Swpaul } 113741502Swpaul} 113841502Swpaul 1139105221Sphkstatic void 1140102336Salfredwb_rxeoc(sc) 114141502Swpaul struct wb_softc *sc; 114241502Swpaul{ 114341502Swpaul wb_rxeof(sc); 114441502Swpaul 114541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 114641502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 114741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 114841502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 114941502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 115041502Swpaul 115141502Swpaul return; 115241502Swpaul} 115341502Swpaul 115441502Swpaul/* 115541502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 115641502Swpaul * the list buffers. 115741502Swpaul */ 1158102336Salfredstatic void 1159102336Salfredwb_txeof(sc) 116041502Swpaul struct wb_softc *sc; 116141502Swpaul{ 116241502Swpaul struct wb_chain *cur_tx; 116341502Swpaul struct ifnet *ifp; 116441502Swpaul 1165147256Sbrooks ifp = sc->wb_ifp; 116641502Swpaul 116741502Swpaul /* Clear the timeout timer. */ 116841502Swpaul ifp->if_timer = 0; 116941502Swpaul 117041502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 117141502Swpaul return; 117241502Swpaul 117341502Swpaul /* 117441502Swpaul * Go through our tx list and free mbufs for those 117541502Swpaul * frames that have been transmitted. 117641502Swpaul */ 117741502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 117841502Swpaul u_int32_t txstat; 117941502Swpaul 118041502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 118141502Swpaul txstat = WB_TXSTATUS(cur_tx); 118241502Swpaul 118341502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 118441502Swpaul break; 118541502Swpaul 118641502Swpaul if (txstat & WB_TXSTAT_TXERR) { 118741502Swpaul ifp->if_oerrors++; 118841502Swpaul if (txstat & WB_TXSTAT_ABORT) 118941502Swpaul ifp->if_collisions++; 119041502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 119141502Swpaul ifp->if_collisions++; 119241502Swpaul } 119341502Swpaul 119441502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 119541502Swpaul 119641502Swpaul ifp->if_opackets++; 119741502Swpaul m_freem(cur_tx->wb_mbuf); 119841502Swpaul cur_tx->wb_mbuf = NULL; 119941502Swpaul 120041502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 120141502Swpaul sc->wb_cdata.wb_tx_head = NULL; 120241502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 120341502Swpaul break; 120441502Swpaul } 120541502Swpaul 120641502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 120741502Swpaul } 120841502Swpaul 120941502Swpaul return; 121041502Swpaul} 121141502Swpaul 121241502Swpaul/* 121341502Swpaul * TX 'end of channel' interrupt handler. 121441502Swpaul */ 1215102336Salfredstatic void 1216102336Salfredwb_txeoc(sc) 121741502Swpaul struct wb_softc *sc; 121841502Swpaul{ 121941502Swpaul struct ifnet *ifp; 122041502Swpaul 1221147256Sbrooks ifp = sc->wb_ifp; 122241502Swpaul 122341502Swpaul ifp->if_timer = 0; 122441502Swpaul 122541502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 1226148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 122741502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 122841502Swpaul } else { 122941502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 123041502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 123141502Swpaul ifp->if_timer = 5; 123241502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 123341502Swpaul } 123441502Swpaul } 123541502Swpaul 123641502Swpaul return; 123741502Swpaul} 123841502Swpaul 1239102336Salfredstatic void 1240102336Salfredwb_intr(arg) 124141502Swpaul void *arg; 124241502Swpaul{ 124341502Swpaul struct wb_softc *sc; 124441502Swpaul struct ifnet *ifp; 124541502Swpaul u_int32_t status; 124641502Swpaul 124741502Swpaul sc = arg; 124867087Swpaul WB_LOCK(sc); 1249147256Sbrooks ifp = sc->wb_ifp; 125041502Swpaul 125167087Swpaul if (!(ifp->if_flags & IFF_UP)) { 125267087Swpaul WB_UNLOCK(sc); 125341502Swpaul return; 125467087Swpaul } 125541502Swpaul 125641502Swpaul /* Disable interrupts. */ 125741502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 125841502Swpaul 125941502Swpaul for (;;) { 126041502Swpaul 126141502Swpaul status = CSR_READ_4(sc, WB_ISR); 126241502Swpaul if (status) 126341502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 126441502Swpaul 126541502Swpaul if ((status & WB_INTRS) == 0) 126641502Swpaul break; 126741502Swpaul 126841502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 126941502Swpaul ifp->if_ierrors++; 127041502Swpaul wb_reset(sc); 127150675Swpaul if (status & WB_ISR_RX_ERR) 127250675Swpaul wb_fixmedia(sc); 127341502Swpaul wb_init(sc); 127450675Swpaul continue; 127541502Swpaul } 127641502Swpaul 127750675Swpaul if (status & WB_ISR_RX_OK) 127850675Swpaul wb_rxeof(sc); 127950675Swpaul 128050675Swpaul if (status & WB_ISR_RX_IDLE) 128150675Swpaul wb_rxeoc(sc); 128250675Swpaul 128341502Swpaul if (status & WB_ISR_TX_OK) 128441502Swpaul wb_txeof(sc); 128541502Swpaul 128641502Swpaul if (status & WB_ISR_TX_NOBUF) 128741502Swpaul wb_txeoc(sc); 128841502Swpaul 128941502Swpaul if (status & WB_ISR_TX_IDLE) { 129041502Swpaul wb_txeof(sc); 129141502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 129241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 129341502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 129441502Swpaul } 129541502Swpaul } 129641502Swpaul 129741502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 129841502Swpaul ifp->if_oerrors++; 129941502Swpaul wb_txeof(sc); 130041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 130141502Swpaul /* Jack up TX threshold */ 130241502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 130341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 130441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 130541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 130641502Swpaul } 130741502Swpaul 130841502Swpaul if (status & WB_ISR_BUS_ERR) { 130941502Swpaul wb_reset(sc); 131041502Swpaul wb_init(sc); 131141502Swpaul } 131241502Swpaul 131341502Swpaul } 131441502Swpaul 131541502Swpaul /* Re-enable interrupts. */ 131641502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 131741502Swpaul 131841502Swpaul if (ifp->if_snd.ifq_head != NULL) { 131941502Swpaul wb_start(ifp); 132041502Swpaul } 132141502Swpaul 132267087Swpaul WB_UNLOCK(sc); 132367087Swpaul 132441502Swpaul return; 132541502Swpaul} 132641502Swpaul 1327102336Salfredstatic void 1328102336Salfredwb_tick(xsc) 132950675Swpaul void *xsc; 133050675Swpaul{ 133150675Swpaul struct wb_softc *sc; 133250675Swpaul struct mii_data *mii; 133350675Swpaul 133450675Swpaul sc = xsc; 133567087Swpaul WB_LOCK(sc); 133650675Swpaul mii = device_get_softc(sc->wb_miibus); 133750675Swpaul 133850675Swpaul mii_tick(mii); 133950675Swpaul 134050675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 134150675Swpaul 134267087Swpaul WB_UNLOCK(sc); 134350685Swpaul 134450675Swpaul return; 134550675Swpaul} 134650675Swpaul 134741502Swpaul/* 134841502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 134941502Swpaul * pointers to the fragment pointers. 135041502Swpaul */ 1351102336Salfredstatic int 1352102336Salfredwb_encap(sc, c, m_head) 135341502Swpaul struct wb_softc *sc; 135441502Swpaul struct wb_chain *c; 135541502Swpaul struct mbuf *m_head; 135641502Swpaul{ 135741502Swpaul int frag = 0; 135841502Swpaul struct wb_desc *f = NULL; 135941502Swpaul int total_len; 136041502Swpaul struct mbuf *m; 136141502Swpaul 136241502Swpaul /* 136341502Swpaul * Start packing the mbufs in this chain into 136441502Swpaul * the fragment pointers. Stop when we run out 136541502Swpaul * of fragments or hit the end of the mbuf chain. 136641502Swpaul */ 136741502Swpaul m = m_head; 136841502Swpaul total_len = 0; 136941502Swpaul 137041502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 137141502Swpaul if (m->m_len != 0) { 137241502Swpaul if (frag == WB_MAXFRAGS) 137341502Swpaul break; 137441502Swpaul total_len += m->m_len; 137541502Swpaul f = &c->wb_ptr->wb_frag[frag]; 137641502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 137741502Swpaul if (frag == 0) { 137841502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 137941502Swpaul f->wb_status = 0; 138041502Swpaul } else 138141502Swpaul f->wb_status = WB_TXSTAT_OWN; 138241502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 138341502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 138441502Swpaul frag++; 138541502Swpaul } 138641502Swpaul } 138741502Swpaul 138841502Swpaul /* 138941502Swpaul * Handle special case: we used up all 16 fragments, 139041502Swpaul * but we have more mbufs left in the chain. Copy the 139141502Swpaul * data into an mbuf cluster. Note that we don't 139241502Swpaul * bother clearing the values in the other fragment 139341502Swpaul * pointers/counters; it wouldn't gain us anything, 139441502Swpaul * and would waste cycles. 139541502Swpaul */ 139641502Swpaul if (m != NULL) { 139741502Swpaul struct mbuf *m_new = NULL; 139841502Swpaul 1399111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 140087846Sluigi if (m_new == NULL) 140141502Swpaul return(1); 140241502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1403111119Simp MCLGET(m_new, M_DONTWAIT); 140441502Swpaul if (!(m_new->m_flags & M_EXT)) { 140541502Swpaul m_freem(m_new); 140641502Swpaul return(1); 140741502Swpaul } 140841502Swpaul } 140941502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 141041502Swpaul mtod(m_new, caddr_t)); 141141502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 141241502Swpaul m_freem(m_head); 141341502Swpaul m_head = m_new; 141441502Swpaul f = &c->wb_ptr->wb_frag[0]; 141541502Swpaul f->wb_status = 0; 141641502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 141741502Swpaul f->wb_ctl = total_len = m_new->m_len; 141841502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 141941502Swpaul frag = 1; 142041502Swpaul } 142141502Swpaul 142241502Swpaul if (total_len < WB_MIN_FRAMELEN) { 142341502Swpaul f = &c->wb_ptr->wb_frag[frag]; 142441502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 142541502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 142641502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 142741502Swpaul f->wb_status = WB_TXSTAT_OWN; 142841502Swpaul frag++; 142941502Swpaul } 143041502Swpaul 143141502Swpaul c->wb_mbuf = m_head; 143241502Swpaul c->wb_lastdesc = frag - 1; 143341502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 143441502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 143541502Swpaul 143641502Swpaul return(0); 143741502Swpaul} 143841502Swpaul 143941502Swpaul/* 144041502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 144141502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 144241502Swpaul * copy of the pointers since the transmit list fragment pointers are 144341502Swpaul * physical addresses. 144441502Swpaul */ 144541502Swpaul 1446102336Salfredstatic void 1447102336Salfredwb_start(ifp) 144841502Swpaul struct ifnet *ifp; 144941502Swpaul{ 145041502Swpaul struct wb_softc *sc; 145141502Swpaul struct mbuf *m_head = NULL; 145241502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 145341502Swpaul 145441502Swpaul sc = ifp->if_softc; 145567087Swpaul WB_LOCK(sc); 145641502Swpaul 145741502Swpaul /* 145841502Swpaul * Check for an available queue slot. If there are none, 145941502Swpaul * punt. 146041502Swpaul */ 146141502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1462148887Srwatson ifp->if_drv_flags |= IFF_DRV_OACTIVE; 146367087Swpaul WB_UNLOCK(sc); 146441502Swpaul return; 146541502Swpaul } 146641502Swpaul 146741502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 146841502Swpaul 146941502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 147041502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 147141502Swpaul if (m_head == NULL) 147241502Swpaul break; 147341502Swpaul 147441502Swpaul /* Pick a descriptor off the free list. */ 147541502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 147641502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 147741502Swpaul 147841502Swpaul /* Pack the data into the descriptor. */ 147941502Swpaul wb_encap(sc, cur_tx, m_head); 148041502Swpaul 148141502Swpaul if (cur_tx != start_tx) 148241502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 148341502Swpaul 148441502Swpaul /* 148541502Swpaul * If there's a BPF listener, bounce a copy of this frame 148641502Swpaul * to him. 148741502Swpaul */ 1488106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 148941502Swpaul } 149041502Swpaul 149141502Swpaul /* 149241526Swpaul * If there are no packets queued, bail. 149341526Swpaul */ 149467087Swpaul if (cur_tx == NULL) { 149567087Swpaul WB_UNLOCK(sc); 149641526Swpaul return; 149767087Swpaul } 149841526Swpaul 149941526Swpaul /* 150041502Swpaul * Place the request for the upload interrupt 150141502Swpaul * in the last descriptor in the chain. This way, if 150241502Swpaul * we're chaining several packets at once, we'll only 150341502Swpaul * get an interupt once for the whole chain rather than 150441502Swpaul * once for each packet. 150541502Swpaul */ 150641502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 150742718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 150841502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 150941502Swpaul 151041502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 151141502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 151241502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 151341502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 151441502Swpaul } else { 151541502Swpaul /* 151641502Swpaul * We need to distinguish between the case where 151741502Swpaul * the own bit is clear because the chip cleared it 151841502Swpaul * and where the own bit is clear because we haven't 151941502Swpaul * set it yet. The magic value WB_UNSET is just some 152041502Swpaul * ramdomly chosen number which doesn't have the own 152141502Swpaul * bit set. When we actually transmit the frame, the 152241502Swpaul * status word will have _only_ the own bit set, so 152341502Swpaul * the txeoc handler will be able to tell if it needs 152441502Swpaul * to initiate another transmission to flush out pending 152541502Swpaul * frames. 152641502Swpaul */ 152741502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 152841502Swpaul } 152941502Swpaul 153041502Swpaul /* 153141502Swpaul * Set a timeout in case the chip goes out to lunch. 153241502Swpaul */ 153341502Swpaul ifp->if_timer = 5; 153467087Swpaul WB_UNLOCK(sc); 153541502Swpaul 153641502Swpaul return; 153741502Swpaul} 153841502Swpaul 1539102336Salfredstatic void 1540102336Salfredwb_init(xsc) 154141502Swpaul void *xsc; 154241502Swpaul{ 154341502Swpaul struct wb_softc *sc = xsc; 1544147256Sbrooks struct ifnet *ifp = sc->wb_ifp; 154567087Swpaul int i; 154650675Swpaul struct mii_data *mii; 154741502Swpaul 154867087Swpaul WB_LOCK(sc); 154950675Swpaul mii = device_get_softc(sc->wb_miibus); 155041502Swpaul 155141502Swpaul /* 155241502Swpaul * Cancel pending I/O and free all RX/TX buffers. 155341502Swpaul */ 155441502Swpaul wb_stop(sc); 155541502Swpaul wb_reset(sc); 155641502Swpaul 155741502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 155841502Swpaul 155941502Swpaul /* 156041502Swpaul * Set cache alignment and burst length. 156141502Swpaul */ 156250675Swpaul#ifdef foo 156341502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 156441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 156541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 156650675Swpaul#endif 156741502Swpaul 156850675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 156950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 157050675Swpaul switch(sc->wb_cachesize) { 157150675Swpaul case 32: 157250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 157350675Swpaul break; 157450675Swpaul case 16: 157550675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 157650675Swpaul break; 157750675Swpaul case 8: 157850675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 157950675Swpaul break; 158050675Swpaul case 0: 158150675Swpaul default: 158250675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 158350675Swpaul break; 158450675Swpaul } 158550675Swpaul 158641502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 158741502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 158841502Swpaul 158941502Swpaul /* Init our MAC address */ 159041502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 1591147256Sbrooks CSR_WRITE_1(sc, WB_NODE0 + i, IFP2ENADDR(sc->wb_ifp)[i]); 159241502Swpaul } 159341502Swpaul 159441502Swpaul /* Init circular RX list. */ 159541502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 1596149677Sjhb if_printf(ifp, 1597149677Sjhb "initialization failed: no memory for rx buffers\n"); 159841502Swpaul wb_stop(sc); 159967087Swpaul WB_UNLOCK(sc); 160041502Swpaul return; 160141502Swpaul } 160241502Swpaul 160341502Swpaul /* Init TX descriptors. */ 160441502Swpaul wb_list_tx_init(sc); 160541502Swpaul 160641502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 160741502Swpaul if (ifp->if_flags & IFF_PROMISC) { 160841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 160941502Swpaul } else { 161041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 161141502Swpaul } 161241502Swpaul 161341502Swpaul /* 161441502Swpaul * Set capture broadcast bit to capture broadcast frames. 161541502Swpaul */ 161641502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 161741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 161841502Swpaul } else { 161941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 162041502Swpaul } 162141502Swpaul 162241502Swpaul /* 162341502Swpaul * Program the multicast filter, if necessary. 162441502Swpaul */ 162541502Swpaul wb_setmulti(sc); 162641502Swpaul 162741502Swpaul /* 162841502Swpaul * Load the address of the RX list. 162941502Swpaul */ 163041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 163141502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 163241502Swpaul 163341502Swpaul /* 163441502Swpaul * Enable interrupts. 163541502Swpaul */ 163641502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 163741502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 163841502Swpaul 163941502Swpaul /* Enable receiver and transmitter. */ 164041502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 164141502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 164241502Swpaul 164341502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 164441502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 164541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 164641502Swpaul 164750675Swpaul mii_mediachg(mii); 164841502Swpaul 1649148887Srwatson ifp->if_drv_flags |= IFF_DRV_RUNNING; 1650148887Srwatson ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 165141502Swpaul 165250675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 165367087Swpaul WB_UNLOCK(sc); 165450675Swpaul 165541502Swpaul return; 165641502Swpaul} 165741502Swpaul 165841502Swpaul/* 165941502Swpaul * Set media options. 166041502Swpaul */ 1661102336Salfredstatic int 1662102336Salfredwb_ifmedia_upd(ifp) 166341502Swpaul struct ifnet *ifp; 166441502Swpaul{ 166541502Swpaul struct wb_softc *sc; 166641502Swpaul 166741502Swpaul sc = ifp->if_softc; 166841502Swpaul 166950675Swpaul if (ifp->if_flags & IFF_UP) 167050675Swpaul wb_init(sc); 167141502Swpaul 167241502Swpaul return(0); 167341502Swpaul} 167441502Swpaul 167541502Swpaul/* 167641502Swpaul * Report current media status. 167741502Swpaul */ 1678102336Salfredstatic void 1679102336Salfredwb_ifmedia_sts(ifp, ifmr) 168041502Swpaul struct ifnet *ifp; 168141502Swpaul struct ifmediareq *ifmr; 168241502Swpaul{ 168341502Swpaul struct wb_softc *sc; 168450675Swpaul struct mii_data *mii; 168541502Swpaul 168641502Swpaul sc = ifp->if_softc; 168741502Swpaul 168850675Swpaul mii = device_get_softc(sc->wb_miibus); 168941502Swpaul 169050675Swpaul mii_pollstat(mii); 169150675Swpaul ifmr->ifm_active = mii->mii_media_active; 169250675Swpaul ifmr->ifm_status = mii->mii_media_status; 169341502Swpaul 169441502Swpaul return; 169541502Swpaul} 169641502Swpaul 1697102336Salfredstatic int 1698102336Salfredwb_ioctl(ifp, command, data) 169941502Swpaul struct ifnet *ifp; 170041502Swpaul u_long command; 170141502Swpaul caddr_t data; 170241502Swpaul{ 170341502Swpaul struct wb_softc *sc = ifp->if_softc; 170450675Swpaul struct mii_data *mii; 170541502Swpaul struct ifreq *ifr = (struct ifreq *) data; 170667087Swpaul int error = 0; 170741502Swpaul 170867087Swpaul WB_LOCK(sc); 170941502Swpaul 171041502Swpaul switch(command) { 171141502Swpaul case SIOCSIFFLAGS: 171241502Swpaul if (ifp->if_flags & IFF_UP) { 171341502Swpaul wb_init(sc); 171441502Swpaul } else { 1715148887Srwatson if (ifp->if_drv_flags & IFF_DRV_RUNNING) 171641502Swpaul wb_stop(sc); 171741502Swpaul } 171841502Swpaul error = 0; 171941502Swpaul break; 172041502Swpaul case SIOCADDMULTI: 172141502Swpaul case SIOCDELMULTI: 172241502Swpaul wb_setmulti(sc); 172341502Swpaul error = 0; 172441502Swpaul break; 172541502Swpaul case SIOCGIFMEDIA: 172641502Swpaul case SIOCSIFMEDIA: 172750675Swpaul mii = device_get_softc(sc->wb_miibus); 172850675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 172941502Swpaul break; 173041502Swpaul default: 1731106936Ssam error = ether_ioctl(ifp, command, data); 173241502Swpaul break; 173341502Swpaul } 173441502Swpaul 173567087Swpaul WB_UNLOCK(sc); 173641502Swpaul 173741502Swpaul return(error); 173841502Swpaul} 173941502Swpaul 1740102336Salfredstatic void 1741102336Salfredwb_watchdog(ifp) 174241502Swpaul struct ifnet *ifp; 174341502Swpaul{ 174441502Swpaul struct wb_softc *sc; 174541502Swpaul 174641502Swpaul sc = ifp->if_softc; 174741502Swpaul 174867087Swpaul WB_LOCK(sc); 174941502Swpaul ifp->if_oerrors++; 1750149677Sjhb if_printf(ifp, "watchdog timeout\n"); 175150675Swpaul#ifdef foo 175241502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1753149677Sjhb if_printf(ifp, "no carrier - transceiver cable problem?\n"); 175450675Swpaul#endif 175541502Swpaul wb_stop(sc); 175641502Swpaul wb_reset(sc); 175741502Swpaul wb_init(sc); 175841502Swpaul 175941502Swpaul if (ifp->if_snd.ifq_head != NULL) 176041502Swpaul wb_start(ifp); 176167087Swpaul WB_UNLOCK(sc); 176241502Swpaul 176341502Swpaul return; 176441502Swpaul} 176541502Swpaul 176641502Swpaul/* 176741502Swpaul * Stop the adapter and free any mbufs allocated to the 176841502Swpaul * RX and TX lists. 176941502Swpaul */ 1770102336Salfredstatic void 1771102336Salfredwb_stop(sc) 177241502Swpaul struct wb_softc *sc; 177341502Swpaul{ 177441502Swpaul register int i; 177541502Swpaul struct ifnet *ifp; 177641502Swpaul 177767087Swpaul WB_LOCK(sc); 1778147256Sbrooks ifp = sc->wb_ifp; 177941502Swpaul ifp->if_timer = 0; 178041502Swpaul 178150675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 178250675Swpaul 178341502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 178441502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 178541502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 178641502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 178741502Swpaul 178841502Swpaul /* 178941502Swpaul * Free data in the RX lists. 179041502Swpaul */ 179141502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 179241502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 179341502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 179441502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 179541502Swpaul } 179641502Swpaul } 179741502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 179841502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 179941502Swpaul 180041502Swpaul /* 180141502Swpaul * Free the TX list buffers. 180241502Swpaul */ 180341502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 180441502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 180541502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 180641502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 180741502Swpaul } 180841502Swpaul } 180941502Swpaul 181041502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 181141502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 181241502Swpaul 1813148887Srwatson ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 181467087Swpaul WB_UNLOCK(sc); 181541502Swpaul 181641502Swpaul return; 181741502Swpaul} 181841502Swpaul 181941502Swpaul/* 182041502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 182141502Swpaul * get confused by errant DMAs when rebooting. 182241502Swpaul */ 1823102336Salfredstatic void 1824102336Salfredwb_shutdown(dev) 182549611Swpaul device_t dev; 182641502Swpaul{ 182749611Swpaul struct wb_softc *sc; 182841502Swpaul 182949611Swpaul sc = device_get_softc(dev); 183041502Swpaul wb_stop(sc); 183141502Swpaul 183241502Swpaul return; 183341502Swpaul} 1834