if_wb.c revision 130270
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 130270 2004-06-09 14:34:04Z naddy $"); 35 36/* 37 * Winbond fast ethernet PCI NIC driver 38 * 39 * Supports various cheap network adapters based on the Winbond W89C840F 40 * fast ethernet controller chip. This includes adapters manufactured by 41 * Winbond itself and some made by Linksys. 42 * 43 * Written by Bill Paul <wpaul@ctr.columbia.edu> 44 * Electrical Engineering Department 45 * Columbia University, New York City 46 */ 47/* 48 * The Winbond W89C840F chip is a bus master; in some ways it resembles 49 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 50 * one major difference which is that while the registers do many of 51 * the same things as a tulip adapter, the offsets are different: where 52 * tulip registers are typically spaced 8 bytes apart, the Winbond 53 * registers are spaced 4 bytes apart. The receiver filter is also 54 * programmed differently. 55 * 56 * Like the tulip, the Winbond chip uses small descriptors containing 57 * a status word, a control word and 32-bit areas that can either be used 58 * to point to two external data blocks, or to point to a single block 59 * and another descriptor in a linked list. Descriptors can be grouped 60 * together in blocks to form fixed length rings or can be chained 61 * together in linked lists. A single packet may be spread out over 62 * several descriptors if necessary. 63 * 64 * For the receive ring, this driver uses a linked list of descriptors, 65 * each pointing to a single mbuf cluster buffer, which us large enough 66 * to hold an entire packet. The link list is looped back to created a 67 * closed ring. 68 * 69 * For transmission, the driver creates a linked list of 'super descriptors' 70 * which each contain several individual descriptors linked toghether. 71 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 72 * abuse as fragment pointers. This allows us to use a buffer managment 73 * scheme very similar to that used in the ThunderLAN and Etherlink XL 74 * drivers. 75 * 76 * Autonegotiation is performed using the external PHY via the MII bus. 77 * The sample boards I have all use a Davicom PHY. 78 * 79 * Note: the author of the Linux driver for the Winbond chip alludes 80 * to some sort of flaw in the chip's design that seems to mandate some 81 * drastic workaround which signigicantly impairs transmit performance. 82 * I have no idea what he's on about: transmit performance with all 83 * three of my test boards seems fine. 84 */ 85 86#include "opt_bdg.h" 87 88#include <sys/param.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_memio.h> 109#include <machine/bus_pio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124#define WB_USEIOSPACE 125 126#include <pci/if_wbreg.h> 127 128MODULE_DEPEND(wb, pci, 1, 1, 1); 129MODULE_DEPEND(wb, ether, 1, 1, 1); 130MODULE_DEPEND(wb, miibus, 1, 1, 1); 131 132/* 133 * Various supported device vendors/types and their names. 134 */ 135static struct wb_type wb_devs[] = { 136 { WB_VENDORID, WB_DEVICEID_840F, 137 "Winbond W89C840F 10/100BaseTX" }, 138 { CP_VENDORID, CP_DEVICEID_RL100, 139 "Compex RL100-ATX 10/100baseTX" }, 140 { 0, 0, NULL } 141}; 142 143static int wb_probe (device_t); 144static int wb_attach (device_t); 145static int wb_detach (device_t); 146 147static void wb_bfree (void *addr, void *args); 148static int wb_newbuf (struct wb_softc *, 149 struct wb_chain_onefrag *, 150 struct mbuf *); 151static int wb_encap (struct wb_softc *, struct wb_chain *, 152 struct mbuf *); 153 154static void wb_rxeof (struct wb_softc *); 155static void wb_rxeoc (struct wb_softc *); 156static void wb_txeof (struct wb_softc *); 157static void wb_txeoc (struct wb_softc *); 158static void wb_intr (void *); 159static void wb_tick (void *); 160static void wb_start (struct ifnet *); 161static int wb_ioctl (struct ifnet *, u_long, caddr_t); 162static void wb_init (void *); 163static void wb_stop (struct wb_softc *); 164static void wb_watchdog (struct ifnet *); 165static void wb_shutdown (device_t); 166static int wb_ifmedia_upd (struct ifnet *); 167static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 168 169static void wb_eeprom_putbyte (struct wb_softc *, int); 170static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 171static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 172static void wb_mii_sync (struct wb_softc *); 173static void wb_mii_send (struct wb_softc *, u_int32_t, int); 174static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176 177static void wb_setcfg (struct wb_softc *, u_int32_t); 178static void wb_setmulti (struct wb_softc *); 179static void wb_reset (struct wb_softc *); 180static void wb_fixmedia (struct wb_softc *); 181static int wb_list_rx_init (struct wb_softc *); 182static int wb_list_tx_init (struct wb_softc *); 183 184static int wb_miibus_readreg (device_t, int, int); 185static int wb_miibus_writereg (device_t, int, int, int); 186static void wb_miibus_statchg (device_t); 187 188#ifdef WB_USEIOSPACE 189#define WB_RES SYS_RES_IOPORT 190#define WB_RID WB_PCI_LOIO 191#else 192#define WB_RES SYS_RES_MEMORY 193#define WB_RID WB_PCI_LOMEM 194#endif 195 196static device_method_t wb_methods[] = { 197 /* Device interface */ 198 DEVMETHOD(device_probe, wb_probe), 199 DEVMETHOD(device_attach, wb_attach), 200 DEVMETHOD(device_detach, wb_detach), 201 DEVMETHOD(device_shutdown, wb_shutdown), 202 203 /* bus interface, for miibus */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 209 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 210 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 211 { 0, 0 } 212}; 213 214static driver_t wb_driver = { 215 "wb", 216 wb_methods, 217 sizeof(struct wb_softc) 218}; 219 220static devclass_t wb_devclass; 221 222DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 223DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 224 225#define WB_SETBIT(sc, reg, x) \ 226 CSR_WRITE_4(sc, reg, \ 227 CSR_READ_4(sc, reg) | (x)) 228 229#define WB_CLRBIT(sc, reg, x) \ 230 CSR_WRITE_4(sc, reg, \ 231 CSR_READ_4(sc, reg) & ~(x)) 232 233#define SIO_SET(x) \ 234 CSR_WRITE_4(sc, WB_SIO, \ 235 CSR_READ_4(sc, WB_SIO) | (x)) 236 237#define SIO_CLR(x) \ 238 CSR_WRITE_4(sc, WB_SIO, \ 239 CSR_READ_4(sc, WB_SIO) & ~(x)) 240 241/* 242 * Send a read command and address to the EEPROM, check for ACK. 243 */ 244static void 245wb_eeprom_putbyte(sc, addr) 246 struct wb_softc *sc; 247 int addr; 248{ 249 register int d, i; 250 251 d = addr | WB_EECMD_READ; 252 253 /* 254 * Feed in each bit and stobe the clock. 255 */ 256 for (i = 0x400; i; i >>= 1) { 257 if (d & i) { 258 SIO_SET(WB_SIO_EE_DATAIN); 259 } else { 260 SIO_CLR(WB_SIO_EE_DATAIN); 261 } 262 DELAY(100); 263 SIO_SET(WB_SIO_EE_CLK); 264 DELAY(150); 265 SIO_CLR(WB_SIO_EE_CLK); 266 DELAY(100); 267 } 268 269 return; 270} 271 272/* 273 * Read a word of data stored in the EEPROM at address 'addr.' 274 */ 275static void 276wb_eeprom_getword(sc, addr, dest) 277 struct wb_softc *sc; 278 int addr; 279 u_int16_t *dest; 280{ 281 register int i; 282 u_int16_t word = 0; 283 284 /* Enter EEPROM access mode. */ 285 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 286 287 /* 288 * Send address of word we want to read. 289 */ 290 wb_eeprom_putbyte(sc, addr); 291 292 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 293 294 /* 295 * Start reading bits from EEPROM. 296 */ 297 for (i = 0x8000; i; i >>= 1) { 298 SIO_SET(WB_SIO_EE_CLK); 299 DELAY(100); 300 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 301 word |= i; 302 SIO_CLR(WB_SIO_EE_CLK); 303 DELAY(100); 304 } 305 306 /* Turn off EEPROM access mode. */ 307 CSR_WRITE_4(sc, WB_SIO, 0); 308 309 *dest = word; 310 311 return; 312} 313 314/* 315 * Read a sequence of words from the EEPROM. 316 */ 317static void 318wb_read_eeprom(sc, dest, off, cnt, swap) 319 struct wb_softc *sc; 320 caddr_t dest; 321 int off; 322 int cnt; 323 int swap; 324{ 325 int i; 326 u_int16_t word = 0, *ptr; 327 328 for (i = 0; i < cnt; i++) { 329 wb_eeprom_getword(sc, off + i, &word); 330 ptr = (u_int16_t *)(dest + (i * 2)); 331 if (swap) 332 *ptr = ntohs(word); 333 else 334 *ptr = word; 335 } 336 337 return; 338} 339 340/* 341 * Sync the PHYs by setting data bit and strobing the clock 32 times. 342 */ 343static void 344wb_mii_sync(sc) 345 struct wb_softc *sc; 346{ 347 register int i; 348 349 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 350 351 for (i = 0; i < 32; i++) { 352 SIO_SET(WB_SIO_MII_CLK); 353 DELAY(1); 354 SIO_CLR(WB_SIO_MII_CLK); 355 DELAY(1); 356 } 357 358 return; 359} 360 361/* 362 * Clock a series of bits through the MII. 363 */ 364static void 365wb_mii_send(sc, bits, cnt) 366 struct wb_softc *sc; 367 u_int32_t bits; 368 int cnt; 369{ 370 int i; 371 372 SIO_CLR(WB_SIO_MII_CLK); 373 374 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 375 if (bits & i) { 376 SIO_SET(WB_SIO_MII_DATAIN); 377 } else { 378 SIO_CLR(WB_SIO_MII_DATAIN); 379 } 380 DELAY(1); 381 SIO_CLR(WB_SIO_MII_CLK); 382 DELAY(1); 383 SIO_SET(WB_SIO_MII_CLK); 384 } 385} 386 387/* 388 * Read an PHY register through the MII. 389 */ 390static int 391wb_mii_readreg(sc, frame) 392 struct wb_softc *sc; 393 struct wb_mii_frame *frame; 394 395{ 396 int i, ack; 397 398 WB_LOCK(sc); 399 400 /* 401 * Set up frame for RX. 402 */ 403 frame->mii_stdelim = WB_MII_STARTDELIM; 404 frame->mii_opcode = WB_MII_READOP; 405 frame->mii_turnaround = 0; 406 frame->mii_data = 0; 407 408 CSR_WRITE_4(sc, WB_SIO, 0); 409 410 /* 411 * Turn on data xmit. 412 */ 413 SIO_SET(WB_SIO_MII_DIR); 414 415 wb_mii_sync(sc); 416 417 /* 418 * Send command/address info. 419 */ 420 wb_mii_send(sc, frame->mii_stdelim, 2); 421 wb_mii_send(sc, frame->mii_opcode, 2); 422 wb_mii_send(sc, frame->mii_phyaddr, 5); 423 wb_mii_send(sc, frame->mii_regaddr, 5); 424 425 /* Idle bit */ 426 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 427 DELAY(1); 428 SIO_SET(WB_SIO_MII_CLK); 429 DELAY(1); 430 431 /* Turn off xmit. */ 432 SIO_CLR(WB_SIO_MII_DIR); 433 /* Check for ack */ 434 SIO_CLR(WB_SIO_MII_CLK); 435 DELAY(1); 436 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 437 SIO_SET(WB_SIO_MII_CLK); 438 DELAY(1); 439 SIO_CLR(WB_SIO_MII_CLK); 440 DELAY(1); 441 SIO_SET(WB_SIO_MII_CLK); 442 DELAY(1); 443 444 /* 445 * Now try reading data bits. If the ack failed, we still 446 * need to clock through 16 cycles to keep the PHY(s) in sync. 447 */ 448 if (ack) { 449 for(i = 0; i < 16; i++) { 450 SIO_CLR(WB_SIO_MII_CLK); 451 DELAY(1); 452 SIO_SET(WB_SIO_MII_CLK); 453 DELAY(1); 454 } 455 goto fail; 456 } 457 458 for (i = 0x8000; i; i >>= 1) { 459 SIO_CLR(WB_SIO_MII_CLK); 460 DELAY(1); 461 if (!ack) { 462 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 463 frame->mii_data |= i; 464 DELAY(1); 465 } 466 SIO_SET(WB_SIO_MII_CLK); 467 DELAY(1); 468 } 469 470fail: 471 472 SIO_CLR(WB_SIO_MII_CLK); 473 DELAY(1); 474 SIO_SET(WB_SIO_MII_CLK); 475 DELAY(1); 476 477 WB_UNLOCK(sc); 478 479 if (ack) 480 return(1); 481 return(0); 482} 483 484/* 485 * Write to a PHY register through the MII. 486 */ 487static int 488wb_mii_writereg(sc, frame) 489 struct wb_softc *sc; 490 struct wb_mii_frame *frame; 491 492{ 493 WB_LOCK(sc); 494 495 /* 496 * Set up frame for TX. 497 */ 498 499 frame->mii_stdelim = WB_MII_STARTDELIM; 500 frame->mii_opcode = WB_MII_WRITEOP; 501 frame->mii_turnaround = WB_MII_TURNAROUND; 502 503 /* 504 * Turn on data output. 505 */ 506 SIO_SET(WB_SIO_MII_DIR); 507 508 wb_mii_sync(sc); 509 510 wb_mii_send(sc, frame->mii_stdelim, 2); 511 wb_mii_send(sc, frame->mii_opcode, 2); 512 wb_mii_send(sc, frame->mii_phyaddr, 5); 513 wb_mii_send(sc, frame->mii_regaddr, 5); 514 wb_mii_send(sc, frame->mii_turnaround, 2); 515 wb_mii_send(sc, frame->mii_data, 16); 516 517 /* Idle bit. */ 518 SIO_SET(WB_SIO_MII_CLK); 519 DELAY(1); 520 SIO_CLR(WB_SIO_MII_CLK); 521 DELAY(1); 522 523 /* 524 * Turn off xmit. 525 */ 526 SIO_CLR(WB_SIO_MII_DIR); 527 528 WB_UNLOCK(sc); 529 530 return(0); 531} 532 533static int 534wb_miibus_readreg(dev, phy, reg) 535 device_t dev; 536 int phy, reg; 537{ 538 struct wb_softc *sc; 539 struct wb_mii_frame frame; 540 541 sc = device_get_softc(dev); 542 543 bzero((char *)&frame, sizeof(frame)); 544 545 frame.mii_phyaddr = phy; 546 frame.mii_regaddr = reg; 547 wb_mii_readreg(sc, &frame); 548 549 return(frame.mii_data); 550} 551 552static int 553wb_miibus_writereg(dev, phy, reg, data) 554 device_t dev; 555 int phy, reg, data; 556{ 557 struct wb_softc *sc; 558 struct wb_mii_frame frame; 559 560 sc = device_get_softc(dev); 561 562 bzero((char *)&frame, sizeof(frame)); 563 564 frame.mii_phyaddr = phy; 565 frame.mii_regaddr = reg; 566 frame.mii_data = data; 567 568 wb_mii_writereg(sc, &frame); 569 570 return(0); 571} 572 573static void 574wb_miibus_statchg(dev) 575 device_t dev; 576{ 577 struct wb_softc *sc; 578 struct mii_data *mii; 579 580 sc = device_get_softc(dev); 581 WB_LOCK(sc); 582 mii = device_get_softc(sc->wb_miibus); 583 wb_setcfg(sc, mii->mii_media_active); 584 WB_UNLOCK(sc); 585 586 return; 587} 588 589/* 590 * Program the 64-bit multicast hash filter. 591 */ 592static void 593wb_setmulti(sc) 594 struct wb_softc *sc; 595{ 596 struct ifnet *ifp; 597 int h = 0; 598 u_int32_t hashes[2] = { 0, 0 }; 599 struct ifmultiaddr *ifma; 600 u_int32_t rxfilt; 601 int mcnt = 0; 602 603 ifp = &sc->arpcom.ac_if; 604 605 rxfilt = CSR_READ_4(sc, WB_NETCFG); 606 607 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 608 rxfilt |= WB_NETCFG_RX_MULTI; 609 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 610 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 611 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 612 return; 613 } 614 615 /* first, zot all the existing hash bits */ 616 CSR_WRITE_4(sc, WB_MAR0, 0); 617 CSR_WRITE_4(sc, WB_MAR1, 0); 618 619 /* now program new ones */ 620 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 621 if (ifma->ifma_addr->sa_family != AF_LINK) 622 continue; 623 h = ~ether_crc32_be(LLADDR((struct sockaddr_dl *) 624 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 625 if (h < 32) 626 hashes[0] |= (1 << h); 627 else 628 hashes[1] |= (1 << (h - 32)); 629 mcnt++; 630 } 631 632 if (mcnt) 633 rxfilt |= WB_NETCFG_RX_MULTI; 634 else 635 rxfilt &= ~WB_NETCFG_RX_MULTI; 636 637 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 638 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 639 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 640 641 return; 642} 643 644/* 645 * The Winbond manual states that in order to fiddle with the 646 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 647 * first have to put the transmit and/or receive logic in the idle state. 648 */ 649static void 650wb_setcfg(sc, media) 651 struct wb_softc *sc; 652 u_int32_t media; 653{ 654 int i, restart = 0; 655 656 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 657 restart = 1; 658 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 659 660 for (i = 0; i < WB_TIMEOUT; i++) { 661 DELAY(10); 662 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 663 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 664 break; 665 } 666 667 if (i == WB_TIMEOUT) 668 printf("wb%d: failed to force tx and " 669 "rx to idle state\n", sc->wb_unit); 670 } 671 672 if (IFM_SUBTYPE(media) == IFM_10_T) 673 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 674 else 675 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 676 677 if ((media & IFM_GMASK) == IFM_FDX) 678 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 679 else 680 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 681 682 if (restart) 683 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 684 685 return; 686} 687 688static void 689wb_reset(sc) 690 struct wb_softc *sc; 691{ 692 register int i; 693 struct mii_data *mii; 694 695 CSR_WRITE_4(sc, WB_NETCFG, 0); 696 CSR_WRITE_4(sc, WB_BUSCTL, 0); 697 CSR_WRITE_4(sc, WB_TXADDR, 0); 698 CSR_WRITE_4(sc, WB_RXADDR, 0); 699 700 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 701 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 702 703 for (i = 0; i < WB_TIMEOUT; i++) { 704 DELAY(10); 705 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 706 break; 707 } 708 if (i == WB_TIMEOUT) 709 printf("wb%d: reset never completed!\n", sc->wb_unit); 710 711 /* Wait a little while for the chip to get its brains in order. */ 712 DELAY(1000); 713 714 if (sc->wb_miibus == NULL) 715 return; 716 717 mii = device_get_softc(sc->wb_miibus); 718 if (mii == NULL) 719 return; 720 721 if (mii->mii_instance) { 722 struct mii_softc *miisc; 723 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 724 mii_phy_reset(miisc); 725 } 726 727 return; 728} 729 730static void 731wb_fixmedia(sc) 732 struct wb_softc *sc; 733{ 734 struct mii_data *mii = NULL; 735 struct ifnet *ifp; 736 u_int32_t media; 737 738 if (sc->wb_miibus == NULL) 739 return; 740 741 mii = device_get_softc(sc->wb_miibus); 742 ifp = &sc->arpcom.ac_if; 743 744 mii_pollstat(mii); 745 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 746 media = mii->mii_media_active & ~IFM_10_T; 747 media |= IFM_100_TX; 748 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 749 media = mii->mii_media_active & ~IFM_100_TX; 750 media |= IFM_10_T; 751 } else 752 return; 753 754 ifmedia_set(&mii->mii_media, media); 755 756 return; 757} 758 759/* 760 * Probe for a Winbond chip. Check the PCI vendor and device 761 * IDs against our list and return a device name if we find a match. 762 */ 763static int 764wb_probe(dev) 765 device_t dev; 766{ 767 struct wb_type *t; 768 769 t = wb_devs; 770 771 while(t->wb_name != NULL) { 772 if ((pci_get_vendor(dev) == t->wb_vid) && 773 (pci_get_device(dev) == t->wb_did)) { 774 device_set_desc(dev, t->wb_name); 775 return(0); 776 } 777 t++; 778 } 779 780 return(ENXIO); 781} 782 783/* 784 * Attach the interface. Allocate softc structures, do ifmedia 785 * setup and ethernet/BPF attach. 786 */ 787static int 788wb_attach(dev) 789 device_t dev; 790{ 791 u_char eaddr[ETHER_ADDR_LEN]; 792 struct wb_softc *sc; 793 struct ifnet *ifp; 794 int unit, error = 0, rid; 795 796 sc = device_get_softc(dev); 797 unit = device_get_unit(dev); 798 799 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 800 MTX_DEF | MTX_RECURSE); 801#ifndef BURN_BRIDGES 802 /* 803 * Handle power management nonsense. 804 */ 805 806 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 807 u_int32_t iobase, membase, irq; 808 809 /* Save important PCI config data. */ 810 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 811 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 812 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 813 814 /* Reset the power state. */ 815 printf("wb%d: chip is in D%d power mode " 816 "-- setting to D0\n", unit, 817 pci_get_powerstate(dev)); 818 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 819 820 /* Restore PCI config data. */ 821 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 822 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 823 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 824 } 825#endif 826 /* 827 * Map control/status registers. 828 */ 829 pci_enable_busmaster(dev); 830 831 rid = WB_RID; 832 sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 833 834 if (sc->wb_res == NULL) { 835 printf("wb%d: couldn't map ports/memory\n", unit); 836 error = ENXIO; 837 goto fail; 838 } 839 840 sc->wb_btag = rman_get_bustag(sc->wb_res); 841 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 842 843 /* Allocate interrupt */ 844 rid = 0; 845 sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 846 RF_SHAREABLE | RF_ACTIVE); 847 848 if (sc->wb_irq == NULL) { 849 printf("wb%d: couldn't map interrupt\n", unit); 850 error = ENXIO; 851 goto fail; 852 } 853 854 /* Save the cache line size. */ 855 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 856 857 /* Reset the adapter. */ 858 wb_reset(sc); 859 860 /* 861 * Get station address from the EEPROM. 862 */ 863 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 864 865 sc->wb_unit = unit; 866 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 867 868 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 869 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 870 871 if (sc->wb_ldata == NULL) { 872 printf("wb%d: no memory for list buffers!\n", unit); 873 error = ENXIO; 874 goto fail; 875 } 876 877 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 878 879 ifp = &sc->arpcom.ac_if; 880 ifp->if_softc = sc; 881 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 882 ifp->if_mtu = ETHERMTU; 883 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 884 ifp->if_ioctl = wb_ioctl; 885 ifp->if_start = wb_start; 886 ifp->if_watchdog = wb_watchdog; 887 ifp->if_init = wb_init; 888 ifp->if_baudrate = 10000000; 889 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 890 891 /* 892 * Do MII setup. 893 */ 894 if (mii_phy_probe(dev, &sc->wb_miibus, 895 wb_ifmedia_upd, wb_ifmedia_sts)) { 896 error = ENXIO; 897 goto fail; 898 } 899 900 /* 901 * Call MI attach routine. 902 */ 903 ether_ifattach(ifp, eaddr); 904 905 /* Hook interrupt last to avoid having to lock softc */ 906 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 907 wb_intr, sc, &sc->wb_intrhand); 908 909 if (error) { 910 printf("wb%d: couldn't set up irq\n", unit); 911 ether_ifdetach(ifp); 912 goto fail; 913 } 914 915fail: 916 if (error) 917 wb_detach(dev); 918 919 return(error); 920} 921 922/* 923 * Shutdown hardware and free up resources. This can be called any 924 * time after the mutex has been initialized. It is called in both 925 * the error case in attach and the normal detach case so it needs 926 * to be careful about only freeing resources that have actually been 927 * allocated. 928 */ 929static int 930wb_detach(dev) 931 device_t dev; 932{ 933 struct wb_softc *sc; 934 struct ifnet *ifp; 935 936 sc = device_get_softc(dev); 937 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 938 WB_LOCK(sc); 939 ifp = &sc->arpcom.ac_if; 940 941 /* 942 * Delete any miibus and phy devices attached to this interface. 943 * This should only be done if attach succeeded. 944 */ 945 if (device_is_attached(dev)) { 946 wb_stop(sc); 947 ether_ifdetach(ifp); 948 } 949 if (sc->wb_miibus) 950 device_delete_child(dev, sc->wb_miibus); 951 bus_generic_detach(dev); 952 953 if (sc->wb_intrhand) 954 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 955 if (sc->wb_irq) 956 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 957 if (sc->wb_res) 958 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 959 960 if (sc->wb_ldata) { 961 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 962 M_DEVBUF); 963 } 964 965 WB_UNLOCK(sc); 966 mtx_destroy(&sc->wb_mtx); 967 968 return(0); 969} 970 971/* 972 * Initialize the transmit descriptors. 973 */ 974static int 975wb_list_tx_init(sc) 976 struct wb_softc *sc; 977{ 978 struct wb_chain_data *cd; 979 struct wb_list_data *ld; 980 int i; 981 982 cd = &sc->wb_cdata; 983 ld = sc->wb_ldata; 984 985 for (i = 0; i < WB_TX_LIST_CNT; i++) { 986 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 987 if (i == (WB_TX_LIST_CNT - 1)) { 988 cd->wb_tx_chain[i].wb_nextdesc = 989 &cd->wb_tx_chain[0]; 990 } else { 991 cd->wb_tx_chain[i].wb_nextdesc = 992 &cd->wb_tx_chain[i + 1]; 993 } 994 } 995 996 cd->wb_tx_free = &cd->wb_tx_chain[0]; 997 cd->wb_tx_tail = cd->wb_tx_head = NULL; 998 999 return(0); 1000} 1001 1002 1003/* 1004 * Initialize the RX descriptors and allocate mbufs for them. Note that 1005 * we arrange the descriptors in a closed ring, so that the last descriptor 1006 * points back to the first. 1007 */ 1008static int 1009wb_list_rx_init(sc) 1010 struct wb_softc *sc; 1011{ 1012 struct wb_chain_data *cd; 1013 struct wb_list_data *ld; 1014 int i; 1015 1016 cd = &sc->wb_cdata; 1017 ld = sc->wb_ldata; 1018 1019 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1020 cd->wb_rx_chain[i].wb_ptr = 1021 (struct wb_desc *)&ld->wb_rx_list[i]; 1022 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1023 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1024 return(ENOBUFS); 1025 if (i == (WB_RX_LIST_CNT - 1)) { 1026 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1027 ld->wb_rx_list[i].wb_next = 1028 vtophys(&ld->wb_rx_list[0]); 1029 } else { 1030 cd->wb_rx_chain[i].wb_nextdesc = 1031 &cd->wb_rx_chain[i + 1]; 1032 ld->wb_rx_list[i].wb_next = 1033 vtophys(&ld->wb_rx_list[i + 1]); 1034 } 1035 } 1036 1037 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1038 1039 return(0); 1040} 1041 1042static void 1043wb_bfree(buf, args) 1044 void *buf; 1045 void *args; 1046{ 1047 return; 1048} 1049 1050/* 1051 * Initialize an RX descriptor and attach an MBUF cluster. 1052 */ 1053static int 1054wb_newbuf(sc, c, m) 1055 struct wb_softc *sc; 1056 struct wb_chain_onefrag *c; 1057 struct mbuf *m; 1058{ 1059 struct mbuf *m_new = NULL; 1060 1061 if (m == NULL) { 1062 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1063 if (m_new == NULL) 1064 return(ENOBUFS); 1065 m_new->m_data = c->wb_buf; 1066 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1067 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1068 EXT_NET_DRV); 1069 } else { 1070 m_new = m; 1071 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1072 m_new->m_data = m_new->m_ext.ext_buf; 1073 } 1074 1075 m_adj(m_new, sizeof(u_int64_t)); 1076 1077 c->wb_mbuf = m_new; 1078 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1079 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1080 c->wb_ptr->wb_status = WB_RXSTAT; 1081 1082 return(0); 1083} 1084 1085/* 1086 * A frame has been uploaded: pass the resulting mbuf chain up to 1087 * the higher level protocols. 1088 */ 1089static void 1090wb_rxeof(sc) 1091 struct wb_softc *sc; 1092{ 1093 struct mbuf *m = NULL; 1094 struct ifnet *ifp; 1095 struct wb_chain_onefrag *cur_rx; 1096 int total_len = 0; 1097 u_int32_t rxstat; 1098 1099 WB_LOCK_ASSERT(sc); 1100 1101 ifp = &sc->arpcom.ac_if; 1102 1103 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1104 WB_RXSTAT_OWN)) { 1105 struct mbuf *m0 = NULL; 1106 1107 cur_rx = sc->wb_cdata.wb_rx_head; 1108 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1109 1110 m = cur_rx->wb_mbuf; 1111 1112 if ((rxstat & WB_RXSTAT_MIIERR) || 1113 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1114 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1115 !(rxstat & WB_RXSTAT_LASTFRAG) || 1116 !(rxstat & WB_RXSTAT_RXCMP)) { 1117 ifp->if_ierrors++; 1118 wb_newbuf(sc, cur_rx, m); 1119 printf("wb%x: receiver babbling: possible chip " 1120 "bug, forcing reset\n", sc->wb_unit); 1121 wb_fixmedia(sc); 1122 wb_reset(sc); 1123 wb_init(sc); 1124 return; 1125 } 1126 1127 if (rxstat & WB_RXSTAT_RXERR) { 1128 ifp->if_ierrors++; 1129 wb_newbuf(sc, cur_rx, m); 1130 break; 1131 } 1132 1133 /* No errors; receive the packet. */ 1134 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1135 1136 /* 1137 * XXX The Winbond chip includes the CRC with every 1138 * received frame, and there's no way to turn this 1139 * behavior off (at least, I can't find anything in 1140 * the manual that explains how to do it) so we have 1141 * to trim off the CRC manually. 1142 */ 1143 total_len -= ETHER_CRC_LEN; 1144 1145 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1146 NULL); 1147 wb_newbuf(sc, cur_rx, m); 1148 if (m0 == NULL) { 1149 ifp->if_ierrors++; 1150 break; 1151 } 1152 m = m0; 1153 1154 ifp->if_ipackets++; 1155 WB_UNLOCK(sc); 1156 (*ifp->if_input)(ifp, m); 1157 WB_LOCK(sc); 1158 } 1159} 1160 1161static void 1162wb_rxeoc(sc) 1163 struct wb_softc *sc; 1164{ 1165 wb_rxeof(sc); 1166 1167 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1168 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1169 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1170 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1171 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1172 1173 return; 1174} 1175 1176/* 1177 * A frame was downloaded to the chip. It's safe for us to clean up 1178 * the list buffers. 1179 */ 1180static void 1181wb_txeof(sc) 1182 struct wb_softc *sc; 1183{ 1184 struct wb_chain *cur_tx; 1185 struct ifnet *ifp; 1186 1187 ifp = &sc->arpcom.ac_if; 1188 1189 /* Clear the timeout timer. */ 1190 ifp->if_timer = 0; 1191 1192 if (sc->wb_cdata.wb_tx_head == NULL) 1193 return; 1194 1195 /* 1196 * Go through our tx list and free mbufs for those 1197 * frames that have been transmitted. 1198 */ 1199 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1200 u_int32_t txstat; 1201 1202 cur_tx = sc->wb_cdata.wb_tx_head; 1203 txstat = WB_TXSTATUS(cur_tx); 1204 1205 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1206 break; 1207 1208 if (txstat & WB_TXSTAT_TXERR) { 1209 ifp->if_oerrors++; 1210 if (txstat & WB_TXSTAT_ABORT) 1211 ifp->if_collisions++; 1212 if (txstat & WB_TXSTAT_LATECOLL) 1213 ifp->if_collisions++; 1214 } 1215 1216 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1217 1218 ifp->if_opackets++; 1219 m_freem(cur_tx->wb_mbuf); 1220 cur_tx->wb_mbuf = NULL; 1221 1222 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1223 sc->wb_cdata.wb_tx_head = NULL; 1224 sc->wb_cdata.wb_tx_tail = NULL; 1225 break; 1226 } 1227 1228 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1229 } 1230 1231 return; 1232} 1233 1234/* 1235 * TX 'end of channel' interrupt handler. 1236 */ 1237static void 1238wb_txeoc(sc) 1239 struct wb_softc *sc; 1240{ 1241 struct ifnet *ifp; 1242 1243 ifp = &sc->arpcom.ac_if; 1244 1245 ifp->if_timer = 0; 1246 1247 if (sc->wb_cdata.wb_tx_head == NULL) { 1248 ifp->if_flags &= ~IFF_OACTIVE; 1249 sc->wb_cdata.wb_tx_tail = NULL; 1250 } else { 1251 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1252 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1253 ifp->if_timer = 5; 1254 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1255 } 1256 } 1257 1258 return; 1259} 1260 1261static void 1262wb_intr(arg) 1263 void *arg; 1264{ 1265 struct wb_softc *sc; 1266 struct ifnet *ifp; 1267 u_int32_t status; 1268 1269 sc = arg; 1270 WB_LOCK(sc); 1271 ifp = &sc->arpcom.ac_if; 1272 1273 if (!(ifp->if_flags & IFF_UP)) { 1274 WB_UNLOCK(sc); 1275 return; 1276 } 1277 1278 /* Disable interrupts. */ 1279 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1280 1281 for (;;) { 1282 1283 status = CSR_READ_4(sc, WB_ISR); 1284 if (status) 1285 CSR_WRITE_4(sc, WB_ISR, status); 1286 1287 if ((status & WB_INTRS) == 0) 1288 break; 1289 1290 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1291 ifp->if_ierrors++; 1292 wb_reset(sc); 1293 if (status & WB_ISR_RX_ERR) 1294 wb_fixmedia(sc); 1295 wb_init(sc); 1296 continue; 1297 } 1298 1299 if (status & WB_ISR_RX_OK) 1300 wb_rxeof(sc); 1301 1302 if (status & WB_ISR_RX_IDLE) 1303 wb_rxeoc(sc); 1304 1305 if (status & WB_ISR_TX_OK) 1306 wb_txeof(sc); 1307 1308 if (status & WB_ISR_TX_NOBUF) 1309 wb_txeoc(sc); 1310 1311 if (status & WB_ISR_TX_IDLE) { 1312 wb_txeof(sc); 1313 if (sc->wb_cdata.wb_tx_head != NULL) { 1314 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1315 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1316 } 1317 } 1318 1319 if (status & WB_ISR_TX_UNDERRUN) { 1320 ifp->if_oerrors++; 1321 wb_txeof(sc); 1322 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1323 /* Jack up TX threshold */ 1324 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1325 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1326 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1327 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1328 } 1329 1330 if (status & WB_ISR_BUS_ERR) { 1331 wb_reset(sc); 1332 wb_init(sc); 1333 } 1334 1335 } 1336 1337 /* Re-enable interrupts. */ 1338 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1339 1340 if (ifp->if_snd.ifq_head != NULL) { 1341 wb_start(ifp); 1342 } 1343 1344 WB_UNLOCK(sc); 1345 1346 return; 1347} 1348 1349static void 1350wb_tick(xsc) 1351 void *xsc; 1352{ 1353 struct wb_softc *sc; 1354 struct mii_data *mii; 1355 1356 sc = xsc; 1357 WB_LOCK(sc); 1358 mii = device_get_softc(sc->wb_miibus); 1359 1360 mii_tick(mii); 1361 1362 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1363 1364 WB_UNLOCK(sc); 1365 1366 return; 1367} 1368 1369/* 1370 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1371 * pointers to the fragment pointers. 1372 */ 1373static int 1374wb_encap(sc, c, m_head) 1375 struct wb_softc *sc; 1376 struct wb_chain *c; 1377 struct mbuf *m_head; 1378{ 1379 int frag = 0; 1380 struct wb_desc *f = NULL; 1381 int total_len; 1382 struct mbuf *m; 1383 1384 /* 1385 * Start packing the mbufs in this chain into 1386 * the fragment pointers. Stop when we run out 1387 * of fragments or hit the end of the mbuf chain. 1388 */ 1389 m = m_head; 1390 total_len = 0; 1391 1392 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1393 if (m->m_len != 0) { 1394 if (frag == WB_MAXFRAGS) 1395 break; 1396 total_len += m->m_len; 1397 f = &c->wb_ptr->wb_frag[frag]; 1398 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1399 if (frag == 0) { 1400 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1401 f->wb_status = 0; 1402 } else 1403 f->wb_status = WB_TXSTAT_OWN; 1404 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1405 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1406 frag++; 1407 } 1408 } 1409 1410 /* 1411 * Handle special case: we used up all 16 fragments, 1412 * but we have more mbufs left in the chain. Copy the 1413 * data into an mbuf cluster. Note that we don't 1414 * bother clearing the values in the other fragment 1415 * pointers/counters; it wouldn't gain us anything, 1416 * and would waste cycles. 1417 */ 1418 if (m != NULL) { 1419 struct mbuf *m_new = NULL; 1420 1421 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1422 if (m_new == NULL) 1423 return(1); 1424 if (m_head->m_pkthdr.len > MHLEN) { 1425 MCLGET(m_new, M_DONTWAIT); 1426 if (!(m_new->m_flags & M_EXT)) { 1427 m_freem(m_new); 1428 return(1); 1429 } 1430 } 1431 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1432 mtod(m_new, caddr_t)); 1433 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1434 m_freem(m_head); 1435 m_head = m_new; 1436 f = &c->wb_ptr->wb_frag[0]; 1437 f->wb_status = 0; 1438 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1439 f->wb_ctl = total_len = m_new->m_len; 1440 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1441 frag = 1; 1442 } 1443 1444 if (total_len < WB_MIN_FRAMELEN) { 1445 f = &c->wb_ptr->wb_frag[frag]; 1446 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1447 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1448 f->wb_ctl |= WB_TXCTL_TLINK; 1449 f->wb_status = WB_TXSTAT_OWN; 1450 frag++; 1451 } 1452 1453 c->wb_mbuf = m_head; 1454 c->wb_lastdesc = frag - 1; 1455 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1456 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1457 1458 return(0); 1459} 1460 1461/* 1462 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1463 * to the mbuf data regions directly in the transmit lists. We also save a 1464 * copy of the pointers since the transmit list fragment pointers are 1465 * physical addresses. 1466 */ 1467 1468static void 1469wb_start(ifp) 1470 struct ifnet *ifp; 1471{ 1472 struct wb_softc *sc; 1473 struct mbuf *m_head = NULL; 1474 struct wb_chain *cur_tx = NULL, *start_tx; 1475 1476 sc = ifp->if_softc; 1477 WB_LOCK(sc); 1478 1479 /* 1480 * Check for an available queue slot. If there are none, 1481 * punt. 1482 */ 1483 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1484 ifp->if_flags |= IFF_OACTIVE; 1485 WB_UNLOCK(sc); 1486 return; 1487 } 1488 1489 start_tx = sc->wb_cdata.wb_tx_free; 1490 1491 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1492 IF_DEQUEUE(&ifp->if_snd, m_head); 1493 if (m_head == NULL) 1494 break; 1495 1496 /* Pick a descriptor off the free list. */ 1497 cur_tx = sc->wb_cdata.wb_tx_free; 1498 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1499 1500 /* Pack the data into the descriptor. */ 1501 wb_encap(sc, cur_tx, m_head); 1502 1503 if (cur_tx != start_tx) 1504 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1505 1506 /* 1507 * If there's a BPF listener, bounce a copy of this frame 1508 * to him. 1509 */ 1510 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1511 } 1512 1513 /* 1514 * If there are no packets queued, bail. 1515 */ 1516 if (cur_tx == NULL) { 1517 WB_UNLOCK(sc); 1518 return; 1519 } 1520 1521 /* 1522 * Place the request for the upload interrupt 1523 * in the last descriptor in the chain. This way, if 1524 * we're chaining several packets at once, we'll only 1525 * get an interupt once for the whole chain rather than 1526 * once for each packet. 1527 */ 1528 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1529 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1530 sc->wb_cdata.wb_tx_tail = cur_tx; 1531 1532 if (sc->wb_cdata.wb_tx_head == NULL) { 1533 sc->wb_cdata.wb_tx_head = start_tx; 1534 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1535 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1536 } else { 1537 /* 1538 * We need to distinguish between the case where 1539 * the own bit is clear because the chip cleared it 1540 * and where the own bit is clear because we haven't 1541 * set it yet. The magic value WB_UNSET is just some 1542 * ramdomly chosen number which doesn't have the own 1543 * bit set. When we actually transmit the frame, the 1544 * status word will have _only_ the own bit set, so 1545 * the txeoc handler will be able to tell if it needs 1546 * to initiate another transmission to flush out pending 1547 * frames. 1548 */ 1549 WB_TXOWN(start_tx) = WB_UNSENT; 1550 } 1551 1552 /* 1553 * Set a timeout in case the chip goes out to lunch. 1554 */ 1555 ifp->if_timer = 5; 1556 WB_UNLOCK(sc); 1557 1558 return; 1559} 1560 1561static void 1562wb_init(xsc) 1563 void *xsc; 1564{ 1565 struct wb_softc *sc = xsc; 1566 struct ifnet *ifp = &sc->arpcom.ac_if; 1567 int i; 1568 struct mii_data *mii; 1569 1570 WB_LOCK(sc); 1571 mii = device_get_softc(sc->wb_miibus); 1572 1573 /* 1574 * Cancel pending I/O and free all RX/TX buffers. 1575 */ 1576 wb_stop(sc); 1577 wb_reset(sc); 1578 1579 sc->wb_txthresh = WB_TXTHRESH_INIT; 1580 1581 /* 1582 * Set cache alignment and burst length. 1583 */ 1584#ifdef foo 1585 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1586 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1587 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1588#endif 1589 1590 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1591 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1592 switch(sc->wb_cachesize) { 1593 case 32: 1594 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1595 break; 1596 case 16: 1597 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1598 break; 1599 case 8: 1600 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1601 break; 1602 case 0: 1603 default: 1604 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1605 break; 1606 } 1607 1608 /* This doesn't tend to work too well at 100Mbps. */ 1609 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1610 1611 /* Init our MAC address */ 1612 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1613 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1614 } 1615 1616 /* Init circular RX list. */ 1617 if (wb_list_rx_init(sc) == ENOBUFS) { 1618 printf("wb%d: initialization failed: no " 1619 "memory for rx buffers\n", sc->wb_unit); 1620 wb_stop(sc); 1621 WB_UNLOCK(sc); 1622 return; 1623 } 1624 1625 /* Init TX descriptors. */ 1626 wb_list_tx_init(sc); 1627 1628 /* If we want promiscuous mode, set the allframes bit. */ 1629 if (ifp->if_flags & IFF_PROMISC) { 1630 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1631 } else { 1632 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1633 } 1634 1635 /* 1636 * Set capture broadcast bit to capture broadcast frames. 1637 */ 1638 if (ifp->if_flags & IFF_BROADCAST) { 1639 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1640 } else { 1641 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1642 } 1643 1644 /* 1645 * Program the multicast filter, if necessary. 1646 */ 1647 wb_setmulti(sc); 1648 1649 /* 1650 * Load the address of the RX list. 1651 */ 1652 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1653 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1654 1655 /* 1656 * Enable interrupts. 1657 */ 1658 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1659 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1660 1661 /* Enable receiver and transmitter. */ 1662 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1663 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1664 1665 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1666 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1667 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1668 1669 mii_mediachg(mii); 1670 1671 ifp->if_flags |= IFF_RUNNING; 1672 ifp->if_flags &= ~IFF_OACTIVE; 1673 1674 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1675 WB_UNLOCK(sc); 1676 1677 return; 1678} 1679 1680/* 1681 * Set media options. 1682 */ 1683static int 1684wb_ifmedia_upd(ifp) 1685 struct ifnet *ifp; 1686{ 1687 struct wb_softc *sc; 1688 1689 sc = ifp->if_softc; 1690 1691 if (ifp->if_flags & IFF_UP) 1692 wb_init(sc); 1693 1694 return(0); 1695} 1696 1697/* 1698 * Report current media status. 1699 */ 1700static void 1701wb_ifmedia_sts(ifp, ifmr) 1702 struct ifnet *ifp; 1703 struct ifmediareq *ifmr; 1704{ 1705 struct wb_softc *sc; 1706 struct mii_data *mii; 1707 1708 sc = ifp->if_softc; 1709 1710 mii = device_get_softc(sc->wb_miibus); 1711 1712 mii_pollstat(mii); 1713 ifmr->ifm_active = mii->mii_media_active; 1714 ifmr->ifm_status = mii->mii_media_status; 1715 1716 return; 1717} 1718 1719static int 1720wb_ioctl(ifp, command, data) 1721 struct ifnet *ifp; 1722 u_long command; 1723 caddr_t data; 1724{ 1725 struct wb_softc *sc = ifp->if_softc; 1726 struct mii_data *mii; 1727 struct ifreq *ifr = (struct ifreq *) data; 1728 int error = 0; 1729 1730 WB_LOCK(sc); 1731 1732 switch(command) { 1733 case SIOCSIFFLAGS: 1734 if (ifp->if_flags & IFF_UP) { 1735 wb_init(sc); 1736 } else { 1737 if (ifp->if_flags & IFF_RUNNING) 1738 wb_stop(sc); 1739 } 1740 error = 0; 1741 break; 1742 case SIOCADDMULTI: 1743 case SIOCDELMULTI: 1744 wb_setmulti(sc); 1745 error = 0; 1746 break; 1747 case SIOCGIFMEDIA: 1748 case SIOCSIFMEDIA: 1749 mii = device_get_softc(sc->wb_miibus); 1750 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1751 break; 1752 default: 1753 error = ether_ioctl(ifp, command, data); 1754 break; 1755 } 1756 1757 WB_UNLOCK(sc); 1758 1759 return(error); 1760} 1761 1762static void 1763wb_watchdog(ifp) 1764 struct ifnet *ifp; 1765{ 1766 struct wb_softc *sc; 1767 1768 sc = ifp->if_softc; 1769 1770 WB_LOCK(sc); 1771 ifp->if_oerrors++; 1772 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1773#ifdef foo 1774 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1775 printf("wb%d: no carrier - transceiver cable problem?\n", 1776 sc->wb_unit); 1777#endif 1778 wb_stop(sc); 1779 wb_reset(sc); 1780 wb_init(sc); 1781 1782 if (ifp->if_snd.ifq_head != NULL) 1783 wb_start(ifp); 1784 WB_UNLOCK(sc); 1785 1786 return; 1787} 1788 1789/* 1790 * Stop the adapter and free any mbufs allocated to the 1791 * RX and TX lists. 1792 */ 1793static void 1794wb_stop(sc) 1795 struct wb_softc *sc; 1796{ 1797 register int i; 1798 struct ifnet *ifp; 1799 1800 WB_LOCK(sc); 1801 ifp = &sc->arpcom.ac_if; 1802 ifp->if_timer = 0; 1803 1804 untimeout(wb_tick, sc, sc->wb_stat_ch); 1805 1806 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1807 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1808 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1809 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1810 1811 /* 1812 * Free data in the RX lists. 1813 */ 1814 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1815 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1816 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1817 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1818 } 1819 } 1820 bzero((char *)&sc->wb_ldata->wb_rx_list, 1821 sizeof(sc->wb_ldata->wb_rx_list)); 1822 1823 /* 1824 * Free the TX list buffers. 1825 */ 1826 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1827 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1828 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1829 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1830 } 1831 } 1832 1833 bzero((char *)&sc->wb_ldata->wb_tx_list, 1834 sizeof(sc->wb_ldata->wb_tx_list)); 1835 1836 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1837 WB_UNLOCK(sc); 1838 1839 return; 1840} 1841 1842/* 1843 * Stop all chip I/O so that the kernel's probe routines don't 1844 * get confused by errant DMAs when rebooting. 1845 */ 1846static void 1847wb_shutdown(dev) 1848 device_t dev; 1849{ 1850 struct wb_softc *sc; 1851 1852 sc = device_get_softc(dev); 1853 wb_stop(sc); 1854 1855 return; 1856} 1857