if_wb.c revision 127135
141502Swpaul/* 241502Swpaul * Copyright (c) 1997, 1998 341502Swpaul * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 441502Swpaul * 541502Swpaul * Redistribution and use in source and binary forms, with or without 641502Swpaul * modification, are permitted provided that the following conditions 741502Swpaul * are met: 841502Swpaul * 1. Redistributions of source code must retain the above copyright 941502Swpaul * notice, this list of conditions and the following disclaimer. 1041502Swpaul * 2. Redistributions in binary form must reproduce the above copyright 1141502Swpaul * notice, this list of conditions and the following disclaimer in the 1241502Swpaul * documentation and/or other materials provided with the distribution. 1341502Swpaul * 3. All advertising materials mentioning features or use of this software 1441502Swpaul * must display the following acknowledgement: 1541502Swpaul * This product includes software developed by Bill Paul. 1641502Swpaul * 4. Neither the name of the author nor the names of any co-contributors 1741502Swpaul * may be used to endorse or promote products derived from this software 1841502Swpaul * without specific prior written permission. 1941502Swpaul * 2041502Swpaul * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2141502Swpaul * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2241502Swpaul * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2341502Swpaul * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2441502Swpaul * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2541502Swpaul * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2641502Swpaul * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2741502Swpaul * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2841502Swpaul * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2941502Swpaul * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3041502Swpaul * THE POSSIBILITY OF SUCH DAMAGE. 3141502Swpaul */ 3241502Swpaul 33122678Sobrien#include <sys/cdefs.h> 34122678Sobrien__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 127135 2004-03-17 17:50:55Z njl $"); 35122678Sobrien 3641502Swpaul/* 3741502Swpaul * Winbond fast ethernet PCI NIC driver 3841502Swpaul * 3941502Swpaul * Supports various cheap network adapters based on the Winbond W89C840F 4041502Swpaul * fast ethernet controller chip. This includes adapters manufactured by 4141502Swpaul * Winbond itself and some made by Linksys. 4241502Swpaul * 4341502Swpaul * Written by Bill Paul <wpaul@ctr.columbia.edu> 4441502Swpaul * Electrical Engineering Department 4541502Swpaul * Columbia University, New York City 4641502Swpaul */ 4741502Swpaul/* 4841502Swpaul * The Winbond W89C840F chip is a bus master; in some ways it resembles 4941502Swpaul * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 5041502Swpaul * one major difference which is that while the registers do many of 5141502Swpaul * the same things as a tulip adapter, the offsets are different: where 5241502Swpaul * tulip registers are typically spaced 8 bytes apart, the Winbond 5341502Swpaul * registers are spaced 4 bytes apart. The receiver filter is also 5441502Swpaul * programmed differently. 5541502Swpaul * 5641502Swpaul * Like the tulip, the Winbond chip uses small descriptors containing 5741502Swpaul * a status word, a control word and 32-bit areas that can either be used 5841502Swpaul * to point to two external data blocks, or to point to a single block 5941502Swpaul * and another descriptor in a linked list. Descriptors can be grouped 6041502Swpaul * together in blocks to form fixed length rings or can be chained 6141502Swpaul * together in linked lists. A single packet may be spread out over 6241502Swpaul * several descriptors if necessary. 6341502Swpaul * 6441502Swpaul * For the receive ring, this driver uses a linked list of descriptors, 6541502Swpaul * each pointing to a single mbuf cluster buffer, which us large enough 6641502Swpaul * to hold an entire packet. The link list is looped back to created a 6741502Swpaul * closed ring. 6841502Swpaul * 6941502Swpaul * For transmission, the driver creates a linked list of 'super descriptors' 7041502Swpaul * which each contain several individual descriptors linked toghether. 7141502Swpaul * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 7241502Swpaul * abuse as fragment pointers. This allows us to use a buffer managment 7341502Swpaul * scheme very similar to that used in the ThunderLAN and Etherlink XL 7441502Swpaul * drivers. 7541502Swpaul * 7641502Swpaul * Autonegotiation is performed using the external PHY via the MII bus. 7741502Swpaul * The sample boards I have all use a Davicom PHY. 7841502Swpaul * 7941502Swpaul * Note: the author of the Linux driver for the Winbond chip alludes 8041502Swpaul * to some sort of flaw in the chip's design that seems to mandate some 8141502Swpaul * drastic workaround which signigicantly impairs transmit performance. 8241502Swpaul * I have no idea what he's on about: transmit performance with all 8341502Swpaul * three of my test boards seems fine. 8441502Swpaul */ 8541502Swpaul 8648745Swpaul#include "opt_bdg.h" 8741502Swpaul 8841502Swpaul#include <sys/param.h> 8941502Swpaul#include <sys/systm.h> 9041502Swpaul#include <sys/sockio.h> 9141502Swpaul#include <sys/mbuf.h> 9241502Swpaul#include <sys/malloc.h> 9341502Swpaul#include <sys/kernel.h> 9441502Swpaul#include <sys/socket.h> 9550675Swpaul#include <sys/queue.h> 9641502Swpaul 9741502Swpaul#include <net/if.h> 9841502Swpaul#include <net/if_arp.h> 9941502Swpaul#include <net/ethernet.h> 10041502Swpaul#include <net/if_dl.h> 10141502Swpaul#include <net/if_media.h> 10241502Swpaul 10341502Swpaul#include <net/bpf.h> 10441502Swpaul 10541502Swpaul#include <vm/vm.h> /* for vtophys */ 10641502Swpaul#include <vm/pmap.h> /* for vtophys */ 10741502Swpaul#include <machine/bus_memio.h> 10841502Swpaul#include <machine/bus_pio.h> 10941502Swpaul#include <machine/bus.h> 11049611Swpaul#include <machine/resource.h> 11149611Swpaul#include <sys/bus.h> 11249611Swpaul#include <sys/rman.h> 11341502Swpaul 114119288Simp#include <dev/pci/pcireg.h> 115119288Simp#include <dev/pci/pcivar.h> 11641502Swpaul 11750675Swpaul#include <dev/mii/mii.h> 11850675Swpaul#include <dev/mii/miivar.h> 11950675Swpaul 12051089Speter/* "controller miibus0" required. See GENERIC if you get errors here. */ 12150675Swpaul#include "miibus_if.h" 12250675Swpaul 12341502Swpaul#define WB_USEIOSPACE 12441502Swpaul 12541502Swpaul#include <pci/if_wbreg.h> 12641502Swpaul 127113506SmdoddMODULE_DEPEND(wb, pci, 1, 1, 1); 128113506SmdoddMODULE_DEPEND(wb, ether, 1, 1, 1); 12959758SpeterMODULE_DEPEND(wb, miibus, 1, 1, 1); 13059758Speter 13141502Swpaul/* 13241502Swpaul * Various supported device vendors/types and their names. 13341502Swpaul */ 13441502Swpaulstatic struct wb_type wb_devs[] = { 13541502Swpaul { WB_VENDORID, WB_DEVICEID_840F, 13641502Swpaul "Winbond W89C840F 10/100BaseTX" }, 13741502Swpaul { CP_VENDORID, CP_DEVICEID_RL100, 13841502Swpaul "Compex RL100-ATX 10/100baseTX" }, 13941502Swpaul { 0, 0, NULL } 14041502Swpaul}; 14141502Swpaul 14292739Salfredstatic int wb_probe (device_t); 14392739Salfredstatic int wb_attach (device_t); 14492739Salfredstatic int wb_detach (device_t); 14541502Swpaul 14698995Salfredstatic void wb_bfree (void *addr, void *args); 14792739Salfredstatic int wb_newbuf (struct wb_softc *, 14848745Swpaul struct wb_chain_onefrag *, 14992739Salfred struct mbuf *); 15092739Salfredstatic int wb_encap (struct wb_softc *, struct wb_chain *, 15192739Salfred struct mbuf *); 15241502Swpaul 15392739Salfredstatic void wb_rxeof (struct wb_softc *); 15492739Salfredstatic void wb_rxeoc (struct wb_softc *); 15592739Salfredstatic void wb_txeof (struct wb_softc *); 15692739Salfredstatic void wb_txeoc (struct wb_softc *); 15792739Salfredstatic void wb_intr (void *); 15892739Salfredstatic void wb_tick (void *); 15992739Salfredstatic void wb_start (struct ifnet *); 16092739Salfredstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 16192739Salfredstatic void wb_init (void *); 16292739Salfredstatic void wb_stop (struct wb_softc *); 16392739Salfredstatic void wb_watchdog (struct ifnet *); 16492739Salfredstatic void wb_shutdown (device_t); 16592739Salfredstatic int wb_ifmedia_upd (struct ifnet *); 16692739Salfredstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 16741502Swpaul 16892739Salfredstatic void wb_eeprom_putbyte (struct wb_softc *, int); 16992739Salfredstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 17092739Salfredstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 17192739Salfredstatic void wb_mii_sync (struct wb_softc *); 17292739Salfredstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 17392739Salfredstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 17492739Salfredstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 17541502Swpaul 17692739Salfredstatic void wb_setcfg (struct wb_softc *, u_int32_t); 177123289Sobrienstatic uint32_t wb_mchash (const uint8_t *); 17892739Salfredstatic void wb_setmulti (struct wb_softc *); 17992739Salfredstatic void wb_reset (struct wb_softc *); 18092739Salfredstatic void wb_fixmedia (struct wb_softc *); 18192739Salfredstatic int wb_list_rx_init (struct wb_softc *); 18292739Salfredstatic int wb_list_tx_init (struct wb_softc *); 18341502Swpaul 18492739Salfredstatic int wb_miibus_readreg (device_t, int, int); 18592739Salfredstatic int wb_miibus_writereg (device_t, int, int, int); 18692739Salfredstatic void wb_miibus_statchg (device_t); 18750675Swpaul 18849611Swpaul#ifdef WB_USEIOSPACE 18949611Swpaul#define WB_RES SYS_RES_IOPORT 19049611Swpaul#define WB_RID WB_PCI_LOIO 19149611Swpaul#else 19249611Swpaul#define WB_RES SYS_RES_MEMORY 19349611Swpaul#define WB_RID WB_PCI_LOMEM 19449611Swpaul#endif 19549611Swpaul 19649611Swpaulstatic device_method_t wb_methods[] = { 19749611Swpaul /* Device interface */ 19849611Swpaul DEVMETHOD(device_probe, wb_probe), 19949611Swpaul DEVMETHOD(device_attach, wb_attach), 20049611Swpaul DEVMETHOD(device_detach, wb_detach), 20149611Swpaul DEVMETHOD(device_shutdown, wb_shutdown), 20250675Swpaul 20350675Swpaul /* bus interface, for miibus */ 20450675Swpaul DEVMETHOD(bus_print_child, bus_generic_print_child), 20550675Swpaul DEVMETHOD(bus_driver_added, bus_generic_driver_added), 20650675Swpaul 20750675Swpaul /* MII interface */ 20850675Swpaul DEVMETHOD(miibus_readreg, wb_miibus_readreg), 20950675Swpaul DEVMETHOD(miibus_writereg, wb_miibus_writereg), 21050675Swpaul DEVMETHOD(miibus_statchg, wb_miibus_statchg), 21149611Swpaul { 0, 0 } 21249611Swpaul}; 21349611Swpaul 21449611Swpaulstatic driver_t wb_driver = { 21551455Swpaul "wb", 21649611Swpaul wb_methods, 21749611Swpaul sizeof(struct wb_softc) 21849611Swpaul}; 21949611Swpaul 22049611Swpaulstatic devclass_t wb_devclass; 22149611Swpaul 222113506SmdoddDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 22351473SwpaulDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 22449611Swpaul 22541502Swpaul#define WB_SETBIT(sc, reg, x) \ 22641502Swpaul CSR_WRITE_4(sc, reg, \ 227105221Sphk CSR_READ_4(sc, reg) | (x)) 22841502Swpaul 22941502Swpaul#define WB_CLRBIT(sc, reg, x) \ 23041502Swpaul CSR_WRITE_4(sc, reg, \ 231105221Sphk CSR_READ_4(sc, reg) & ~(x)) 23241502Swpaul 23341502Swpaul#define SIO_SET(x) \ 23441502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 235105221Sphk CSR_READ_4(sc, WB_SIO) | (x)) 23641502Swpaul 23741502Swpaul#define SIO_CLR(x) \ 23841502Swpaul CSR_WRITE_4(sc, WB_SIO, \ 239105221Sphk CSR_READ_4(sc, WB_SIO) & ~(x)) 24041502Swpaul 24141502Swpaul/* 24241502Swpaul * Send a read command and address to the EEPROM, check for ACK. 24341502Swpaul */ 244102336Salfredstatic void 245102336Salfredwb_eeprom_putbyte(sc, addr) 24641502Swpaul struct wb_softc *sc; 24742718Swpaul int addr; 24841502Swpaul{ 24941502Swpaul register int d, i; 25041502Swpaul 25141502Swpaul d = addr | WB_EECMD_READ; 25241502Swpaul 25341502Swpaul /* 25441502Swpaul * Feed in each bit and stobe the clock. 25541502Swpaul */ 25641502Swpaul for (i = 0x400; i; i >>= 1) { 25741502Swpaul if (d & i) { 25841502Swpaul SIO_SET(WB_SIO_EE_DATAIN); 25941502Swpaul } else { 26041502Swpaul SIO_CLR(WB_SIO_EE_DATAIN); 26141502Swpaul } 26241502Swpaul DELAY(100); 26341502Swpaul SIO_SET(WB_SIO_EE_CLK); 26441502Swpaul DELAY(150); 26541502Swpaul SIO_CLR(WB_SIO_EE_CLK); 26641502Swpaul DELAY(100); 26741502Swpaul } 26841502Swpaul 26941502Swpaul return; 27041502Swpaul} 27141502Swpaul 27241502Swpaul/* 27341502Swpaul * Read a word of data stored in the EEPROM at address 'addr.' 27441502Swpaul */ 275102336Salfredstatic void 276102336Salfredwb_eeprom_getword(sc, addr, dest) 27741502Swpaul struct wb_softc *sc; 27842718Swpaul int addr; 27941502Swpaul u_int16_t *dest; 28041502Swpaul{ 28141502Swpaul register int i; 28241502Swpaul u_int16_t word = 0; 28341502Swpaul 28441502Swpaul /* Enter EEPROM access mode. */ 28541502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 28641502Swpaul 28741502Swpaul /* 28841502Swpaul * Send address of word we want to read. 28941502Swpaul */ 29041502Swpaul wb_eeprom_putbyte(sc, addr); 29141502Swpaul 29241502Swpaul CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 29341502Swpaul 29441502Swpaul /* 29541502Swpaul * Start reading bits from EEPROM. 29641502Swpaul */ 29741502Swpaul for (i = 0x8000; i; i >>= 1) { 29841502Swpaul SIO_SET(WB_SIO_EE_CLK); 29941502Swpaul DELAY(100); 30041502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 30141502Swpaul word |= i; 30241502Swpaul SIO_CLR(WB_SIO_EE_CLK); 30341502Swpaul DELAY(100); 30441502Swpaul } 30541502Swpaul 30641502Swpaul /* Turn off EEPROM access mode. */ 30741502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 30841502Swpaul 30941502Swpaul *dest = word; 31041502Swpaul 31141502Swpaul return; 31241502Swpaul} 31341502Swpaul 31441502Swpaul/* 31541502Swpaul * Read a sequence of words from the EEPROM. 31641502Swpaul */ 317102336Salfredstatic void 318102336Salfredwb_read_eeprom(sc, dest, off, cnt, swap) 31941502Swpaul struct wb_softc *sc; 32041502Swpaul caddr_t dest; 32141502Swpaul int off; 32241502Swpaul int cnt; 32341502Swpaul int swap; 32441502Swpaul{ 32541502Swpaul int i; 32641502Swpaul u_int16_t word = 0, *ptr; 32741502Swpaul 32841502Swpaul for (i = 0; i < cnt; i++) { 32941502Swpaul wb_eeprom_getword(sc, off + i, &word); 33041502Swpaul ptr = (u_int16_t *)(dest + (i * 2)); 33141502Swpaul if (swap) 33241502Swpaul *ptr = ntohs(word); 33341502Swpaul else 33441502Swpaul *ptr = word; 33541502Swpaul } 33641502Swpaul 33741502Swpaul return; 33841502Swpaul} 33941502Swpaul 34041502Swpaul/* 34141502Swpaul * Sync the PHYs by setting data bit and strobing the clock 32 times. 34241502Swpaul */ 343102336Salfredstatic void 344102336Salfredwb_mii_sync(sc) 34541502Swpaul struct wb_softc *sc; 34641502Swpaul{ 34741502Swpaul register int i; 34841502Swpaul 34941502Swpaul SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 35041502Swpaul 35141502Swpaul for (i = 0; i < 32; i++) { 35241502Swpaul SIO_SET(WB_SIO_MII_CLK); 35341502Swpaul DELAY(1); 35441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 35541502Swpaul DELAY(1); 35641502Swpaul } 35741502Swpaul 35841502Swpaul return; 35941502Swpaul} 36041502Swpaul 36141502Swpaul/* 36241502Swpaul * Clock a series of bits through the MII. 36341502Swpaul */ 364102336Salfredstatic void 365102336Salfredwb_mii_send(sc, bits, cnt) 36641502Swpaul struct wb_softc *sc; 36741502Swpaul u_int32_t bits; 36841502Swpaul int cnt; 36941502Swpaul{ 37041502Swpaul int i; 37141502Swpaul 37241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 37341502Swpaul 37441502Swpaul for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 37541502Swpaul if (bits & i) { 37641502Swpaul SIO_SET(WB_SIO_MII_DATAIN); 37741502Swpaul } else { 37841502Swpaul SIO_CLR(WB_SIO_MII_DATAIN); 37941502Swpaul } 38041502Swpaul DELAY(1); 38141502Swpaul SIO_CLR(WB_SIO_MII_CLK); 38241502Swpaul DELAY(1); 38341502Swpaul SIO_SET(WB_SIO_MII_CLK); 38441502Swpaul } 38541502Swpaul} 38641502Swpaul 38741502Swpaul/* 38841502Swpaul * Read an PHY register through the MII. 38941502Swpaul */ 390102336Salfredstatic int 391102336Salfredwb_mii_readreg(sc, frame) 39241502Swpaul struct wb_softc *sc; 39341502Swpaul struct wb_mii_frame *frame; 39441502Swpaul 39541502Swpaul{ 39667087Swpaul int i, ack; 39741502Swpaul 39867087Swpaul WB_LOCK(sc); 39941502Swpaul 40041502Swpaul /* 40141502Swpaul * Set up frame for RX. 40241502Swpaul */ 40341502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 40441502Swpaul frame->mii_opcode = WB_MII_READOP; 40541502Swpaul frame->mii_turnaround = 0; 40641502Swpaul frame->mii_data = 0; 40741502Swpaul 40841502Swpaul CSR_WRITE_4(sc, WB_SIO, 0); 40941502Swpaul 41041502Swpaul /* 41141502Swpaul * Turn on data xmit. 41241502Swpaul */ 41341502Swpaul SIO_SET(WB_SIO_MII_DIR); 41441502Swpaul 41541502Swpaul wb_mii_sync(sc); 41641502Swpaul 41741502Swpaul /* 41841502Swpaul * Send command/address info. 41941502Swpaul */ 42041502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 42141502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 42241502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 42341502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 42441502Swpaul 42541502Swpaul /* Idle bit */ 42641502Swpaul SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 42741502Swpaul DELAY(1); 42841502Swpaul SIO_SET(WB_SIO_MII_CLK); 42941502Swpaul DELAY(1); 43041502Swpaul 43141502Swpaul /* Turn off xmit. */ 43241502Swpaul SIO_CLR(WB_SIO_MII_DIR); 43341502Swpaul /* Check for ack */ 43441502Swpaul SIO_CLR(WB_SIO_MII_CLK); 43541502Swpaul DELAY(1); 436109058Smbr ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 43741502Swpaul SIO_SET(WB_SIO_MII_CLK); 43841502Swpaul DELAY(1); 43941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 44041502Swpaul DELAY(1); 44141502Swpaul SIO_SET(WB_SIO_MII_CLK); 44241502Swpaul DELAY(1); 44341502Swpaul 44441502Swpaul /* 44541502Swpaul * Now try reading data bits. If the ack failed, we still 44641502Swpaul * need to clock through 16 cycles to keep the PHY(s) in sync. 44741502Swpaul */ 44841502Swpaul if (ack) { 44941502Swpaul for(i = 0; i < 16; i++) { 45041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 45141502Swpaul DELAY(1); 45241502Swpaul SIO_SET(WB_SIO_MII_CLK); 45341502Swpaul DELAY(1); 45441502Swpaul } 45541502Swpaul goto fail; 45641502Swpaul } 45741502Swpaul 45841502Swpaul for (i = 0x8000; i; i >>= 1) { 45941502Swpaul SIO_CLR(WB_SIO_MII_CLK); 46041502Swpaul DELAY(1); 46141502Swpaul if (!ack) { 46241502Swpaul if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 46341502Swpaul frame->mii_data |= i; 46441502Swpaul DELAY(1); 46541502Swpaul } 46641502Swpaul SIO_SET(WB_SIO_MII_CLK); 46741502Swpaul DELAY(1); 46841502Swpaul } 46941502Swpaul 47041502Swpaulfail: 47141502Swpaul 47241502Swpaul SIO_CLR(WB_SIO_MII_CLK); 47341502Swpaul DELAY(1); 47441502Swpaul SIO_SET(WB_SIO_MII_CLK); 47541502Swpaul DELAY(1); 47641502Swpaul 47767087Swpaul WB_UNLOCK(sc); 47841502Swpaul 47941502Swpaul if (ack) 48041502Swpaul return(1); 48141502Swpaul return(0); 48241502Swpaul} 48341502Swpaul 48441502Swpaul/* 48541502Swpaul * Write to a PHY register through the MII. 48641502Swpaul */ 487102336Salfredstatic int 488102336Salfredwb_mii_writereg(sc, frame) 48941502Swpaul struct wb_softc *sc; 49041502Swpaul struct wb_mii_frame *frame; 49141502Swpaul 49241502Swpaul{ 49367087Swpaul WB_LOCK(sc); 49441502Swpaul 49541502Swpaul /* 49641502Swpaul * Set up frame for TX. 49741502Swpaul */ 49841502Swpaul 49941502Swpaul frame->mii_stdelim = WB_MII_STARTDELIM; 50041502Swpaul frame->mii_opcode = WB_MII_WRITEOP; 50141502Swpaul frame->mii_turnaround = WB_MII_TURNAROUND; 50241502Swpaul 50341502Swpaul /* 50441502Swpaul * Turn on data output. 50541502Swpaul */ 50641502Swpaul SIO_SET(WB_SIO_MII_DIR); 50741502Swpaul 50841502Swpaul wb_mii_sync(sc); 50941502Swpaul 51041502Swpaul wb_mii_send(sc, frame->mii_stdelim, 2); 51141502Swpaul wb_mii_send(sc, frame->mii_opcode, 2); 51241502Swpaul wb_mii_send(sc, frame->mii_phyaddr, 5); 51341502Swpaul wb_mii_send(sc, frame->mii_regaddr, 5); 51441502Swpaul wb_mii_send(sc, frame->mii_turnaround, 2); 51541502Swpaul wb_mii_send(sc, frame->mii_data, 16); 51641502Swpaul 51741502Swpaul /* Idle bit. */ 51841502Swpaul SIO_SET(WB_SIO_MII_CLK); 51941502Swpaul DELAY(1); 52041502Swpaul SIO_CLR(WB_SIO_MII_CLK); 52141502Swpaul DELAY(1); 52241502Swpaul 52341502Swpaul /* 52441502Swpaul * Turn off xmit. 52541502Swpaul */ 52641502Swpaul SIO_CLR(WB_SIO_MII_DIR); 52741502Swpaul 52867087Swpaul WB_UNLOCK(sc); 52941502Swpaul 53041502Swpaul return(0); 53141502Swpaul} 53241502Swpaul 533102336Salfredstatic int 534102336Salfredwb_miibus_readreg(dev, phy, reg) 53550675Swpaul device_t dev; 53650675Swpaul int phy, reg; 53750675Swpaul{ 53841502Swpaul struct wb_softc *sc; 53941502Swpaul struct wb_mii_frame frame; 54041502Swpaul 54150675Swpaul sc = device_get_softc(dev); 54250675Swpaul 54341502Swpaul bzero((char *)&frame, sizeof(frame)); 54441502Swpaul 54550675Swpaul frame.mii_phyaddr = phy; 54641502Swpaul frame.mii_regaddr = reg; 54741502Swpaul wb_mii_readreg(sc, &frame); 54841502Swpaul 54941502Swpaul return(frame.mii_data); 55041502Swpaul} 55141502Swpaul 552102336Salfredstatic int 553102336Salfredwb_miibus_writereg(dev, phy, reg, data) 55450675Swpaul device_t dev; 55550675Swpaul int phy, reg, data; 55650675Swpaul{ 55741502Swpaul struct wb_softc *sc; 55841502Swpaul struct wb_mii_frame frame; 55941502Swpaul 56050675Swpaul sc = device_get_softc(dev); 56150675Swpaul 56241502Swpaul bzero((char *)&frame, sizeof(frame)); 56341502Swpaul 56450675Swpaul frame.mii_phyaddr = phy; 56541502Swpaul frame.mii_regaddr = reg; 56641502Swpaul frame.mii_data = data; 56741502Swpaul 56841502Swpaul wb_mii_writereg(sc, &frame); 56941502Swpaul 57050675Swpaul return(0); 57150675Swpaul} 57250675Swpaul 573102336Salfredstatic void 574102336Salfredwb_miibus_statchg(dev) 57550675Swpaul device_t dev; 57650675Swpaul{ 57750675Swpaul struct wb_softc *sc; 57850675Swpaul struct mii_data *mii; 57950675Swpaul 58050675Swpaul sc = device_get_softc(dev); 58167087Swpaul WB_LOCK(sc); 58250675Swpaul mii = device_get_softc(sc->wb_miibus); 58350675Swpaul wb_setcfg(sc, mii->mii_media_active); 58467087Swpaul WB_UNLOCK(sc); 58550675Swpaul 58641502Swpaul return; 58741502Swpaul} 58841502Swpaul 589122625Sobrienstatic u_int32_t 590122625Sobrienwb_mchash(addr) 591123289Sobrien const uint8_t *addr; 59241502Swpaul{ 593123289Sobrien uint32_t crc, carry; 594123289Sobrien int idx, bit; 595123289Sobrien uint8_t data; 59641502Swpaul 59741502Swpaul /* Compute CRC for the address value. */ 59841502Swpaul crc = 0xFFFFFFFF; /* initial value */ 59941502Swpaul 600122625Sobrien for (idx = 0; idx < 6; idx++) { 601122625Sobrien for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 602122625Sobrien carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 60341502Swpaul crc <<= 1; 60441502Swpaul if (carry) 60541502Swpaul crc = (crc ^ 0x04c11db6) | carry; 60641502Swpaul } 60741502Swpaul } 60841502Swpaul 60941502Swpaul /* 61041502Swpaul * return the filter bit position 61141502Swpaul * Note: I arrived at the following nonsense 61241502Swpaul * through experimentation. It's not the usual way to 61341502Swpaul * generate the bit position but it's the only thing 61441502Swpaul * I could come up with that works. 61541502Swpaul */ 61641502Swpaul return(~(crc >> 26) & 0x0000003F); 61741502Swpaul} 61841502Swpaul 61941502Swpaul/* 62041502Swpaul * Program the 64-bit multicast hash filter. 62141502Swpaul */ 622102336Salfredstatic void 623102336Salfredwb_setmulti(sc) 62441502Swpaul struct wb_softc *sc; 62541502Swpaul{ 62641502Swpaul struct ifnet *ifp; 62741502Swpaul int h = 0; 62841502Swpaul u_int32_t hashes[2] = { 0, 0 }; 62941502Swpaul struct ifmultiaddr *ifma; 63041502Swpaul u_int32_t rxfilt; 63141502Swpaul int mcnt = 0; 63241502Swpaul 63341502Swpaul ifp = &sc->arpcom.ac_if; 63441502Swpaul 63541502Swpaul rxfilt = CSR_READ_4(sc, WB_NETCFG); 63641502Swpaul 63741502Swpaul if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 63841502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 63941502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 64041502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 64141502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 64241502Swpaul return; 64341502Swpaul } 64441502Swpaul 64541502Swpaul /* first, zot all the existing hash bits */ 64641502Swpaul CSR_WRITE_4(sc, WB_MAR0, 0); 64741502Swpaul CSR_WRITE_4(sc, WB_MAR1, 0); 64841502Swpaul 64941502Swpaul /* now program new ones */ 65072084Sphk TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 65141502Swpaul if (ifma->ifma_addr->sa_family != AF_LINK) 65241502Swpaul continue; 653122625Sobrien h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 65441502Swpaul if (h < 32) 65541502Swpaul hashes[0] |= (1 << h); 65641502Swpaul else 65741502Swpaul hashes[1] |= (1 << (h - 32)); 65841502Swpaul mcnt++; 65941502Swpaul } 66041502Swpaul 66141502Swpaul if (mcnt) 66241502Swpaul rxfilt |= WB_NETCFG_RX_MULTI; 66341502Swpaul else 66441502Swpaul rxfilt &= ~WB_NETCFG_RX_MULTI; 66541502Swpaul 66641502Swpaul CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 66741502Swpaul CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 66841502Swpaul CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 66941502Swpaul 67041502Swpaul return; 67141502Swpaul} 67241502Swpaul 67341502Swpaul/* 67441502Swpaul * The Winbond manual states that in order to fiddle with the 67541502Swpaul * 'full-duplex' and '100Mbps' bits in the netconfig register, we 67641502Swpaul * first have to put the transmit and/or receive logic in the idle state. 67741502Swpaul */ 678102336Salfredstatic void 679102336Salfredwb_setcfg(sc, media) 68041502Swpaul struct wb_softc *sc; 68150675Swpaul u_int32_t media; 68241502Swpaul{ 68341502Swpaul int i, restart = 0; 68441502Swpaul 68541502Swpaul if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 68641502Swpaul restart = 1; 68741502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 68841502Swpaul 68941502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 69041502Swpaul DELAY(10); 69141502Swpaul if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 69241502Swpaul (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 69341502Swpaul break; 69441502Swpaul } 69541502Swpaul 69641502Swpaul if (i == WB_TIMEOUT) 69741502Swpaul printf("wb%d: failed to force tx and " 69841502Swpaul "rx to idle state\n", sc->wb_unit); 69941502Swpaul } 70041502Swpaul 70150675Swpaul if (IFM_SUBTYPE(media) == IFM_10_T) 70250675Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70350675Swpaul else 70441502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 70541502Swpaul 70650675Swpaul if ((media & IFM_GMASK) == IFM_FDX) 70741502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 70841502Swpaul else 70941502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 71041502Swpaul 71141502Swpaul if (restart) 71241502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 71341502Swpaul 71441502Swpaul return; 71541502Swpaul} 71641502Swpaul 717102336Salfredstatic void 718102336Salfredwb_reset(sc) 71941502Swpaul struct wb_softc *sc; 72041502Swpaul{ 72141502Swpaul register int i; 72250675Swpaul struct mii_data *mii; 72341502Swpaul 72450675Swpaul CSR_WRITE_4(sc, WB_NETCFG, 0); 72550675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, 0); 72650675Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0); 72750675Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0); 72850675Swpaul 72941502Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 73141502Swpaul 73241502Swpaul for (i = 0; i < WB_TIMEOUT; i++) { 73341502Swpaul DELAY(10); 73441502Swpaul if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 73541502Swpaul break; 73641502Swpaul } 73741502Swpaul if (i == WB_TIMEOUT) 73841502Swpaul printf("wb%d: reset never completed!\n", sc->wb_unit); 73941502Swpaul 74041502Swpaul /* Wait a little while for the chip to get its brains in order. */ 74141502Swpaul DELAY(1000); 74241502Swpaul 74350675Swpaul if (sc->wb_miibus == NULL) 74450675Swpaul return; 74541502Swpaul 74650675Swpaul mii = device_get_softc(sc->wb_miibus); 74750675Swpaul if (mii == NULL) 74850675Swpaul return; 74950675Swpaul 75050675Swpaul if (mii->mii_instance) { 75150675Swpaul struct mii_softc *miisc; 75272012Sphk LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 75350675Swpaul mii_phy_reset(miisc); 75450675Swpaul } 75550675Swpaul 75641502Swpaul return; 75741502Swpaul} 75841502Swpaul 759102336Salfredstatic void 760102336Salfredwb_fixmedia(sc) 76150675Swpaul struct wb_softc *sc; 76250675Swpaul{ 76350675Swpaul struct mii_data *mii = NULL; 76450675Swpaul struct ifnet *ifp; 76550675Swpaul u_int32_t media; 76650675Swpaul 76750675Swpaul if (sc->wb_miibus == NULL) 76850675Swpaul return; 76950675Swpaul 77050675Swpaul mii = device_get_softc(sc->wb_miibus); 77150675Swpaul ifp = &sc->arpcom.ac_if; 77250675Swpaul 77350675Swpaul mii_pollstat(mii); 77450675Swpaul if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 77550675Swpaul media = mii->mii_media_active & ~IFM_10_T; 77650675Swpaul media |= IFM_100_TX; 77750675Swpaul } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 77850675Swpaul media = mii->mii_media_active & ~IFM_100_TX; 77950675Swpaul media |= IFM_10_T; 78050675Swpaul } else 78150675Swpaul return; 78250675Swpaul 78350675Swpaul ifmedia_set(&mii->mii_media, media); 78450675Swpaul 78550675Swpaul return; 78650675Swpaul} 78750675Swpaul 78841502Swpaul/* 78941502Swpaul * Probe for a Winbond chip. Check the PCI vendor and device 79041502Swpaul * IDs against our list and return a device name if we find a match. 79141502Swpaul */ 792102336Salfredstatic int 793102336Salfredwb_probe(dev) 79449611Swpaul device_t dev; 79541502Swpaul{ 79641502Swpaul struct wb_type *t; 79741502Swpaul 79841502Swpaul t = wb_devs; 79941502Swpaul 80041502Swpaul while(t->wb_name != NULL) { 80149611Swpaul if ((pci_get_vendor(dev) == t->wb_vid) && 80249611Swpaul (pci_get_device(dev) == t->wb_did)) { 80349611Swpaul device_set_desc(dev, t->wb_name); 80449611Swpaul return(0); 80541502Swpaul } 80641502Swpaul t++; 80741502Swpaul } 80841502Swpaul 80949611Swpaul return(ENXIO); 81041502Swpaul} 81141502Swpaul 81241502Swpaul/* 81341502Swpaul * Attach the interface. Allocate softc structures, do ifmedia 81441502Swpaul * setup and ethernet/BPF attach. 81541502Swpaul */ 816102336Salfredstatic int 817102336Salfredwb_attach(dev) 81849611Swpaul device_t dev; 81941502Swpaul{ 82041502Swpaul u_char eaddr[ETHER_ADDR_LEN]; 82141502Swpaul struct wb_softc *sc; 82241502Swpaul struct ifnet *ifp; 82349611Swpaul int unit, error = 0, rid; 82441502Swpaul 82549611Swpaul sc = device_get_softc(dev); 82649611Swpaul unit = device_get_unit(dev); 82741502Swpaul 82893818Sjhb mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 82993818Sjhb MTX_DEF | MTX_RECURSE); 830117208Simp#ifndef BURN_BRIDGES 83141502Swpaul /* 83241502Swpaul * Handle power management nonsense. 83341502Swpaul */ 83441502Swpaul 83572813Swpaul if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 83672813Swpaul u_int32_t iobase, membase, irq; 83741502Swpaul 83872813Swpaul /* Save important PCI config data. */ 83972813Swpaul iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 84072813Swpaul membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 84172813Swpaul irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 84241502Swpaul 84372813Swpaul /* Reset the power state. */ 84472813Swpaul printf("wb%d: chip is in D%d power mode " 84572813Swpaul "-- setting to D0\n", unit, 84672813Swpaul pci_get_powerstate(dev)); 84772813Swpaul pci_set_powerstate(dev, PCI_POWERSTATE_D0); 84841502Swpaul 84972813Swpaul /* Restore PCI config data. */ 85072813Swpaul pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 85172813Swpaul pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 85272813Swpaul pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 85341502Swpaul } 854117208Simp#endif 85541502Swpaul /* 85641502Swpaul * Map control/status registers. 85741502Swpaul */ 85872813Swpaul pci_enable_busmaster(dev); 85941502Swpaul 86049611Swpaul rid = WB_RID; 861127135Snjl sc->wb_res = bus_alloc_resource_any(dev, WB_RES, &rid, RF_ACTIVE); 86249611Swpaul 86349611Swpaul if (sc->wb_res == NULL) { 86449611Swpaul printf("wb%d: couldn't map ports/memory\n", unit); 86549611Swpaul error = ENXIO; 86641502Swpaul goto fail; 86741502Swpaul } 86841502Swpaul 86949611Swpaul sc->wb_btag = rman_get_bustag(sc->wb_res); 87049611Swpaul sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 87149611Swpaul 87241502Swpaul /* Allocate interrupt */ 87349611Swpaul rid = 0; 874127135Snjl sc->wb_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 87549611Swpaul RF_SHAREABLE | RF_ACTIVE); 87649611Swpaul 87749611Swpaul if (sc->wb_irq == NULL) { 87841502Swpaul printf("wb%d: couldn't map interrupt\n", unit); 87949611Swpaul error = ENXIO; 88041502Swpaul goto fail; 88141502Swpaul } 88241502Swpaul 88350675Swpaul /* Save the cache line size. */ 88450675Swpaul sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 88550675Swpaul 88641502Swpaul /* Reset the adapter. */ 88741502Swpaul wb_reset(sc); 88841502Swpaul 88941502Swpaul /* 89041502Swpaul * Get station address from the EEPROM. 89141502Swpaul */ 89241502Swpaul wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 89341502Swpaul 89441502Swpaul sc->wb_unit = unit; 89541502Swpaul bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 89641502Swpaul 89750675Swpaul sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 89851657Swpaul M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 89950675Swpaul 90050675Swpaul if (sc->wb_ldata == NULL) { 90141502Swpaul printf("wb%d: no memory for list buffers!\n", unit); 90249611Swpaul error = ENXIO; 90349611Swpaul goto fail; 90441502Swpaul } 90541502Swpaul 90641502Swpaul bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 90741502Swpaul 90841502Swpaul ifp = &sc->arpcom.ac_if; 90941502Swpaul ifp->if_softc = sc; 910121816Sbrooks if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 91141502Swpaul ifp->if_mtu = ETHERMTU; 91241502Swpaul ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 91341502Swpaul ifp->if_ioctl = wb_ioctl; 91441502Swpaul ifp->if_start = wb_start; 91541502Swpaul ifp->if_watchdog = wb_watchdog; 91641502Swpaul ifp->if_init = wb_init; 91741502Swpaul ifp->if_baudrate = 10000000; 91843515Swpaul ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 91941502Swpaul 92050675Swpaul /* 92150675Swpaul * Do MII setup. 92250675Swpaul */ 92350675Swpaul if (mii_phy_probe(dev, &sc->wb_miibus, 92450675Swpaul wb_ifmedia_upd, wb_ifmedia_sts)) { 92549611Swpaul error = ENXIO; 92641502Swpaul goto fail; 92741502Swpaul } 92841502Swpaul 92941502Swpaul /* 93063090Sarchie * Call MI attach routine. 93141502Swpaul */ 932106936Ssam ether_ifattach(ifp, eaddr); 93341502Swpaul 934113609Snjl /* Hook interrupt last to avoid having to lock softc */ 935112872Snjl error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 936112872Snjl wb_intr, sc, &sc->wb_intrhand); 937112872Snjl 938112872Snjl if (error) { 939112872Snjl printf("wb%d: couldn't set up irq\n", unit); 940113609Snjl ether_ifdetach(ifp); 941112872Snjl goto fail; 942112872Snjl } 943112872Snjl 94441502Swpaulfail: 94550675Swpaul if (error) 946112872Snjl wb_detach(dev); 94750675Swpaul 94849611Swpaul return(error); 94941502Swpaul} 95041502Swpaul 951113609Snjl/* 952113609Snjl * Shutdown hardware and free up resources. This can be called any 953113609Snjl * time after the mutex has been initialized. It is called in both 954113609Snjl * the error case in attach and the normal detach case so it needs 955113609Snjl * to be careful about only freeing resources that have actually been 956113609Snjl * allocated. 957113609Snjl */ 958102336Salfredstatic int 959102336Salfredwb_detach(dev) 96049611Swpaul device_t dev; 96149611Swpaul{ 96249611Swpaul struct wb_softc *sc; 96349611Swpaul struct ifnet *ifp; 96449611Swpaul 96549611Swpaul sc = device_get_softc(dev); 966112880Sjhb KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 96767087Swpaul WB_LOCK(sc); 96849611Swpaul ifp = &sc->arpcom.ac_if; 96949611Swpaul 970113609Snjl /* 971113609Snjl * Delete any miibus and phy devices attached to this interface. 972113609Snjl * This should only be done if attach succeeded. 973113609Snjl */ 974113812Simp if (device_is_attached(dev)) { 975113609Snjl wb_stop(sc); 976112872Snjl ether_ifdetach(ifp); 977113609Snjl } 978113609Snjl if (sc->wb_miibus) 979112872Snjl device_delete_child(dev, sc->wb_miibus); 980113609Snjl bus_generic_detach(dev); 98150675Swpaul 982112872Snjl if (sc->wb_intrhand) 983112872Snjl bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 984112872Snjl if (sc->wb_irq) 985112872Snjl bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 986112872Snjl if (sc->wb_res) 987112872Snjl bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 98849611Swpaul 989112872Snjl if (sc->wb_ldata) { 990112872Snjl contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 991112872Snjl M_DEVBUF); 992112872Snjl } 99349611Swpaul 99467087Swpaul WB_UNLOCK(sc); 99567087Swpaul mtx_destroy(&sc->wb_mtx); 99649611Swpaul 99749611Swpaul return(0); 99849611Swpaul} 99949611Swpaul 100041502Swpaul/* 100141502Swpaul * Initialize the transmit descriptors. 100241502Swpaul */ 1003102336Salfredstatic int 1004102336Salfredwb_list_tx_init(sc) 100541502Swpaul struct wb_softc *sc; 100641502Swpaul{ 100741502Swpaul struct wb_chain_data *cd; 100841502Swpaul struct wb_list_data *ld; 100941502Swpaul int i; 101041502Swpaul 101141502Swpaul cd = &sc->wb_cdata; 101241502Swpaul ld = sc->wb_ldata; 101341502Swpaul 101441502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 101541502Swpaul cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 101641502Swpaul if (i == (WB_TX_LIST_CNT - 1)) { 101741502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 101841502Swpaul &cd->wb_tx_chain[0]; 101941502Swpaul } else { 102041502Swpaul cd->wb_tx_chain[i].wb_nextdesc = 102141502Swpaul &cd->wb_tx_chain[i + 1]; 102241502Swpaul } 102341502Swpaul } 102441502Swpaul 102541502Swpaul cd->wb_tx_free = &cd->wb_tx_chain[0]; 102641502Swpaul cd->wb_tx_tail = cd->wb_tx_head = NULL; 102741502Swpaul 102841502Swpaul return(0); 102941502Swpaul} 103041502Swpaul 103141502Swpaul 103241502Swpaul/* 103341502Swpaul * Initialize the RX descriptors and allocate mbufs for them. Note that 103441502Swpaul * we arrange the descriptors in a closed ring, so that the last descriptor 103541502Swpaul * points back to the first. 103641502Swpaul */ 1037102336Salfredstatic int 1038102336Salfredwb_list_rx_init(sc) 103941502Swpaul struct wb_softc *sc; 104041502Swpaul{ 104141502Swpaul struct wb_chain_data *cd; 104241502Swpaul struct wb_list_data *ld; 104341502Swpaul int i; 104441502Swpaul 104541502Swpaul cd = &sc->wb_cdata; 104641502Swpaul ld = sc->wb_ldata; 104741502Swpaul 104841502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 104941502Swpaul cd->wb_rx_chain[i].wb_ptr = 105041502Swpaul (struct wb_desc *)&ld->wb_rx_list[i]; 105150675Swpaul cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 105248745Swpaul if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 105341502Swpaul return(ENOBUFS); 105441502Swpaul if (i == (WB_RX_LIST_CNT - 1)) { 105541502Swpaul cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 105641502Swpaul ld->wb_rx_list[i].wb_next = 105741502Swpaul vtophys(&ld->wb_rx_list[0]); 105841502Swpaul } else { 105941502Swpaul cd->wb_rx_chain[i].wb_nextdesc = 106041502Swpaul &cd->wb_rx_chain[i + 1]; 106141502Swpaul ld->wb_rx_list[i].wb_next = 106241502Swpaul vtophys(&ld->wb_rx_list[i + 1]); 106341502Swpaul } 106441502Swpaul } 106541502Swpaul 106641502Swpaul cd->wb_rx_head = &cd->wb_rx_chain[0]; 106741502Swpaul 106841502Swpaul return(0); 106941502Swpaul} 107041502Swpaul 1071102336Salfredstatic void 1072102336Salfredwb_bfree(buf, args) 107398995Salfred void *buf; 107464837Sdwmalone void *args; 107550675Swpaul{ 107650675Swpaul return; 107750675Swpaul} 107850675Swpaul 107941502Swpaul/* 108041502Swpaul * Initialize an RX descriptor and attach an MBUF cluster. 108141502Swpaul */ 1082102336Salfredstatic int 1083102336Salfredwb_newbuf(sc, c, m) 108441502Swpaul struct wb_softc *sc; 108541502Swpaul struct wb_chain_onefrag *c; 108648745Swpaul struct mbuf *m; 108741502Swpaul{ 108841502Swpaul struct mbuf *m_new = NULL; 108941502Swpaul 109048745Swpaul if (m == NULL) { 1091111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 109287846Sluigi if (m_new == NULL) 109348745Swpaul return(ENOBUFS); 109464837Sdwmalone m_new->m_data = c->wb_buf; 109564837Sdwmalone m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 109668621Sbmilekic MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 109768621Sbmilekic EXT_NET_DRV); 109848745Swpaul } else { 109948745Swpaul m_new = m; 110050675Swpaul m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 110148745Swpaul m_new->m_data = m_new->m_ext.ext_buf; 110241502Swpaul } 110341502Swpaul 110448745Swpaul m_adj(m_new, sizeof(u_int64_t)); 110548745Swpaul 110641502Swpaul c->wb_mbuf = m_new; 110741502Swpaul c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 110850675Swpaul c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 110941502Swpaul c->wb_ptr->wb_status = WB_RXSTAT; 111041502Swpaul 111141502Swpaul return(0); 111241502Swpaul} 111341502Swpaul 111441502Swpaul/* 111541502Swpaul * A frame has been uploaded: pass the resulting mbuf chain up to 111641502Swpaul * the higher level protocols. 111741502Swpaul */ 1118102336Salfredstatic void 1119102336Salfredwb_rxeof(sc) 112041502Swpaul struct wb_softc *sc; 112141502Swpaul{ 112250675Swpaul struct mbuf *m = NULL; 112341502Swpaul struct ifnet *ifp; 112441502Swpaul struct wb_chain_onefrag *cur_rx; 112541502Swpaul int total_len = 0; 112641502Swpaul u_int32_t rxstat; 112741502Swpaul 1128122689Ssam WB_LOCK_ASSERT(sc); 1129122689Ssam 113041502Swpaul ifp = &sc->arpcom.ac_if; 113141502Swpaul 113241502Swpaul while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 113341502Swpaul WB_RXSTAT_OWN)) { 113448745Swpaul struct mbuf *m0 = NULL; 113548745Swpaul 113641502Swpaul cur_rx = sc->wb_cdata.wb_rx_head; 113741502Swpaul sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 113850675Swpaul 113948745Swpaul m = cur_rx->wb_mbuf; 114041502Swpaul 114150675Swpaul if ((rxstat & WB_RXSTAT_MIIERR) || 114250675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 114350675Swpaul (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 114450675Swpaul !(rxstat & WB_RXSTAT_LASTFRAG) || 114550675Swpaul !(rxstat & WB_RXSTAT_RXCMP)) { 114641502Swpaul ifp->if_ierrors++; 114750675Swpaul wb_newbuf(sc, cur_rx, m); 114841502Swpaul printf("wb%x: receiver babbling: possible chip " 114941502Swpaul "bug, forcing reset\n", sc->wb_unit); 115050675Swpaul wb_fixmedia(sc); 115150675Swpaul wb_reset(sc); 115250675Swpaul wb_init(sc); 115341502Swpaul return; 115441502Swpaul } 115541502Swpaul 115642718Swpaul if (rxstat & WB_RXSTAT_RXERR) { 115742718Swpaul ifp->if_ierrors++; 115848745Swpaul wb_newbuf(sc, cur_rx, m); 115950675Swpaul break; 116042718Swpaul } 116142718Swpaul 116241502Swpaul /* No errors; receive the packet. */ 116341502Swpaul total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 116441502Swpaul 116541502Swpaul /* 116641934Swpaul * XXX The Winbond chip includes the CRC with every 116741934Swpaul * received frame, and there's no way to turn this 116841934Swpaul * behavior off (at least, I can't find anything in 116941934Swpaul * the manual that explains how to do it) so we have 117041934Swpaul * to trim off the CRC manually. 117141934Swpaul */ 117241934Swpaul total_len -= ETHER_CRC_LEN; 117341934Swpaul 117478508Sbmilekic m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 117578508Sbmilekic NULL); 117648745Swpaul wb_newbuf(sc, cur_rx, m); 117748745Swpaul if (m0 == NULL) { 117848745Swpaul ifp->if_ierrors++; 117950675Swpaul break; 118041502Swpaul } 118148745Swpaul m = m0; 118241502Swpaul 118341502Swpaul ifp->if_ipackets++; 1184122689Ssam WB_UNLOCK(sc); 1185106936Ssam (*ifp->if_input)(ifp, m); 1186122689Ssam WB_LOCK(sc); 118741502Swpaul } 118841502Swpaul} 118941502Swpaul 1190105221Sphkstatic void 1191102336Salfredwb_rxeoc(sc) 119241502Swpaul struct wb_softc *sc; 119341502Swpaul{ 119441502Swpaul wb_rxeof(sc); 119541502Swpaul 119641502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 119741502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 119841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 119941502Swpaul if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 120041502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 120141502Swpaul 120241502Swpaul return; 120341502Swpaul} 120441502Swpaul 120541502Swpaul/* 120641502Swpaul * A frame was downloaded to the chip. It's safe for us to clean up 120741502Swpaul * the list buffers. 120841502Swpaul */ 1209102336Salfredstatic void 1210102336Salfredwb_txeof(sc) 121141502Swpaul struct wb_softc *sc; 121241502Swpaul{ 121341502Swpaul struct wb_chain *cur_tx; 121441502Swpaul struct ifnet *ifp; 121541502Swpaul 121641502Swpaul ifp = &sc->arpcom.ac_if; 121741502Swpaul 121841502Swpaul /* Clear the timeout timer. */ 121941502Swpaul ifp->if_timer = 0; 122041502Swpaul 122141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) 122241502Swpaul return; 122341502Swpaul 122441502Swpaul /* 122541502Swpaul * Go through our tx list and free mbufs for those 122641502Swpaul * frames that have been transmitted. 122741502Swpaul */ 122841502Swpaul while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 122941502Swpaul u_int32_t txstat; 123041502Swpaul 123141502Swpaul cur_tx = sc->wb_cdata.wb_tx_head; 123241502Swpaul txstat = WB_TXSTATUS(cur_tx); 123341502Swpaul 123441502Swpaul if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 123541502Swpaul break; 123641502Swpaul 123741502Swpaul if (txstat & WB_TXSTAT_TXERR) { 123841502Swpaul ifp->if_oerrors++; 123941502Swpaul if (txstat & WB_TXSTAT_ABORT) 124041502Swpaul ifp->if_collisions++; 124141502Swpaul if (txstat & WB_TXSTAT_LATECOLL) 124241502Swpaul ifp->if_collisions++; 124341502Swpaul } 124441502Swpaul 124541502Swpaul ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 124641502Swpaul 124741502Swpaul ifp->if_opackets++; 124841502Swpaul m_freem(cur_tx->wb_mbuf); 124941502Swpaul cur_tx->wb_mbuf = NULL; 125041502Swpaul 125141502Swpaul if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 125241502Swpaul sc->wb_cdata.wb_tx_head = NULL; 125341502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 125441502Swpaul break; 125541502Swpaul } 125641502Swpaul 125741502Swpaul sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 125841502Swpaul } 125941502Swpaul 126041502Swpaul return; 126141502Swpaul} 126241502Swpaul 126341502Swpaul/* 126441502Swpaul * TX 'end of channel' interrupt handler. 126541502Swpaul */ 1266102336Salfredstatic void 1267102336Salfredwb_txeoc(sc) 126841502Swpaul struct wb_softc *sc; 126941502Swpaul{ 127041502Swpaul struct ifnet *ifp; 127141502Swpaul 127241502Swpaul ifp = &sc->arpcom.ac_if; 127341502Swpaul 127441502Swpaul ifp->if_timer = 0; 127541502Swpaul 127641502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 127741502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 127841502Swpaul sc->wb_cdata.wb_tx_tail = NULL; 127941502Swpaul } else { 128041502Swpaul if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 128141502Swpaul WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 128241502Swpaul ifp->if_timer = 5; 128341502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 128441502Swpaul } 128541502Swpaul } 128641502Swpaul 128741502Swpaul return; 128841502Swpaul} 128941502Swpaul 1290102336Salfredstatic void 1291102336Salfredwb_intr(arg) 129241502Swpaul void *arg; 129341502Swpaul{ 129441502Swpaul struct wb_softc *sc; 129541502Swpaul struct ifnet *ifp; 129641502Swpaul u_int32_t status; 129741502Swpaul 129841502Swpaul sc = arg; 129967087Swpaul WB_LOCK(sc); 130041502Swpaul ifp = &sc->arpcom.ac_if; 130141502Swpaul 130267087Swpaul if (!(ifp->if_flags & IFF_UP)) { 130367087Swpaul WB_UNLOCK(sc); 130441502Swpaul return; 130567087Swpaul } 130641502Swpaul 130741502Swpaul /* Disable interrupts. */ 130841502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 130941502Swpaul 131041502Swpaul for (;;) { 131141502Swpaul 131241502Swpaul status = CSR_READ_4(sc, WB_ISR); 131341502Swpaul if (status) 131441502Swpaul CSR_WRITE_4(sc, WB_ISR, status); 131541502Swpaul 131641502Swpaul if ((status & WB_INTRS) == 0) 131741502Swpaul break; 131841502Swpaul 131941502Swpaul if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 132041502Swpaul ifp->if_ierrors++; 132141502Swpaul wb_reset(sc); 132250675Swpaul if (status & WB_ISR_RX_ERR) 132350675Swpaul wb_fixmedia(sc); 132441502Swpaul wb_init(sc); 132550675Swpaul continue; 132641502Swpaul } 132741502Swpaul 132850675Swpaul if (status & WB_ISR_RX_OK) 132950675Swpaul wb_rxeof(sc); 133050675Swpaul 133150675Swpaul if (status & WB_ISR_RX_IDLE) 133250675Swpaul wb_rxeoc(sc); 133350675Swpaul 133441502Swpaul if (status & WB_ISR_TX_OK) 133541502Swpaul wb_txeof(sc); 133641502Swpaul 133741502Swpaul if (status & WB_ISR_TX_NOBUF) 133841502Swpaul wb_txeoc(sc); 133941502Swpaul 134041502Swpaul if (status & WB_ISR_TX_IDLE) { 134141502Swpaul wb_txeof(sc); 134241502Swpaul if (sc->wb_cdata.wb_tx_head != NULL) { 134341502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 134441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 134541502Swpaul } 134641502Swpaul } 134741502Swpaul 134841502Swpaul if (status & WB_ISR_TX_UNDERRUN) { 134941502Swpaul ifp->if_oerrors++; 135041502Swpaul wb_txeof(sc); 135141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135241502Swpaul /* Jack up TX threshold */ 135341502Swpaul sc->wb_txthresh += WB_TXTHRESH_CHUNK; 135441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 135541502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 135641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 135741502Swpaul } 135841502Swpaul 135941502Swpaul if (status & WB_ISR_BUS_ERR) { 136041502Swpaul wb_reset(sc); 136141502Swpaul wb_init(sc); 136241502Swpaul } 136341502Swpaul 136441502Swpaul } 136541502Swpaul 136641502Swpaul /* Re-enable interrupts. */ 136741502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 136841502Swpaul 136941502Swpaul if (ifp->if_snd.ifq_head != NULL) { 137041502Swpaul wb_start(ifp); 137141502Swpaul } 137241502Swpaul 137367087Swpaul WB_UNLOCK(sc); 137467087Swpaul 137541502Swpaul return; 137641502Swpaul} 137741502Swpaul 1378102336Salfredstatic void 1379102336Salfredwb_tick(xsc) 138050675Swpaul void *xsc; 138150675Swpaul{ 138250675Swpaul struct wb_softc *sc; 138350675Swpaul struct mii_data *mii; 138450675Swpaul 138550675Swpaul sc = xsc; 138667087Swpaul WB_LOCK(sc); 138750675Swpaul mii = device_get_softc(sc->wb_miibus); 138850675Swpaul 138950675Swpaul mii_tick(mii); 139050675Swpaul 139150675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 139250675Swpaul 139367087Swpaul WB_UNLOCK(sc); 139450685Swpaul 139550675Swpaul return; 139650675Swpaul} 139750675Swpaul 139841502Swpaul/* 139941502Swpaul * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 140041502Swpaul * pointers to the fragment pointers. 140141502Swpaul */ 1402102336Salfredstatic int 1403102336Salfredwb_encap(sc, c, m_head) 140441502Swpaul struct wb_softc *sc; 140541502Swpaul struct wb_chain *c; 140641502Swpaul struct mbuf *m_head; 140741502Swpaul{ 140841502Swpaul int frag = 0; 140941502Swpaul struct wb_desc *f = NULL; 141041502Swpaul int total_len; 141141502Swpaul struct mbuf *m; 141241502Swpaul 141341502Swpaul /* 141441502Swpaul * Start packing the mbufs in this chain into 141541502Swpaul * the fragment pointers. Stop when we run out 141641502Swpaul * of fragments or hit the end of the mbuf chain. 141741502Swpaul */ 141841502Swpaul m = m_head; 141941502Swpaul total_len = 0; 142041502Swpaul 142141502Swpaul for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 142241502Swpaul if (m->m_len != 0) { 142341502Swpaul if (frag == WB_MAXFRAGS) 142441502Swpaul break; 142541502Swpaul total_len += m->m_len; 142641502Swpaul f = &c->wb_ptr->wb_frag[frag]; 142741502Swpaul f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 142841502Swpaul if (frag == 0) { 142941502Swpaul f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 143041502Swpaul f->wb_status = 0; 143141502Swpaul } else 143241502Swpaul f->wb_status = WB_TXSTAT_OWN; 143341502Swpaul f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 143441502Swpaul f->wb_data = vtophys(mtod(m, vm_offset_t)); 143541502Swpaul frag++; 143641502Swpaul } 143741502Swpaul } 143841502Swpaul 143941502Swpaul /* 144041502Swpaul * Handle special case: we used up all 16 fragments, 144141502Swpaul * but we have more mbufs left in the chain. Copy the 144241502Swpaul * data into an mbuf cluster. Note that we don't 144341502Swpaul * bother clearing the values in the other fragment 144441502Swpaul * pointers/counters; it wouldn't gain us anything, 144541502Swpaul * and would waste cycles. 144641502Swpaul */ 144741502Swpaul if (m != NULL) { 144841502Swpaul struct mbuf *m_new = NULL; 144941502Swpaul 1450111119Simp MGETHDR(m_new, M_DONTWAIT, MT_DATA); 145187846Sluigi if (m_new == NULL) 145241502Swpaul return(1); 145341502Swpaul if (m_head->m_pkthdr.len > MHLEN) { 1454111119Simp MCLGET(m_new, M_DONTWAIT); 145541502Swpaul if (!(m_new->m_flags & M_EXT)) { 145641502Swpaul m_freem(m_new); 145741502Swpaul return(1); 145841502Swpaul } 145941502Swpaul } 146041502Swpaul m_copydata(m_head, 0, m_head->m_pkthdr.len, 146141502Swpaul mtod(m_new, caddr_t)); 146241502Swpaul m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 146341502Swpaul m_freem(m_head); 146441502Swpaul m_head = m_new; 146541502Swpaul f = &c->wb_ptr->wb_frag[0]; 146641502Swpaul f->wb_status = 0; 146741502Swpaul f->wb_data = vtophys(mtod(m_new, caddr_t)); 146841502Swpaul f->wb_ctl = total_len = m_new->m_len; 146941502Swpaul f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 147041502Swpaul frag = 1; 147141502Swpaul } 147241502Swpaul 147341502Swpaul if (total_len < WB_MIN_FRAMELEN) { 147441502Swpaul f = &c->wb_ptr->wb_frag[frag]; 147541502Swpaul f->wb_ctl = WB_MIN_FRAMELEN - total_len; 147641502Swpaul f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 147741502Swpaul f->wb_ctl |= WB_TXCTL_TLINK; 147841502Swpaul f->wb_status = WB_TXSTAT_OWN; 147941502Swpaul frag++; 148041502Swpaul } 148141502Swpaul 148241502Swpaul c->wb_mbuf = m_head; 148341502Swpaul c->wb_lastdesc = frag - 1; 148441502Swpaul WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 148541502Swpaul WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 148641502Swpaul 148741502Swpaul return(0); 148841502Swpaul} 148941502Swpaul 149041502Swpaul/* 149141502Swpaul * Main transmit routine. To avoid having to do mbuf copies, we put pointers 149241502Swpaul * to the mbuf data regions directly in the transmit lists. We also save a 149341502Swpaul * copy of the pointers since the transmit list fragment pointers are 149441502Swpaul * physical addresses. 149541502Swpaul */ 149641502Swpaul 1497102336Salfredstatic void 1498102336Salfredwb_start(ifp) 149941502Swpaul struct ifnet *ifp; 150041502Swpaul{ 150141502Swpaul struct wb_softc *sc; 150241502Swpaul struct mbuf *m_head = NULL; 150341502Swpaul struct wb_chain *cur_tx = NULL, *start_tx; 150441502Swpaul 150541502Swpaul sc = ifp->if_softc; 150667087Swpaul WB_LOCK(sc); 150741502Swpaul 150841502Swpaul /* 150941502Swpaul * Check for an available queue slot. If there are none, 151041502Swpaul * punt. 151141502Swpaul */ 151241502Swpaul if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 151341502Swpaul ifp->if_flags |= IFF_OACTIVE; 151467087Swpaul WB_UNLOCK(sc); 151541502Swpaul return; 151641502Swpaul } 151741502Swpaul 151841502Swpaul start_tx = sc->wb_cdata.wb_tx_free; 151941502Swpaul 152041502Swpaul while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 152141502Swpaul IF_DEQUEUE(&ifp->if_snd, m_head); 152241502Swpaul if (m_head == NULL) 152341502Swpaul break; 152441502Swpaul 152541502Swpaul /* Pick a descriptor off the free list. */ 152641502Swpaul cur_tx = sc->wb_cdata.wb_tx_free; 152741502Swpaul sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 152841502Swpaul 152941502Swpaul /* Pack the data into the descriptor. */ 153041502Swpaul wb_encap(sc, cur_tx, m_head); 153141502Swpaul 153241502Swpaul if (cur_tx != start_tx) 153341502Swpaul WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 153441502Swpaul 153541502Swpaul /* 153641502Swpaul * If there's a BPF listener, bounce a copy of this frame 153741502Swpaul * to him. 153841502Swpaul */ 1539106936Ssam BPF_MTAP(ifp, cur_tx->wb_mbuf); 154041502Swpaul } 154141502Swpaul 154241502Swpaul /* 154341526Swpaul * If there are no packets queued, bail. 154441526Swpaul */ 154567087Swpaul if (cur_tx == NULL) { 154667087Swpaul WB_UNLOCK(sc); 154741526Swpaul return; 154867087Swpaul } 154941526Swpaul 155041526Swpaul /* 155141502Swpaul * Place the request for the upload interrupt 155241502Swpaul * in the last descriptor in the chain. This way, if 155341502Swpaul * we're chaining several packets at once, we'll only 155441502Swpaul * get an interupt once for the whole chain rather than 155541502Swpaul * once for each packet. 155641502Swpaul */ 155741502Swpaul WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 155842718Swpaul cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 155941502Swpaul sc->wb_cdata.wb_tx_tail = cur_tx; 156041502Swpaul 156141502Swpaul if (sc->wb_cdata.wb_tx_head == NULL) { 156241502Swpaul sc->wb_cdata.wb_tx_head = start_tx; 156341502Swpaul WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 156441502Swpaul CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 156541502Swpaul } else { 156641502Swpaul /* 156741502Swpaul * We need to distinguish between the case where 156841502Swpaul * the own bit is clear because the chip cleared it 156941502Swpaul * and where the own bit is clear because we haven't 157041502Swpaul * set it yet. The magic value WB_UNSET is just some 157141502Swpaul * ramdomly chosen number which doesn't have the own 157241502Swpaul * bit set. When we actually transmit the frame, the 157341502Swpaul * status word will have _only_ the own bit set, so 157441502Swpaul * the txeoc handler will be able to tell if it needs 157541502Swpaul * to initiate another transmission to flush out pending 157641502Swpaul * frames. 157741502Swpaul */ 157841502Swpaul WB_TXOWN(start_tx) = WB_UNSENT; 157941502Swpaul } 158041502Swpaul 158141502Swpaul /* 158241502Swpaul * Set a timeout in case the chip goes out to lunch. 158341502Swpaul */ 158441502Swpaul ifp->if_timer = 5; 158567087Swpaul WB_UNLOCK(sc); 158641502Swpaul 158741502Swpaul return; 158841502Swpaul} 158941502Swpaul 1590102336Salfredstatic void 1591102336Salfredwb_init(xsc) 159241502Swpaul void *xsc; 159341502Swpaul{ 159441502Swpaul struct wb_softc *sc = xsc; 159541502Swpaul struct ifnet *ifp = &sc->arpcom.ac_if; 159667087Swpaul int i; 159750675Swpaul struct mii_data *mii; 159841502Swpaul 159967087Swpaul WB_LOCK(sc); 160050675Swpaul mii = device_get_softc(sc->wb_miibus); 160141502Swpaul 160241502Swpaul /* 160341502Swpaul * Cancel pending I/O and free all RX/TX buffers. 160441502Swpaul */ 160541502Swpaul wb_stop(sc); 160641502Swpaul wb_reset(sc); 160741502Swpaul 160841502Swpaul sc->wb_txthresh = WB_TXTHRESH_INIT; 160941502Swpaul 161041502Swpaul /* 161141502Swpaul * Set cache alignment and burst length. 161241502Swpaul */ 161350675Swpaul#ifdef foo 161441502Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 161541502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 161641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 161750675Swpaul#endif 161841502Swpaul 161950675Swpaul CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 162050675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 162150675Swpaul switch(sc->wb_cachesize) { 162250675Swpaul case 32: 162350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 162450675Swpaul break; 162550675Swpaul case 16: 162650675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 162750675Swpaul break; 162850675Swpaul case 8: 162950675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 163050675Swpaul break; 163150675Swpaul case 0: 163250675Swpaul default: 163350675Swpaul WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 163450675Swpaul break; 163550675Swpaul } 163650675Swpaul 163741502Swpaul /* This doesn't tend to work too well at 100Mbps. */ 163841502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 163941502Swpaul 164041502Swpaul /* Init our MAC address */ 164141502Swpaul for (i = 0; i < ETHER_ADDR_LEN; i++) { 164241502Swpaul CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 164341502Swpaul } 164441502Swpaul 164541502Swpaul /* Init circular RX list. */ 164641502Swpaul if (wb_list_rx_init(sc) == ENOBUFS) { 164741502Swpaul printf("wb%d: initialization failed: no " 164841502Swpaul "memory for rx buffers\n", sc->wb_unit); 164941502Swpaul wb_stop(sc); 165067087Swpaul WB_UNLOCK(sc); 165141502Swpaul return; 165241502Swpaul } 165341502Swpaul 165441502Swpaul /* Init TX descriptors. */ 165541502Swpaul wb_list_tx_init(sc); 165641502Swpaul 165741502Swpaul /* If we want promiscuous mode, set the allframes bit. */ 165841502Swpaul if (ifp->if_flags & IFF_PROMISC) { 165941502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166041502Swpaul } else { 166141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 166241502Swpaul } 166341502Swpaul 166441502Swpaul /* 166541502Swpaul * Set capture broadcast bit to capture broadcast frames. 166641502Swpaul */ 166741502Swpaul if (ifp->if_flags & IFF_BROADCAST) { 166841502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 166941502Swpaul } else { 167041502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 167141502Swpaul } 167241502Swpaul 167341502Swpaul /* 167441502Swpaul * Program the multicast filter, if necessary. 167541502Swpaul */ 167641502Swpaul wb_setmulti(sc); 167741502Swpaul 167841502Swpaul /* 167941502Swpaul * Load the address of the RX list. 168041502Swpaul */ 168141502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 168241502Swpaul CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 168341502Swpaul 168441502Swpaul /* 168541502Swpaul * Enable interrupts. 168641502Swpaul */ 168741502Swpaul CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 168841502Swpaul CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 168941502Swpaul 169041502Swpaul /* Enable receiver and transmitter. */ 169141502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 169241502Swpaul CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 169341502Swpaul 169441502Swpaul WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 169541502Swpaul CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 169641502Swpaul WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 169741502Swpaul 169850675Swpaul mii_mediachg(mii); 169941502Swpaul 170041502Swpaul ifp->if_flags |= IFF_RUNNING; 170141502Swpaul ifp->if_flags &= ~IFF_OACTIVE; 170241502Swpaul 170350675Swpaul sc->wb_stat_ch = timeout(wb_tick, sc, hz); 170467087Swpaul WB_UNLOCK(sc); 170550675Swpaul 170641502Swpaul return; 170741502Swpaul} 170841502Swpaul 170941502Swpaul/* 171041502Swpaul * Set media options. 171141502Swpaul */ 1712102336Salfredstatic int 1713102336Salfredwb_ifmedia_upd(ifp) 171441502Swpaul struct ifnet *ifp; 171541502Swpaul{ 171641502Swpaul struct wb_softc *sc; 171741502Swpaul 171841502Swpaul sc = ifp->if_softc; 171941502Swpaul 172050675Swpaul if (ifp->if_flags & IFF_UP) 172150675Swpaul wb_init(sc); 172241502Swpaul 172341502Swpaul return(0); 172441502Swpaul} 172541502Swpaul 172641502Swpaul/* 172741502Swpaul * Report current media status. 172841502Swpaul */ 1729102336Salfredstatic void 1730102336Salfredwb_ifmedia_sts(ifp, ifmr) 173141502Swpaul struct ifnet *ifp; 173241502Swpaul struct ifmediareq *ifmr; 173341502Swpaul{ 173441502Swpaul struct wb_softc *sc; 173550675Swpaul struct mii_data *mii; 173641502Swpaul 173741502Swpaul sc = ifp->if_softc; 173841502Swpaul 173950675Swpaul mii = device_get_softc(sc->wb_miibus); 174041502Swpaul 174150675Swpaul mii_pollstat(mii); 174250675Swpaul ifmr->ifm_active = mii->mii_media_active; 174350675Swpaul ifmr->ifm_status = mii->mii_media_status; 174441502Swpaul 174541502Swpaul return; 174641502Swpaul} 174741502Swpaul 1748102336Salfredstatic int 1749102336Salfredwb_ioctl(ifp, command, data) 175041502Swpaul struct ifnet *ifp; 175141502Swpaul u_long command; 175241502Swpaul caddr_t data; 175341502Swpaul{ 175441502Swpaul struct wb_softc *sc = ifp->if_softc; 175550675Swpaul struct mii_data *mii; 175641502Swpaul struct ifreq *ifr = (struct ifreq *) data; 175767087Swpaul int error = 0; 175841502Swpaul 175967087Swpaul WB_LOCK(sc); 176041502Swpaul 176141502Swpaul switch(command) { 176241502Swpaul case SIOCSIFFLAGS: 176341502Swpaul if (ifp->if_flags & IFF_UP) { 176441502Swpaul wb_init(sc); 176541502Swpaul } else { 176641502Swpaul if (ifp->if_flags & IFF_RUNNING) 176741502Swpaul wb_stop(sc); 176841502Swpaul } 176941502Swpaul error = 0; 177041502Swpaul break; 177141502Swpaul case SIOCADDMULTI: 177241502Swpaul case SIOCDELMULTI: 177341502Swpaul wb_setmulti(sc); 177441502Swpaul error = 0; 177541502Swpaul break; 177641502Swpaul case SIOCGIFMEDIA: 177741502Swpaul case SIOCSIFMEDIA: 177850675Swpaul mii = device_get_softc(sc->wb_miibus); 177950675Swpaul error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 178041502Swpaul break; 178141502Swpaul default: 1782106936Ssam error = ether_ioctl(ifp, command, data); 178341502Swpaul break; 178441502Swpaul } 178541502Swpaul 178667087Swpaul WB_UNLOCK(sc); 178741502Swpaul 178841502Swpaul return(error); 178941502Swpaul} 179041502Swpaul 1791102336Salfredstatic void 1792102336Salfredwb_watchdog(ifp) 179341502Swpaul struct ifnet *ifp; 179441502Swpaul{ 179541502Swpaul struct wb_softc *sc; 179641502Swpaul 179741502Swpaul sc = ifp->if_softc; 179841502Swpaul 179967087Swpaul WB_LOCK(sc); 180041502Swpaul ifp->if_oerrors++; 180141502Swpaul printf("wb%d: watchdog timeout\n", sc->wb_unit); 180250675Swpaul#ifdef foo 180341502Swpaul if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 180441502Swpaul printf("wb%d: no carrier - transceiver cable problem?\n", 180541502Swpaul sc->wb_unit); 180650675Swpaul#endif 180741502Swpaul wb_stop(sc); 180841502Swpaul wb_reset(sc); 180941502Swpaul wb_init(sc); 181041502Swpaul 181141502Swpaul if (ifp->if_snd.ifq_head != NULL) 181241502Swpaul wb_start(ifp); 181367087Swpaul WB_UNLOCK(sc); 181441502Swpaul 181541502Swpaul return; 181641502Swpaul} 181741502Swpaul 181841502Swpaul/* 181941502Swpaul * Stop the adapter and free any mbufs allocated to the 182041502Swpaul * RX and TX lists. 182141502Swpaul */ 1822102336Salfredstatic void 1823102336Salfredwb_stop(sc) 182441502Swpaul struct wb_softc *sc; 182541502Swpaul{ 182641502Swpaul register int i; 182741502Swpaul struct ifnet *ifp; 182841502Swpaul 182967087Swpaul WB_LOCK(sc); 183041502Swpaul ifp = &sc->arpcom.ac_if; 183141502Swpaul ifp->if_timer = 0; 183241502Swpaul 183350675Swpaul untimeout(wb_tick, sc, sc->wb_stat_ch); 183450675Swpaul 183541502Swpaul WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 183641502Swpaul CSR_WRITE_4(sc, WB_IMR, 0x00000000); 183741502Swpaul CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 183841502Swpaul CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 183941502Swpaul 184041502Swpaul /* 184141502Swpaul * Free data in the RX lists. 184241502Swpaul */ 184341502Swpaul for (i = 0; i < WB_RX_LIST_CNT; i++) { 184441502Swpaul if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 184541502Swpaul m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 184641502Swpaul sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 184741502Swpaul } 184841502Swpaul } 184941502Swpaul bzero((char *)&sc->wb_ldata->wb_rx_list, 185041502Swpaul sizeof(sc->wb_ldata->wb_rx_list)); 185141502Swpaul 185241502Swpaul /* 185341502Swpaul * Free the TX list buffers. 185441502Swpaul */ 185541502Swpaul for (i = 0; i < WB_TX_LIST_CNT; i++) { 185641502Swpaul if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 185741502Swpaul m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 185841502Swpaul sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 185941502Swpaul } 186041502Swpaul } 186141502Swpaul 186241502Swpaul bzero((char *)&sc->wb_ldata->wb_tx_list, 186341502Swpaul sizeof(sc->wb_ldata->wb_tx_list)); 186441502Swpaul 186541502Swpaul ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 186667087Swpaul WB_UNLOCK(sc); 186741502Swpaul 186841502Swpaul return; 186941502Swpaul} 187041502Swpaul 187141502Swpaul/* 187241502Swpaul * Stop all chip I/O so that the kernel's probe routines don't 187341502Swpaul * get confused by errant DMAs when rebooting. 187441502Swpaul */ 1875102336Salfredstatic void 1876102336Salfredwb_shutdown(dev) 187749611Swpaul device_t dev; 187841502Swpaul{ 187949611Swpaul struct wb_softc *sc; 188041502Swpaul 188149611Swpaul sc = device_get_softc(dev); 188241502Swpaul wb_stop(sc); 188341502Swpaul 188441502Swpaul return; 188541502Swpaul} 1886