if_wb.c revision 122625
1/* 2 * Copyright (c) 1997, 1998 3 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33/* 34 * Winbond fast ethernet PCI NIC driver 35 * 36 * Supports various cheap network adapters based on the Winbond W89C840F 37 * fast ethernet controller chip. This includes adapters manufactured by 38 * Winbond itself and some made by Linksys. 39 * 40 * Written by Bill Paul <wpaul@ctr.columbia.edu> 41 * Electrical Engineering Department 42 * Columbia University, New York City 43 */ 44 45/* 46 * The Winbond W89C840F chip is a bus master; in some ways it resembles 47 * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 48 * one major difference which is that while the registers do many of 49 * the same things as a tulip adapter, the offsets are different: where 50 * tulip registers are typically spaced 8 bytes apart, the Winbond 51 * registers are spaced 4 bytes apart. The receiver filter is also 52 * programmed differently. 53 * 54 * Like the tulip, the Winbond chip uses small descriptors containing 55 * a status word, a control word and 32-bit areas that can either be used 56 * to point to two external data blocks, or to point to a single block 57 * and another descriptor in a linked list. Descriptors can be grouped 58 * together in blocks to form fixed length rings or can be chained 59 * together in linked lists. A single packet may be spread out over 60 * several descriptors if necessary. 61 * 62 * For the receive ring, this driver uses a linked list of descriptors, 63 * each pointing to a single mbuf cluster buffer, which us large enough 64 * to hold an entire packet. The link list is looped back to created a 65 * closed ring. 66 * 67 * For transmission, the driver creates a linked list of 'super descriptors' 68 * which each contain several individual descriptors linked toghether. 69 * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 70 * abuse as fragment pointers. This allows us to use a buffer managment 71 * scheme very similar to that used in the ThunderLAN and Etherlink XL 72 * drivers. 73 * 74 * Autonegotiation is performed using the external PHY via the MII bus. 75 * The sample boards I have all use a Davicom PHY. 76 * 77 * Note: the author of the Linux driver for the Winbond chip alludes 78 * to some sort of flaw in the chip's design that seems to mandate some 79 * drastic workaround which signigicantly impairs transmit performance. 80 * I have no idea what he's on about: transmit performance with all 81 * three of my test boards seems fine. 82 */ 83 84#include <sys/cdefs.h> 85__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 122625 2003-11-13 20:55:53Z obrien $"); 86 87#include "opt_bdg.h" 88 89#include <sys/param.h> 90#include <sys/systm.h> 91#include <sys/sockio.h> 92#include <sys/mbuf.h> 93#include <sys/malloc.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/queue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103 104#include <net/bpf.h> 105 106#include <vm/vm.h> /* for vtophys */ 107#include <vm/pmap.h> /* for vtophys */ 108#include <machine/bus_memio.h> 109#include <machine/bus_pio.h> 110#include <machine/bus.h> 111#include <machine/resource.h> 112#include <sys/bus.h> 113#include <sys/rman.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117 118#include <dev/mii/mii.h> 119#include <dev/mii/miivar.h> 120 121/* "controller miibus0" required. See GENERIC if you get errors here. */ 122#include "miibus_if.h" 123 124#define WB_USEIOSPACE 125 126#include <pci/if_wbreg.h> 127 128MODULE_DEPEND(wb, pci, 1, 1, 1); 129MODULE_DEPEND(wb, ether, 1, 1, 1); 130MODULE_DEPEND(wb, miibus, 1, 1, 1); 131 132/* 133 * Various supported device vendors/types and their names. 134 */ 135static struct wb_type wb_devs[] = { 136 { WB_VENDORID, WB_DEVICEID_840F, 137 "Winbond W89C840F 10/100BaseTX" }, 138 { CP_VENDORID, CP_DEVICEID_RL100, 139 "Compex RL100-ATX 10/100baseTX" }, 140 { 0, 0, NULL } 141}; 142 143static int wb_probe (device_t); 144static int wb_attach (device_t); 145static int wb_detach (device_t); 146 147static void wb_bfree (void *addr, void *args); 148static int wb_newbuf (struct wb_softc *, 149 struct wb_chain_onefrag *, 150 struct mbuf *); 151static int wb_encap (struct wb_softc *, struct wb_chain *, 152 struct mbuf *); 153 154static void wb_rxeof (struct wb_softc *); 155static void wb_rxeoc (struct wb_softc *); 156static void wb_txeof (struct wb_softc *); 157static void wb_txeoc (struct wb_softc *); 158static void wb_intr (void *); 159static void wb_tick (void *); 160static void wb_start (struct ifnet *); 161static int wb_ioctl (struct ifnet *, u_long, caddr_t); 162static void wb_init (void *); 163static void wb_stop (struct wb_softc *); 164static void wb_watchdog (struct ifnet *); 165static void wb_shutdown (device_t); 166static int wb_ifmedia_upd (struct ifnet *); 167static void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 168 169static void wb_eeprom_putbyte (struct wb_softc *, int); 170static void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 171static void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 172static void wb_mii_sync (struct wb_softc *); 173static void wb_mii_send (struct wb_softc *, u_int32_t, int); 174static int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175static int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176 177static void wb_setcfg (struct wb_softc *, u_int32_t); 178static u_int32_t wb_mchash (caddr_t); 179static void wb_setmulti (struct wb_softc *); 180static void wb_reset (struct wb_softc *); 181static void wb_fixmedia (struct wb_softc *); 182static int wb_list_rx_init (struct wb_softc *); 183static int wb_list_tx_init (struct wb_softc *); 184 185static int wb_miibus_readreg (device_t, int, int); 186static int wb_miibus_writereg (device_t, int, int, int); 187static void wb_miibus_statchg (device_t); 188 189#ifdef WB_USEIOSPACE 190#define WB_RES SYS_RES_IOPORT 191#define WB_RID WB_PCI_LOIO 192#else 193#define WB_RES SYS_RES_MEMORY 194#define WB_RID WB_PCI_LOMEM 195#endif 196 197static device_method_t wb_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, wb_probe), 200 DEVMETHOD(device_attach, wb_attach), 201 DEVMETHOD(device_detach, wb_detach), 202 DEVMETHOD(device_shutdown, wb_shutdown), 203 204 /* bus interface, for miibus */ 205 DEVMETHOD(bus_print_child, bus_generic_print_child), 206 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207 208 /* MII interface */ 209 DEVMETHOD(miibus_readreg, wb_miibus_readreg), 210 DEVMETHOD(miibus_writereg, wb_miibus_writereg), 211 DEVMETHOD(miibus_statchg, wb_miibus_statchg), 212 { 0, 0 } 213}; 214 215static driver_t wb_driver = { 216 "wb", 217 wb_methods, 218 sizeof(struct wb_softc) 219}; 220 221static devclass_t wb_devclass; 222 223DRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 224DRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 225 226#define WB_SETBIT(sc, reg, x) \ 227 CSR_WRITE_4(sc, reg, \ 228 CSR_READ_4(sc, reg) | (x)) 229 230#define WB_CLRBIT(sc, reg, x) \ 231 CSR_WRITE_4(sc, reg, \ 232 CSR_READ_4(sc, reg) & ~(x)) 233 234#define SIO_SET(x) \ 235 CSR_WRITE_4(sc, WB_SIO, \ 236 CSR_READ_4(sc, WB_SIO) | (x)) 237 238#define SIO_CLR(x) \ 239 CSR_WRITE_4(sc, WB_SIO, \ 240 CSR_READ_4(sc, WB_SIO) & ~(x)) 241 242/* 243 * Send a read command and address to the EEPROM, check for ACK. 244 */ 245static void 246wb_eeprom_putbyte(sc, addr) 247 struct wb_softc *sc; 248 int addr; 249{ 250 register int d, i; 251 252 d = addr | WB_EECMD_READ; 253 254 /* 255 * Feed in each bit and stobe the clock. 256 */ 257 for (i = 0x400; i; i >>= 1) { 258 if (d & i) { 259 SIO_SET(WB_SIO_EE_DATAIN); 260 } else { 261 SIO_CLR(WB_SIO_EE_DATAIN); 262 } 263 DELAY(100); 264 SIO_SET(WB_SIO_EE_CLK); 265 DELAY(150); 266 SIO_CLR(WB_SIO_EE_CLK); 267 DELAY(100); 268 } 269 270 return; 271} 272 273/* 274 * Read a word of data stored in the EEPROM at address 'addr.' 275 */ 276static void 277wb_eeprom_getword(sc, addr, dest) 278 struct wb_softc *sc; 279 int addr; 280 u_int16_t *dest; 281{ 282 register int i; 283 u_int16_t word = 0; 284 285 /* Enter EEPROM access mode. */ 286 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 287 288 /* 289 * Send address of word we want to read. 290 */ 291 wb_eeprom_putbyte(sc, addr); 292 293 CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294 295 /* 296 * Start reading bits from EEPROM. 297 */ 298 for (i = 0x8000; i; i >>= 1) { 299 SIO_SET(WB_SIO_EE_CLK); 300 DELAY(100); 301 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 302 word |= i; 303 SIO_CLR(WB_SIO_EE_CLK); 304 DELAY(100); 305 } 306 307 /* Turn off EEPROM access mode. */ 308 CSR_WRITE_4(sc, WB_SIO, 0); 309 310 *dest = word; 311 312 return; 313} 314 315/* 316 * Read a sequence of words from the EEPROM. 317 */ 318static void 319wb_read_eeprom(sc, dest, off, cnt, swap) 320 struct wb_softc *sc; 321 caddr_t dest; 322 int off; 323 int cnt; 324 int swap; 325{ 326 int i; 327 u_int16_t word = 0, *ptr; 328 329 for (i = 0; i < cnt; i++) { 330 wb_eeprom_getword(sc, off + i, &word); 331 ptr = (u_int16_t *)(dest + (i * 2)); 332 if (swap) 333 *ptr = ntohs(word); 334 else 335 *ptr = word; 336 } 337 338 return; 339} 340 341/* 342 * Sync the PHYs by setting data bit and strobing the clock 32 times. 343 */ 344static void 345wb_mii_sync(sc) 346 struct wb_softc *sc; 347{ 348 register int i; 349 350 SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 351 352 for (i = 0; i < 32; i++) { 353 SIO_SET(WB_SIO_MII_CLK); 354 DELAY(1); 355 SIO_CLR(WB_SIO_MII_CLK); 356 DELAY(1); 357 } 358 359 return; 360} 361 362/* 363 * Clock a series of bits through the MII. 364 */ 365static void 366wb_mii_send(sc, bits, cnt) 367 struct wb_softc *sc; 368 u_int32_t bits; 369 int cnt; 370{ 371 int i; 372 373 SIO_CLR(WB_SIO_MII_CLK); 374 375 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 376 if (bits & i) { 377 SIO_SET(WB_SIO_MII_DATAIN); 378 } else { 379 SIO_CLR(WB_SIO_MII_DATAIN); 380 } 381 DELAY(1); 382 SIO_CLR(WB_SIO_MII_CLK); 383 DELAY(1); 384 SIO_SET(WB_SIO_MII_CLK); 385 } 386} 387 388/* 389 * Read an PHY register through the MII. 390 */ 391static int 392wb_mii_readreg(sc, frame) 393 struct wb_softc *sc; 394 struct wb_mii_frame *frame; 395 396{ 397 int i, ack; 398 399 WB_LOCK(sc); 400 401 /* 402 * Set up frame for RX. 403 */ 404 frame->mii_stdelim = WB_MII_STARTDELIM; 405 frame->mii_opcode = WB_MII_READOP; 406 frame->mii_turnaround = 0; 407 frame->mii_data = 0; 408 409 CSR_WRITE_4(sc, WB_SIO, 0); 410 411 /* 412 * Turn on data xmit. 413 */ 414 SIO_SET(WB_SIO_MII_DIR); 415 416 wb_mii_sync(sc); 417 418 /* 419 * Send command/address info. 420 */ 421 wb_mii_send(sc, frame->mii_stdelim, 2); 422 wb_mii_send(sc, frame->mii_opcode, 2); 423 wb_mii_send(sc, frame->mii_phyaddr, 5); 424 wb_mii_send(sc, frame->mii_regaddr, 5); 425 426 /* Idle bit */ 427 SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 428 DELAY(1); 429 SIO_SET(WB_SIO_MII_CLK); 430 DELAY(1); 431 432 /* Turn off xmit. */ 433 SIO_CLR(WB_SIO_MII_DIR); 434 /* Check for ack */ 435 SIO_CLR(WB_SIO_MII_CLK); 436 DELAY(1); 437 ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 438 SIO_SET(WB_SIO_MII_CLK); 439 DELAY(1); 440 SIO_CLR(WB_SIO_MII_CLK); 441 DELAY(1); 442 SIO_SET(WB_SIO_MII_CLK); 443 DELAY(1); 444 445 /* 446 * Now try reading data bits. If the ack failed, we still 447 * need to clock through 16 cycles to keep the PHY(s) in sync. 448 */ 449 if (ack) { 450 for(i = 0; i < 16; i++) { 451 SIO_CLR(WB_SIO_MII_CLK); 452 DELAY(1); 453 SIO_SET(WB_SIO_MII_CLK); 454 DELAY(1); 455 } 456 goto fail; 457 } 458 459 for (i = 0x8000; i; i >>= 1) { 460 SIO_CLR(WB_SIO_MII_CLK); 461 DELAY(1); 462 if (!ack) { 463 if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 464 frame->mii_data |= i; 465 DELAY(1); 466 } 467 SIO_SET(WB_SIO_MII_CLK); 468 DELAY(1); 469 } 470 471fail: 472 473 SIO_CLR(WB_SIO_MII_CLK); 474 DELAY(1); 475 SIO_SET(WB_SIO_MII_CLK); 476 DELAY(1); 477 478 WB_UNLOCK(sc); 479 480 if (ack) 481 return(1); 482 return(0); 483} 484 485/* 486 * Write to a PHY register through the MII. 487 */ 488static int 489wb_mii_writereg(sc, frame) 490 struct wb_softc *sc; 491 struct wb_mii_frame *frame; 492 493{ 494 WB_LOCK(sc); 495 496 /* 497 * Set up frame for TX. 498 */ 499 500 frame->mii_stdelim = WB_MII_STARTDELIM; 501 frame->mii_opcode = WB_MII_WRITEOP; 502 frame->mii_turnaround = WB_MII_TURNAROUND; 503 504 /* 505 * Turn on data output. 506 */ 507 SIO_SET(WB_SIO_MII_DIR); 508 509 wb_mii_sync(sc); 510 511 wb_mii_send(sc, frame->mii_stdelim, 2); 512 wb_mii_send(sc, frame->mii_opcode, 2); 513 wb_mii_send(sc, frame->mii_phyaddr, 5); 514 wb_mii_send(sc, frame->mii_regaddr, 5); 515 wb_mii_send(sc, frame->mii_turnaround, 2); 516 wb_mii_send(sc, frame->mii_data, 16); 517 518 /* Idle bit. */ 519 SIO_SET(WB_SIO_MII_CLK); 520 DELAY(1); 521 SIO_CLR(WB_SIO_MII_CLK); 522 DELAY(1); 523 524 /* 525 * Turn off xmit. 526 */ 527 SIO_CLR(WB_SIO_MII_DIR); 528 529 WB_UNLOCK(sc); 530 531 return(0); 532} 533 534static int 535wb_miibus_readreg(dev, phy, reg) 536 device_t dev; 537 int phy, reg; 538{ 539 struct wb_softc *sc; 540 struct wb_mii_frame frame; 541 542 sc = device_get_softc(dev); 543 544 bzero((char *)&frame, sizeof(frame)); 545 546 frame.mii_phyaddr = phy; 547 frame.mii_regaddr = reg; 548 wb_mii_readreg(sc, &frame); 549 550 return(frame.mii_data); 551} 552 553static int 554wb_miibus_writereg(dev, phy, reg, data) 555 device_t dev; 556 int phy, reg, data; 557{ 558 struct wb_softc *sc; 559 struct wb_mii_frame frame; 560 561 sc = device_get_softc(dev); 562 563 bzero((char *)&frame, sizeof(frame)); 564 565 frame.mii_phyaddr = phy; 566 frame.mii_regaddr = reg; 567 frame.mii_data = data; 568 569 wb_mii_writereg(sc, &frame); 570 571 return(0); 572} 573 574static void 575wb_miibus_statchg(dev) 576 device_t dev; 577{ 578 struct wb_softc *sc; 579 struct mii_data *mii; 580 581 sc = device_get_softc(dev); 582 WB_LOCK(sc); 583 mii = device_get_softc(sc->wb_miibus); 584 wb_setcfg(sc, mii->mii_media_active); 585 WB_UNLOCK(sc); 586 587 return; 588} 589 590static u_int32_t 591wb_mchash(addr) 592 caddr_t addr; 593{ 594 u_int32_t crc, carry; 595 int idx, bit; 596 u_int8_t data; 597 598 /* Compute CRC for the address value. */ 599 crc = 0xFFFFFFFF; /* initial value */ 600 601 for (idx = 0; idx < 6; idx++) { 602 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 603 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 604 crc <<= 1; 605 if (carry) 606 crc = (crc ^ 0x04c11db6) | carry; 607 } 608 } 609 610 /* 611 * return the filter bit position 612 * Note: I arrived at the following nonsense 613 * through experimentation. It's not the usual way to 614 * generate the bit position but it's the only thing 615 * I could come up with that works. 616 */ 617 return(~(crc >> 26) & 0x0000003F); 618} 619 620/* 621 * Program the 64-bit multicast hash filter. 622 */ 623static void 624wb_setmulti(sc) 625 struct wb_softc *sc; 626{ 627 struct ifnet *ifp; 628 int h = 0; 629 u_int32_t hashes[2] = { 0, 0 }; 630 struct ifmultiaddr *ifma; 631 u_int32_t rxfilt; 632 int mcnt = 0; 633 634 ifp = &sc->arpcom.ac_if; 635 636 rxfilt = CSR_READ_4(sc, WB_NETCFG); 637 638 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 639 rxfilt |= WB_NETCFG_RX_MULTI; 640 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 641 CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 642 CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 643 return; 644 } 645 646 /* first, zot all the existing hash bits */ 647 CSR_WRITE_4(sc, WB_MAR0, 0); 648 CSR_WRITE_4(sc, WB_MAR1, 0); 649 650 /* now program new ones */ 651 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 652 if (ifma->ifma_addr->sa_family != AF_LINK) 653 continue; 654 h = wb_mchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 655 if (h < 32) 656 hashes[0] |= (1 << h); 657 else 658 hashes[1] |= (1 << (h - 32)); 659 mcnt++; 660 } 661 662 if (mcnt) 663 rxfilt |= WB_NETCFG_RX_MULTI; 664 else 665 rxfilt &= ~WB_NETCFG_RX_MULTI; 666 667 CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 668 CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 669 CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 670 671 return; 672} 673 674/* 675 * The Winbond manual states that in order to fiddle with the 676 * 'full-duplex' and '100Mbps' bits in the netconfig register, we 677 * first have to put the transmit and/or receive logic in the idle state. 678 */ 679static void 680wb_setcfg(sc, media) 681 struct wb_softc *sc; 682 u_int32_t media; 683{ 684 int i, restart = 0; 685 686 if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 687 restart = 1; 688 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 689 690 for (i = 0; i < WB_TIMEOUT; i++) { 691 DELAY(10); 692 if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 693 (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 694 break; 695 } 696 697 if (i == WB_TIMEOUT) 698 printf("wb%d: failed to force tx and " 699 "rx to idle state\n", sc->wb_unit); 700 } 701 702 if (IFM_SUBTYPE(media) == IFM_10_T) 703 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 704 else 705 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 706 707 if ((media & IFM_GMASK) == IFM_FDX) 708 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 709 else 710 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 711 712 if (restart) 713 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 714 715 return; 716} 717 718static void 719wb_reset(sc) 720 struct wb_softc *sc; 721{ 722 register int i; 723 struct mii_data *mii; 724 725 CSR_WRITE_4(sc, WB_NETCFG, 0); 726 CSR_WRITE_4(sc, WB_BUSCTL, 0); 727 CSR_WRITE_4(sc, WB_TXADDR, 0); 728 CSR_WRITE_4(sc, WB_RXADDR, 0); 729 730 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 731 WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 732 733 for (i = 0; i < WB_TIMEOUT; i++) { 734 DELAY(10); 735 if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 736 break; 737 } 738 if (i == WB_TIMEOUT) 739 printf("wb%d: reset never completed!\n", sc->wb_unit); 740 741 /* Wait a little while for the chip to get its brains in order. */ 742 DELAY(1000); 743 744 if (sc->wb_miibus == NULL) 745 return; 746 747 mii = device_get_softc(sc->wb_miibus); 748 if (mii == NULL) 749 return; 750 751 if (mii->mii_instance) { 752 struct mii_softc *miisc; 753 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 754 mii_phy_reset(miisc); 755 } 756 757 return; 758} 759 760static void 761wb_fixmedia(sc) 762 struct wb_softc *sc; 763{ 764 struct mii_data *mii = NULL; 765 struct ifnet *ifp; 766 u_int32_t media; 767 768 if (sc->wb_miibus == NULL) 769 return; 770 771 mii = device_get_softc(sc->wb_miibus); 772 ifp = &sc->arpcom.ac_if; 773 774 mii_pollstat(mii); 775 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 776 media = mii->mii_media_active & ~IFM_10_T; 777 media |= IFM_100_TX; 778 } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 779 media = mii->mii_media_active & ~IFM_100_TX; 780 media |= IFM_10_T; 781 } else 782 return; 783 784 ifmedia_set(&mii->mii_media, media); 785 786 return; 787} 788 789/* 790 * Probe for a Winbond chip. Check the PCI vendor and device 791 * IDs against our list and return a device name if we find a match. 792 */ 793static int 794wb_probe(dev) 795 device_t dev; 796{ 797 struct wb_type *t; 798 799 t = wb_devs; 800 801 while(t->wb_name != NULL) { 802 if ((pci_get_vendor(dev) == t->wb_vid) && 803 (pci_get_device(dev) == t->wb_did)) { 804 device_set_desc(dev, t->wb_name); 805 return(0); 806 } 807 t++; 808 } 809 810 return(ENXIO); 811} 812 813/* 814 * Attach the interface. Allocate softc structures, do ifmedia 815 * setup and ethernet/BPF attach. 816 */ 817static int 818wb_attach(dev) 819 device_t dev; 820{ 821 u_char eaddr[ETHER_ADDR_LEN]; 822 struct wb_softc *sc; 823 struct ifnet *ifp; 824 int unit, error = 0, rid; 825 826 sc = device_get_softc(dev); 827 unit = device_get_unit(dev); 828 829 mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 830 MTX_DEF | MTX_RECURSE); 831#ifndef BURN_BRIDGES 832 /* 833 * Handle power management nonsense. 834 */ 835 836 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 837 u_int32_t iobase, membase, irq; 838 839 /* Save important PCI config data. */ 840 iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 841 membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 842 irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 843 844 /* Reset the power state. */ 845 printf("wb%d: chip is in D%d power mode " 846 "-- setting to D0\n", unit, 847 pci_get_powerstate(dev)); 848 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 849 850 /* Restore PCI config data. */ 851 pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 852 pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 853 pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 854 } 855#endif 856 /* 857 * Map control/status registers. 858 */ 859 pci_enable_busmaster(dev); 860 861 rid = WB_RID; 862 sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 863 0, ~0, 1, RF_ACTIVE); 864 865 if (sc->wb_res == NULL) { 866 printf("wb%d: couldn't map ports/memory\n", unit); 867 error = ENXIO; 868 goto fail; 869 } 870 871 sc->wb_btag = rman_get_bustag(sc->wb_res); 872 sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 873 874 /* Allocate interrupt */ 875 rid = 0; 876 sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 877 RF_SHAREABLE | RF_ACTIVE); 878 879 if (sc->wb_irq == NULL) { 880 printf("wb%d: couldn't map interrupt\n", unit); 881 error = ENXIO; 882 goto fail; 883 } 884 885 /* Save the cache line size. */ 886 sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 887 888 /* Reset the adapter. */ 889 wb_reset(sc); 890 891 /* 892 * Get station address from the EEPROM. 893 */ 894 wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 895 896 /* 897 * A Winbond chip was detected. Inform the world. 898 */ 899 printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 900 901 sc->wb_unit = unit; 902 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 903 904 sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 905 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 906 907 if (sc->wb_ldata == NULL) { 908 printf("wb%d: no memory for list buffers!\n", unit); 909 error = ENXIO; 910 goto fail; 911 } 912 913 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 914 915 ifp = &sc->arpcom.ac_if; 916 ifp->if_softc = sc; 917 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 918 ifp->if_mtu = ETHERMTU; 919 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 920 ifp->if_ioctl = wb_ioctl; 921 ifp->if_output = ether_output; 922 ifp->if_start = wb_start; 923 ifp->if_watchdog = wb_watchdog; 924 ifp->if_init = wb_init; 925 ifp->if_baudrate = 10000000; 926 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 927 928 /* 929 * Do MII setup. 930 */ 931 if (mii_phy_probe(dev, &sc->wb_miibus, 932 wb_ifmedia_upd, wb_ifmedia_sts)) { 933 error = ENXIO; 934 goto fail; 935 } 936 937 /* 938 * Call MI attach routine. 939 */ 940 ether_ifattach(ifp, eaddr); 941 942 /* Hook interrupt last to avoid having to lock softc */ 943 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 944 wb_intr, sc, &sc->wb_intrhand); 945 946 if (error) { 947 printf("wb%d: couldn't set up irq\n", unit); 948 ether_ifdetach(ifp); 949 goto fail; 950 } 951 952fail: 953 if (error) 954 wb_detach(dev); 955 956 return(error); 957} 958 959/* 960 * Shutdown hardware and free up resources. This can be called any 961 * time after the mutex has been initialized. It is called in both 962 * the error case in attach and the normal detach case so it needs 963 * to be careful about only freeing resources that have actually been 964 * allocated. 965 */ 966static int 967wb_detach(dev) 968 device_t dev; 969{ 970 struct wb_softc *sc; 971 struct ifnet *ifp; 972 973 sc = device_get_softc(dev); 974 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 975 WB_LOCK(sc); 976 ifp = &sc->arpcom.ac_if; 977 978 /* 979 * Delete any miibus and phy devices attached to this interface. 980 * This should only be done if attach succeeded. 981 */ 982 if (device_is_attached(dev)) { 983 wb_stop(sc); 984 ether_ifdetach(ifp); 985 } 986 if (sc->wb_miibus) 987 device_delete_child(dev, sc->wb_miibus); 988 bus_generic_detach(dev); 989 990 if (sc->wb_intrhand) 991 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 992 if (sc->wb_irq) 993 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 994 if (sc->wb_res) 995 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 996 997 if (sc->wb_ldata) { 998 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 999 M_DEVBUF); 1000 } 1001 1002 WB_UNLOCK(sc); 1003 mtx_destroy(&sc->wb_mtx); 1004 1005 return(0); 1006} 1007 1008/* 1009 * Initialize the transmit descriptors. 1010 */ 1011static int 1012wb_list_tx_init(sc) 1013 struct wb_softc *sc; 1014{ 1015 struct wb_chain_data *cd; 1016 struct wb_list_data *ld; 1017 int i; 1018 1019 cd = &sc->wb_cdata; 1020 ld = sc->wb_ldata; 1021 1022 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1023 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1024 if (i == (WB_TX_LIST_CNT - 1)) { 1025 cd->wb_tx_chain[i].wb_nextdesc = 1026 &cd->wb_tx_chain[0]; 1027 } else { 1028 cd->wb_tx_chain[i].wb_nextdesc = 1029 &cd->wb_tx_chain[i + 1]; 1030 } 1031 } 1032 1033 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1034 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1035 1036 return(0); 1037} 1038 1039 1040/* 1041 * Initialize the RX descriptors and allocate mbufs for them. Note that 1042 * we arrange the descriptors in a closed ring, so that the last descriptor 1043 * points back to the first. 1044 */ 1045static int 1046wb_list_rx_init(sc) 1047 struct wb_softc *sc; 1048{ 1049 struct wb_chain_data *cd; 1050 struct wb_list_data *ld; 1051 int i; 1052 1053 cd = &sc->wb_cdata; 1054 ld = sc->wb_ldata; 1055 1056 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1057 cd->wb_rx_chain[i].wb_ptr = 1058 (struct wb_desc *)&ld->wb_rx_list[i]; 1059 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1060 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1061 return(ENOBUFS); 1062 if (i == (WB_RX_LIST_CNT - 1)) { 1063 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1064 ld->wb_rx_list[i].wb_next = 1065 vtophys(&ld->wb_rx_list[0]); 1066 } else { 1067 cd->wb_rx_chain[i].wb_nextdesc = 1068 &cd->wb_rx_chain[i + 1]; 1069 ld->wb_rx_list[i].wb_next = 1070 vtophys(&ld->wb_rx_list[i + 1]); 1071 } 1072 } 1073 1074 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1075 1076 return(0); 1077} 1078 1079static void 1080wb_bfree(buf, args) 1081 void *buf; 1082 void *args; 1083{ 1084 return; 1085} 1086 1087/* 1088 * Initialize an RX descriptor and attach an MBUF cluster. 1089 */ 1090static int 1091wb_newbuf(sc, c, m) 1092 struct wb_softc *sc; 1093 struct wb_chain_onefrag *c; 1094 struct mbuf *m; 1095{ 1096 struct mbuf *m_new = NULL; 1097 1098 if (m == NULL) { 1099 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1100 if (m_new == NULL) 1101 return(ENOBUFS); 1102 m_new->m_data = c->wb_buf; 1103 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1104 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1105 EXT_NET_DRV); 1106 } else { 1107 m_new = m; 1108 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1109 m_new->m_data = m_new->m_ext.ext_buf; 1110 } 1111 1112 m_adj(m_new, sizeof(u_int64_t)); 1113 1114 c->wb_mbuf = m_new; 1115 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1116 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1117 c->wb_ptr->wb_status = WB_RXSTAT; 1118 1119 return(0); 1120} 1121 1122/* 1123 * A frame has been uploaded: pass the resulting mbuf chain up to 1124 * the higher level protocols. 1125 */ 1126static void 1127wb_rxeof(sc) 1128 struct wb_softc *sc; 1129{ 1130 struct mbuf *m = NULL; 1131 struct ifnet *ifp; 1132 struct wb_chain_onefrag *cur_rx; 1133 int total_len = 0; 1134 u_int32_t rxstat; 1135 1136 ifp = &sc->arpcom.ac_if; 1137 1138 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1139 WB_RXSTAT_OWN)) { 1140 struct mbuf *m0 = NULL; 1141 1142 cur_rx = sc->wb_cdata.wb_rx_head; 1143 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1144 1145 m = cur_rx->wb_mbuf; 1146 1147 if ((rxstat & WB_RXSTAT_MIIERR) || 1148 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1149 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1150 !(rxstat & WB_RXSTAT_LASTFRAG) || 1151 !(rxstat & WB_RXSTAT_RXCMP)) { 1152 ifp->if_ierrors++; 1153 wb_newbuf(sc, cur_rx, m); 1154 printf("wb%x: receiver babbling: possible chip " 1155 "bug, forcing reset\n", sc->wb_unit); 1156 wb_fixmedia(sc); 1157 wb_reset(sc); 1158 wb_init(sc); 1159 return; 1160 } 1161 1162 if (rxstat & WB_RXSTAT_RXERR) { 1163 ifp->if_ierrors++; 1164 wb_newbuf(sc, cur_rx, m); 1165 break; 1166 } 1167 1168 /* No errors; receive the packet. */ 1169 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1170 1171 /* 1172 * XXX The Winbond chip includes the CRC with every 1173 * received frame, and there's no way to turn this 1174 * behavior off (at least, I can't find anything in 1175 * the manual that explains how to do it) so we have 1176 * to trim off the CRC manually. 1177 */ 1178 total_len -= ETHER_CRC_LEN; 1179 1180 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1181 NULL); 1182 wb_newbuf(sc, cur_rx, m); 1183 if (m0 == NULL) { 1184 ifp->if_ierrors++; 1185 break; 1186 } 1187 m = m0; 1188 1189 ifp->if_ipackets++; 1190 (*ifp->if_input)(ifp, m); 1191 } 1192} 1193 1194static void 1195wb_rxeoc(sc) 1196 struct wb_softc *sc; 1197{ 1198 wb_rxeof(sc); 1199 1200 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1201 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1202 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1203 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1204 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1205 1206 return; 1207} 1208 1209/* 1210 * A frame was downloaded to the chip. It's safe for us to clean up 1211 * the list buffers. 1212 */ 1213static void 1214wb_txeof(sc) 1215 struct wb_softc *sc; 1216{ 1217 struct wb_chain *cur_tx; 1218 struct ifnet *ifp; 1219 1220 ifp = &sc->arpcom.ac_if; 1221 1222 /* Clear the timeout timer. */ 1223 ifp->if_timer = 0; 1224 1225 if (sc->wb_cdata.wb_tx_head == NULL) 1226 return; 1227 1228 /* 1229 * Go through our tx list and free mbufs for those 1230 * frames that have been transmitted. 1231 */ 1232 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1233 u_int32_t txstat; 1234 1235 cur_tx = sc->wb_cdata.wb_tx_head; 1236 txstat = WB_TXSTATUS(cur_tx); 1237 1238 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1239 break; 1240 1241 if (txstat & WB_TXSTAT_TXERR) { 1242 ifp->if_oerrors++; 1243 if (txstat & WB_TXSTAT_ABORT) 1244 ifp->if_collisions++; 1245 if (txstat & WB_TXSTAT_LATECOLL) 1246 ifp->if_collisions++; 1247 } 1248 1249 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1250 1251 ifp->if_opackets++; 1252 m_freem(cur_tx->wb_mbuf); 1253 cur_tx->wb_mbuf = NULL; 1254 1255 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1256 sc->wb_cdata.wb_tx_head = NULL; 1257 sc->wb_cdata.wb_tx_tail = NULL; 1258 break; 1259 } 1260 1261 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1262 } 1263 1264 return; 1265} 1266 1267/* 1268 * TX 'end of channel' interrupt handler. 1269 */ 1270static void 1271wb_txeoc(sc) 1272 struct wb_softc *sc; 1273{ 1274 struct ifnet *ifp; 1275 1276 ifp = &sc->arpcom.ac_if; 1277 1278 ifp->if_timer = 0; 1279 1280 if (sc->wb_cdata.wb_tx_head == NULL) { 1281 ifp->if_flags &= ~IFF_OACTIVE; 1282 sc->wb_cdata.wb_tx_tail = NULL; 1283 } else { 1284 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1285 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1286 ifp->if_timer = 5; 1287 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1288 } 1289 } 1290 1291 return; 1292} 1293 1294static void 1295wb_intr(arg) 1296 void *arg; 1297{ 1298 struct wb_softc *sc; 1299 struct ifnet *ifp; 1300 u_int32_t status; 1301 1302 sc = arg; 1303 WB_LOCK(sc); 1304 ifp = &sc->arpcom.ac_if; 1305 1306 if (!(ifp->if_flags & IFF_UP)) { 1307 WB_UNLOCK(sc); 1308 return; 1309 } 1310 1311 /* Disable interrupts. */ 1312 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1313 1314 for (;;) { 1315 1316 status = CSR_READ_4(sc, WB_ISR); 1317 if (status) 1318 CSR_WRITE_4(sc, WB_ISR, status); 1319 1320 if ((status & WB_INTRS) == 0) 1321 break; 1322 1323 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1324 ifp->if_ierrors++; 1325 wb_reset(sc); 1326 if (status & WB_ISR_RX_ERR) 1327 wb_fixmedia(sc); 1328 wb_init(sc); 1329 continue; 1330 } 1331 1332 if (status & WB_ISR_RX_OK) 1333 wb_rxeof(sc); 1334 1335 if (status & WB_ISR_RX_IDLE) 1336 wb_rxeoc(sc); 1337 1338 if (status & WB_ISR_TX_OK) 1339 wb_txeof(sc); 1340 1341 if (status & WB_ISR_TX_NOBUF) 1342 wb_txeoc(sc); 1343 1344 if (status & WB_ISR_TX_IDLE) { 1345 wb_txeof(sc); 1346 if (sc->wb_cdata.wb_tx_head != NULL) { 1347 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1348 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1349 } 1350 } 1351 1352 if (status & WB_ISR_TX_UNDERRUN) { 1353 ifp->if_oerrors++; 1354 wb_txeof(sc); 1355 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1356 /* Jack up TX threshold */ 1357 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1358 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1359 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1360 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1361 } 1362 1363 if (status & WB_ISR_BUS_ERR) { 1364 wb_reset(sc); 1365 wb_init(sc); 1366 } 1367 1368 } 1369 1370 /* Re-enable interrupts. */ 1371 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1372 1373 if (ifp->if_snd.ifq_head != NULL) { 1374 wb_start(ifp); 1375 } 1376 1377 WB_UNLOCK(sc); 1378 1379 return; 1380} 1381 1382static void 1383wb_tick(xsc) 1384 void *xsc; 1385{ 1386 struct wb_softc *sc; 1387 struct mii_data *mii; 1388 1389 sc = xsc; 1390 WB_LOCK(sc); 1391 mii = device_get_softc(sc->wb_miibus); 1392 1393 mii_tick(mii); 1394 1395 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1396 1397 WB_UNLOCK(sc); 1398 1399 return; 1400} 1401 1402/* 1403 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1404 * pointers to the fragment pointers. 1405 */ 1406static int 1407wb_encap(sc, c, m_head) 1408 struct wb_softc *sc; 1409 struct wb_chain *c; 1410 struct mbuf *m_head; 1411{ 1412 int frag = 0; 1413 struct wb_desc *f = NULL; 1414 int total_len; 1415 struct mbuf *m; 1416 1417 /* 1418 * Start packing the mbufs in this chain into 1419 * the fragment pointers. Stop when we run out 1420 * of fragments or hit the end of the mbuf chain. 1421 */ 1422 m = m_head; 1423 total_len = 0; 1424 1425 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1426 if (m->m_len != 0) { 1427 if (frag == WB_MAXFRAGS) 1428 break; 1429 total_len += m->m_len; 1430 f = &c->wb_ptr->wb_frag[frag]; 1431 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1432 if (frag == 0) { 1433 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1434 f->wb_status = 0; 1435 } else 1436 f->wb_status = WB_TXSTAT_OWN; 1437 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1438 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1439 frag++; 1440 } 1441 } 1442 1443 /* 1444 * Handle special case: we used up all 16 fragments, 1445 * but we have more mbufs left in the chain. Copy the 1446 * data into an mbuf cluster. Note that we don't 1447 * bother clearing the values in the other fragment 1448 * pointers/counters; it wouldn't gain us anything, 1449 * and would waste cycles. 1450 */ 1451 if (m != NULL) { 1452 struct mbuf *m_new = NULL; 1453 1454 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1455 if (m_new == NULL) 1456 return(1); 1457 if (m_head->m_pkthdr.len > MHLEN) { 1458 MCLGET(m_new, M_DONTWAIT); 1459 if (!(m_new->m_flags & M_EXT)) { 1460 m_freem(m_new); 1461 return(1); 1462 } 1463 } 1464 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1465 mtod(m_new, caddr_t)); 1466 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1467 m_freem(m_head); 1468 m_head = m_new; 1469 f = &c->wb_ptr->wb_frag[0]; 1470 f->wb_status = 0; 1471 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1472 f->wb_ctl = total_len = m_new->m_len; 1473 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1474 frag = 1; 1475 } 1476 1477 if (total_len < WB_MIN_FRAMELEN) { 1478 f = &c->wb_ptr->wb_frag[frag]; 1479 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1480 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1481 f->wb_ctl |= WB_TXCTL_TLINK; 1482 f->wb_status = WB_TXSTAT_OWN; 1483 frag++; 1484 } 1485 1486 c->wb_mbuf = m_head; 1487 c->wb_lastdesc = frag - 1; 1488 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1489 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1490 1491 return(0); 1492} 1493 1494/* 1495 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1496 * to the mbuf data regions directly in the transmit lists. We also save a 1497 * copy of the pointers since the transmit list fragment pointers are 1498 * physical addresses. 1499 */ 1500 1501static void 1502wb_start(ifp) 1503 struct ifnet *ifp; 1504{ 1505 struct wb_softc *sc; 1506 struct mbuf *m_head = NULL; 1507 struct wb_chain *cur_tx = NULL, *start_tx; 1508 1509 sc = ifp->if_softc; 1510 WB_LOCK(sc); 1511 1512 /* 1513 * Check for an available queue slot. If there are none, 1514 * punt. 1515 */ 1516 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1517 ifp->if_flags |= IFF_OACTIVE; 1518 WB_UNLOCK(sc); 1519 return; 1520 } 1521 1522 start_tx = sc->wb_cdata.wb_tx_free; 1523 1524 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1525 IF_DEQUEUE(&ifp->if_snd, m_head); 1526 if (m_head == NULL) 1527 break; 1528 1529 /* Pick a descriptor off the free list. */ 1530 cur_tx = sc->wb_cdata.wb_tx_free; 1531 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1532 1533 /* Pack the data into the descriptor. */ 1534 wb_encap(sc, cur_tx, m_head); 1535 1536 if (cur_tx != start_tx) 1537 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1538 1539 /* 1540 * If there's a BPF listener, bounce a copy of this frame 1541 * to him. 1542 */ 1543 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1544 } 1545 1546 /* 1547 * If there are no packets queued, bail. 1548 */ 1549 if (cur_tx == NULL) { 1550 WB_UNLOCK(sc); 1551 return; 1552 } 1553 1554 /* 1555 * Place the request for the upload interrupt 1556 * in the last descriptor in the chain. This way, if 1557 * we're chaining several packets at once, we'll only 1558 * get an interupt once for the whole chain rather than 1559 * once for each packet. 1560 */ 1561 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1562 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1563 sc->wb_cdata.wb_tx_tail = cur_tx; 1564 1565 if (sc->wb_cdata.wb_tx_head == NULL) { 1566 sc->wb_cdata.wb_tx_head = start_tx; 1567 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1568 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1569 } else { 1570 /* 1571 * We need to distinguish between the case where 1572 * the own bit is clear because the chip cleared it 1573 * and where the own bit is clear because we haven't 1574 * set it yet. The magic value WB_UNSET is just some 1575 * ramdomly chosen number which doesn't have the own 1576 * bit set. When we actually transmit the frame, the 1577 * status word will have _only_ the own bit set, so 1578 * the txeoc handler will be able to tell if it needs 1579 * to initiate another transmission to flush out pending 1580 * frames. 1581 */ 1582 WB_TXOWN(start_tx) = WB_UNSENT; 1583 } 1584 1585 /* 1586 * Set a timeout in case the chip goes out to lunch. 1587 */ 1588 ifp->if_timer = 5; 1589 WB_UNLOCK(sc); 1590 1591 return; 1592} 1593 1594static void 1595wb_init(xsc) 1596 void *xsc; 1597{ 1598 struct wb_softc *sc = xsc; 1599 struct ifnet *ifp = &sc->arpcom.ac_if; 1600 int i; 1601 struct mii_data *mii; 1602 1603 WB_LOCK(sc); 1604 mii = device_get_softc(sc->wb_miibus); 1605 1606 /* 1607 * Cancel pending I/O and free all RX/TX buffers. 1608 */ 1609 wb_stop(sc); 1610 wb_reset(sc); 1611 1612 sc->wb_txthresh = WB_TXTHRESH_INIT; 1613 1614 /* 1615 * Set cache alignment and burst length. 1616 */ 1617#ifdef foo 1618 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1619 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1620 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1621#endif 1622 1623 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1624 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1625 switch(sc->wb_cachesize) { 1626 case 32: 1627 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1628 break; 1629 case 16: 1630 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1631 break; 1632 case 8: 1633 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1634 break; 1635 case 0: 1636 default: 1637 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1638 break; 1639 } 1640 1641 /* This doesn't tend to work too well at 100Mbps. */ 1642 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1643 1644 /* Init our MAC address */ 1645 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1646 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1647 } 1648 1649 /* Init circular RX list. */ 1650 if (wb_list_rx_init(sc) == ENOBUFS) { 1651 printf("wb%d: initialization failed: no " 1652 "memory for rx buffers\n", sc->wb_unit); 1653 wb_stop(sc); 1654 WB_UNLOCK(sc); 1655 return; 1656 } 1657 1658 /* Init TX descriptors. */ 1659 wb_list_tx_init(sc); 1660 1661 /* If we want promiscuous mode, set the allframes bit. */ 1662 if (ifp->if_flags & IFF_PROMISC) { 1663 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1664 } else { 1665 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1666 } 1667 1668 /* 1669 * Set capture broadcast bit to capture broadcast frames. 1670 */ 1671 if (ifp->if_flags & IFF_BROADCAST) { 1672 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1673 } else { 1674 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1675 } 1676 1677 /* 1678 * Program the multicast filter, if necessary. 1679 */ 1680 wb_setmulti(sc); 1681 1682 /* 1683 * Load the address of the RX list. 1684 */ 1685 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1686 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1687 1688 /* 1689 * Enable interrupts. 1690 */ 1691 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1692 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1693 1694 /* Enable receiver and transmitter. */ 1695 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1696 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1697 1698 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1699 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1700 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1701 1702 mii_mediachg(mii); 1703 1704 ifp->if_flags |= IFF_RUNNING; 1705 ifp->if_flags &= ~IFF_OACTIVE; 1706 1707 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1708 WB_UNLOCK(sc); 1709 1710 return; 1711} 1712 1713/* 1714 * Set media options. 1715 */ 1716static int 1717wb_ifmedia_upd(ifp) 1718 struct ifnet *ifp; 1719{ 1720 struct wb_softc *sc; 1721 1722 sc = ifp->if_softc; 1723 1724 if (ifp->if_flags & IFF_UP) 1725 wb_init(sc); 1726 1727 return(0); 1728} 1729 1730/* 1731 * Report current media status. 1732 */ 1733static void 1734wb_ifmedia_sts(ifp, ifmr) 1735 struct ifnet *ifp; 1736 struct ifmediareq *ifmr; 1737{ 1738 struct wb_softc *sc; 1739 struct mii_data *mii; 1740 1741 sc = ifp->if_softc; 1742 1743 mii = device_get_softc(sc->wb_miibus); 1744 1745 mii_pollstat(mii); 1746 ifmr->ifm_active = mii->mii_media_active; 1747 ifmr->ifm_status = mii->mii_media_status; 1748 1749 return; 1750} 1751 1752static int 1753wb_ioctl(ifp, command, data) 1754 struct ifnet *ifp; 1755 u_long command; 1756 caddr_t data; 1757{ 1758 struct wb_softc *sc = ifp->if_softc; 1759 struct mii_data *mii; 1760 struct ifreq *ifr = (struct ifreq *) data; 1761 int error = 0; 1762 1763 WB_LOCK(sc); 1764 1765 switch(command) { 1766 case SIOCSIFFLAGS: 1767 if (ifp->if_flags & IFF_UP) { 1768 wb_init(sc); 1769 } else { 1770 if (ifp->if_flags & IFF_RUNNING) 1771 wb_stop(sc); 1772 } 1773 error = 0; 1774 break; 1775 case SIOCADDMULTI: 1776 case SIOCDELMULTI: 1777 wb_setmulti(sc); 1778 error = 0; 1779 break; 1780 case SIOCGIFMEDIA: 1781 case SIOCSIFMEDIA: 1782 mii = device_get_softc(sc->wb_miibus); 1783 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1784 break; 1785 default: 1786 error = ether_ioctl(ifp, command, data); 1787 break; 1788 } 1789 1790 WB_UNLOCK(sc); 1791 1792 return(error); 1793} 1794 1795static void 1796wb_watchdog(ifp) 1797 struct ifnet *ifp; 1798{ 1799 struct wb_softc *sc; 1800 1801 sc = ifp->if_softc; 1802 1803 WB_LOCK(sc); 1804 ifp->if_oerrors++; 1805 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1806#ifdef foo 1807 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1808 printf("wb%d: no carrier - transceiver cable problem?\n", 1809 sc->wb_unit); 1810#endif 1811 wb_stop(sc); 1812 wb_reset(sc); 1813 wb_init(sc); 1814 1815 if (ifp->if_snd.ifq_head != NULL) 1816 wb_start(ifp); 1817 WB_UNLOCK(sc); 1818 1819 return; 1820} 1821 1822/* 1823 * Stop the adapter and free any mbufs allocated to the 1824 * RX and TX lists. 1825 */ 1826static void 1827wb_stop(sc) 1828 struct wb_softc *sc; 1829{ 1830 register int i; 1831 struct ifnet *ifp; 1832 1833 WB_LOCK(sc); 1834 ifp = &sc->arpcom.ac_if; 1835 ifp->if_timer = 0; 1836 1837 untimeout(wb_tick, sc, sc->wb_stat_ch); 1838 1839 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1840 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1841 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1842 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1843 1844 /* 1845 * Free data in the RX lists. 1846 */ 1847 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1848 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1849 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1850 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1851 } 1852 } 1853 bzero((char *)&sc->wb_ldata->wb_rx_list, 1854 sizeof(sc->wb_ldata->wb_rx_list)); 1855 1856 /* 1857 * Free the TX list buffers. 1858 */ 1859 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1860 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1861 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1862 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1863 } 1864 } 1865 1866 bzero((char *)&sc->wb_ldata->wb_tx_list, 1867 sizeof(sc->wb_ldata->wb_tx_list)); 1868 1869 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1870 WB_UNLOCK(sc); 1871 1872 return; 1873} 1874 1875/* 1876 * Stop all chip I/O so that the kernel's probe routines don't 1877 * get confused by errant DMAs when rebooting. 1878 */ 1879static void 1880wb_shutdown(dev) 1881 device_t dev; 1882{ 1883 struct wb_softc *sc; 1884 1885 sc = device_get_softc(dev); 1886 wb_stop(sc); 1887 1888 return; 1889} 1890