if_wb.c revision 113609
1191783Srmacklem/* 2191783Srmacklem * Copyright (c) 1997, 1998 3191783Srmacklem * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 4191783Srmacklem * 5191783Srmacklem * Redistribution and use in source and binary forms, with or without 6191783Srmacklem * modification, are permitted provided that the following conditions 7191783Srmacklem * are met: 8191783Srmacklem * 1. Redistributions of source code must retain the above copyright 9191783Srmacklem * notice, this list of conditions and the following disclaimer. 10191783Srmacklem * 2. Redistributions in binary form must reproduce the above copyright 11191783Srmacklem * notice, this list of conditions and the following disclaimer in the 12191783Srmacklem * documentation and/or other materials provided with the distribution. 13191783Srmacklem * 3. All advertising materials mentioning features or use of this software 14191783Srmacklem * must display the following acknowledgement: 15191783Srmacklem * This product includes software developed by Bill Paul. 16191783Srmacklem * 4. Neither the name of the author nor the names of any co-contributors 17191783Srmacklem * may be used to endorse or promote products derived from this software 18191783Srmacklem * without specific prior written permission. 19191783Srmacklem * 20191783Srmacklem * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21191783Srmacklem * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22191783Srmacklem * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23191783Srmacklem * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24191783Srmacklem * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25191783Srmacklem * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26191783Srmacklem * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27191783Srmacklem * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28191783Srmacklem * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29191783Srmacklem * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30191783Srmacklem * THE POSSIBILITY OF SUCH DAMAGE. 31191783Srmacklem */ 32191783Srmacklem 33191783Srmacklem/* 34191783Srmacklem * Winbond fast ethernet PCI NIC driver 35191783Srmacklem * 36191783Srmacklem * Supports various cheap network adapters based on the Winbond W89C840F 37191783Srmacklem * fast ethernet controller chip. This includes adapters manufactured by 38191783Srmacklem * Winbond itself and some made by Linksys. 39191783Srmacklem * 40191783Srmacklem * Written by Bill Paul <wpaul@ctr.columbia.edu> 41191783Srmacklem * Electrical Engineering Department 42191783Srmacklem * Columbia University, New York City 43191783Srmacklem */ 44191783Srmacklem 45191783Srmacklem/* 46191783Srmacklem * The Winbond W89C840F chip is a bus master; in some ways it resembles 47191783Srmacklem * a DEC 'tulip' chip, only not as complicated. Unfortunately, it has 48191783Srmacklem * one major difference which is that while the registers do many of 49191783Srmacklem * the same things as a tulip adapter, the offsets are different: where 50191783Srmacklem * tulip registers are typically spaced 8 bytes apart, the Winbond 51191783Srmacklem * registers are spaced 4 bytes apart. The receiver filter is also 52191783Srmacklem * programmed differently. 53191783Srmacklem * 54191783Srmacklem * Like the tulip, the Winbond chip uses small descriptors containing 55191783Srmacklem * a status word, a control word and 32-bit areas that can either be used 56191783Srmacklem * to point to two external data blocks, or to point to a single block 57191783Srmacklem * and another descriptor in a linked list. Descriptors can be grouped 58191783Srmacklem * together in blocks to form fixed length rings or can be chained 59191783Srmacklem * together in linked lists. A single packet may be spread out over 60191783Srmacklem * several descriptors if necessary. 61191783Srmacklem * 62191783Srmacklem * For the receive ring, this driver uses a linked list of descriptors, 63191783Srmacklem * each pointing to a single mbuf cluster buffer, which us large enough 64191783Srmacklem * to hold an entire packet. The link list is looped back to created a 65191783Srmacklem * closed ring. 66191783Srmacklem * 67191783Srmacklem * For transmission, the driver creates a linked list of 'super descriptors' 68191783Srmacklem * which each contain several individual descriptors linked toghether. 69191783Srmacklem * Each 'super descriptor' contains WB_MAXFRAGS descriptors, which we 70191783Srmacklem * abuse as fragment pointers. This allows us to use a buffer managment 71191783Srmacklem * scheme very similar to that used in the ThunderLAN and Etherlink XL 72191783Srmacklem * drivers. 73191783Srmacklem * 74191783Srmacklem * Autonegotiation is performed using the external PHY via the MII bus. 75191783Srmacklem * The sample boards I have all use a Davicom PHY. 76191783Srmacklem * 77191783Srmacklem * Note: the author of the Linux driver for the Winbond chip alludes 78191783Srmacklem * to some sort of flaw in the chip's design that seems to mandate some 79191783Srmacklem * drastic workaround which signigicantly impairs transmit performance. 80191783Srmacklem * I have no idea what he's on about: transmit performance with all 81191783Srmacklem * three of my test boards seems fine. 82191783Srmacklem */ 83191783Srmacklem 84191783Srmacklem#include <sys/cdefs.h> 85191783Srmacklem__FBSDID("$FreeBSD: head/sys/pci/if_wb.c 113609 2003-04-17 20:32:06Z njl $"); 86191783Srmacklem 87191783Srmacklem#include "opt_bdg.h" 88191783Srmacklem 89191783Srmacklem#include <sys/param.h> 90191783Srmacklem#include <sys/systm.h> 91191783Srmacklem#include <sys/sockio.h> 92191783Srmacklem#include <sys/mbuf.h> 93191783Srmacklem#include <sys/malloc.h> 94191783Srmacklem#include <sys/kernel.h> 95191783Srmacklem#include <sys/socket.h> 96191783Srmacklem#include <sys/queue.h> 97191783Srmacklem 98191783Srmacklem#include <net/if.h> 99191783Srmacklem#include <net/if_arp.h> 100191783Srmacklem#include <net/ethernet.h> 101191783Srmacklem#include <net/if_dl.h> 102191783Srmacklem#include <net/if_media.h> 103191783Srmacklem 104191783Srmacklem#include <net/bpf.h> 105191783Srmacklem 106191783Srmacklem#include <vm/vm.h> /* for vtophys */ 107191783Srmacklem#include <vm/pmap.h> /* for vtophys */ 108191783Srmacklem#include <machine/bus_memio.h> 109191783Srmacklem#include <machine/bus_pio.h> 110191783Srmacklem#include <machine/bus.h> 111191783Srmacklem#include <machine/resource.h> 112191783Srmacklem#include <sys/bus.h> 113191783Srmacklem#include <sys/rman.h> 114191783Srmacklem 115191783Srmacklem#include <pci/pcireg.h> 116191783Srmacklem#include <pci/pcivar.h> 117191783Srmacklem 118191783Srmacklem#include <dev/mii/mii.h> 119191783Srmacklem#include <dev/mii/miivar.h> 120191783Srmacklem 121191783Srmacklem/* "controller miibus0" required. See GENERIC if you get errors here. */ 122191783Srmacklem#include "miibus_if.h" 123191783Srmacklem 124191783Srmacklem#define WB_USEIOSPACE 125191783Srmacklem 126191783Srmacklem#include <pci/if_wbreg.h> 127191783Srmacklem 128191783SrmacklemMODULE_DEPEND(wb, pci, 1, 1, 1); 129191783SrmacklemMODULE_DEPEND(wb, ether, 1, 1, 1); 130191783SrmacklemMODULE_DEPEND(wb, miibus, 1, 1, 1); 131191783Srmacklem 132191783Srmacklem/* 133191783Srmacklem * Various supported device vendors/types and their names. 134191783Srmacklem */ 135191783Srmacklemstatic struct wb_type wb_devs[] = { 136191783Srmacklem { WB_VENDORID, WB_DEVICEID_840F, 137191783Srmacklem "Winbond W89C840F 10/100BaseTX" }, 138191783Srmacklem { CP_VENDORID, CP_DEVICEID_RL100, 139191783Srmacklem "Compex RL100-ATX 10/100baseTX" }, 140191783Srmacklem { 0, 0, NULL } 141191783Srmacklem}; 142191783Srmacklem 143191783Srmacklemstatic int wb_probe (device_t); 144191783Srmacklemstatic int wb_attach (device_t); 145191783Srmacklemstatic int wb_detach (device_t); 146191783Srmacklem 147191783Srmacklemstatic void wb_bfree (void *addr, void *args); 148191783Srmacklemstatic int wb_newbuf (struct wb_softc *, 149191783Srmacklem struct wb_chain_onefrag *, 150191783Srmacklem struct mbuf *); 151191783Srmacklemstatic int wb_encap (struct wb_softc *, struct wb_chain *, 152191783Srmacklem struct mbuf *); 153191783Srmacklem 154191783Srmacklemstatic void wb_rxeof (struct wb_softc *); 155191783Srmacklemstatic void wb_rxeoc (struct wb_softc *); 156191783Srmacklemstatic void wb_txeof (struct wb_softc *); 157191783Srmacklemstatic void wb_txeoc (struct wb_softc *); 158191783Srmacklemstatic void wb_intr (void *); 159191783Srmacklemstatic void wb_tick (void *); 160191783Srmacklemstatic void wb_start (struct ifnet *); 161191783Srmacklemstatic int wb_ioctl (struct ifnet *, u_long, caddr_t); 162191783Srmacklemstatic void wb_init (void *); 163191783Srmacklemstatic void wb_stop (struct wb_softc *); 164191783Srmacklemstatic void wb_watchdog (struct ifnet *); 165191783Srmacklemstatic void wb_shutdown (device_t); 166191783Srmacklemstatic int wb_ifmedia_upd (struct ifnet *); 167191783Srmacklemstatic void wb_ifmedia_sts (struct ifnet *, struct ifmediareq *); 168191783Srmacklem 169191783Srmacklemstatic void wb_eeprom_putbyte (struct wb_softc *, int); 170191783Srmacklemstatic void wb_eeprom_getword (struct wb_softc *, int, u_int16_t *); 171191783Srmacklemstatic void wb_read_eeprom (struct wb_softc *, caddr_t, int, int, int); 172191783Srmacklemstatic void wb_mii_sync (struct wb_softc *); 173191783Srmacklemstatic void wb_mii_send (struct wb_softc *, u_int32_t, int); 174191783Srmacklemstatic int wb_mii_readreg (struct wb_softc *, struct wb_mii_frame *); 175191783Srmacklemstatic int wb_mii_writereg (struct wb_softc *, struct wb_mii_frame *); 176191783Srmacklem 177191783Srmacklemstatic void wb_setcfg (struct wb_softc *, u_int32_t); 178191783Srmacklemstatic u_int8_t wb_calchash (caddr_t); 179191783Srmacklemstatic void wb_setmulti (struct wb_softc *); 180191783Srmacklemstatic void wb_reset (struct wb_softc *); 181191783Srmacklemstatic void wb_fixmedia (struct wb_softc *); 182191783Srmacklemstatic int wb_list_rx_init (struct wb_softc *); 183191783Srmacklemstatic int wb_list_tx_init (struct wb_softc *); 184191783Srmacklem 185191783Srmacklemstatic int wb_miibus_readreg (device_t, int, int); 186191783Srmacklemstatic int wb_miibus_writereg (device_t, int, int, int); 187191783Srmacklemstatic void wb_miibus_statchg (device_t); 188191783Srmacklem 189192152Srmacklem#ifdef WB_USEIOSPACE 190192152Srmacklem#define WB_RES SYS_RES_IOPORT 191192152Srmacklem#define WB_RID WB_PCI_LOIO 192192152Srmacklem#else 193192152Srmacklem#define WB_RES SYS_RES_MEMORY 194192152Srmacklem#define WB_RID WB_PCI_LOMEM 195192152Srmacklem#endif 196192152Srmacklem 197192152Srmacklemstatic device_method_t wb_methods[] = { 198192152Srmacklem /* Device interface */ 199192152Srmacklem DEVMETHOD(device_probe, wb_probe), 200192152Srmacklem DEVMETHOD(device_attach, wb_attach), 201192152Srmacklem DEVMETHOD(device_detach, wb_detach), 202192152Srmacklem DEVMETHOD(device_shutdown, wb_shutdown), 203192152Srmacklem 204192152Srmacklem /* bus interface, for miibus */ 205192152Srmacklem DEVMETHOD(bus_print_child, bus_generic_print_child), 206192152Srmacklem DEVMETHOD(bus_driver_added, bus_generic_driver_added), 207192152Srmacklem 208192152Srmacklem /* MII interface */ 209192152Srmacklem DEVMETHOD(miibus_readreg, wb_miibus_readreg), 210192152Srmacklem DEVMETHOD(miibus_writereg, wb_miibus_writereg), 211192152Srmacklem DEVMETHOD(miibus_statchg, wb_miibus_statchg), 212192152Srmacklem { 0, 0 } 213192152Srmacklem}; 214192152Srmacklem 215192152Srmacklemstatic driver_t wb_driver = { 216192152Srmacklem "wb", 217192152Srmacklem wb_methods, 218192152Srmacklem sizeof(struct wb_softc) 219192152Srmacklem}; 220192152Srmacklem 221192152Srmacklemstatic devclass_t wb_devclass; 222192152Srmacklem 223192152SrmacklemDRIVER_MODULE(wb, pci, wb_driver, wb_devclass, 0, 0); 224192152SrmacklemDRIVER_MODULE(miibus, wb, miibus_driver, miibus_devclass, 0, 0); 225192152Srmacklem 226192152Srmacklem#define WB_SETBIT(sc, reg, x) \ 227192152Srmacklem CSR_WRITE_4(sc, reg, \ 228192152Srmacklem CSR_READ_4(sc, reg) | (x)) 229192152Srmacklem 230192152Srmacklem#define WB_CLRBIT(sc, reg, x) \ 231192152Srmacklem CSR_WRITE_4(sc, reg, \ 232192152Srmacklem CSR_READ_4(sc, reg) & ~(x)) 233192152Srmacklem 234192152Srmacklem#define SIO_SET(x) \ 235192152Srmacklem CSR_WRITE_4(sc, WB_SIO, \ 236192152Srmacklem CSR_READ_4(sc, WB_SIO) | (x)) 237192152Srmacklem 238192152Srmacklem#define SIO_CLR(x) \ 239192152Srmacklem CSR_WRITE_4(sc, WB_SIO, \ 240192152Srmacklem CSR_READ_4(sc, WB_SIO) & ~(x)) 241192152Srmacklem 242192152Srmacklem/* 243192152Srmacklem * Send a read command and address to the EEPROM, check for ACK. 244192152Srmacklem */ 245192152Srmacklemstatic void 246192152Srmacklemwb_eeprom_putbyte(sc, addr) 247192152Srmacklem struct wb_softc *sc; 248192152Srmacklem int addr; 249192152Srmacklem{ 250192152Srmacklem register int d, i; 251192152Srmacklem 252192152Srmacklem d = addr | WB_EECMD_READ; 253192152Srmacklem 254192152Srmacklem /* 255192152Srmacklem * Feed in each bit and stobe the clock. 256192152Srmacklem */ 257192152Srmacklem for (i = 0x400; i; i >>= 1) { 258192152Srmacklem if (d & i) { 259192152Srmacklem SIO_SET(WB_SIO_EE_DATAIN); 260192152Srmacklem } else { 261192152Srmacklem SIO_CLR(WB_SIO_EE_DATAIN); 262192152Srmacklem } 263192152Srmacklem DELAY(100); 264192152Srmacklem SIO_SET(WB_SIO_EE_CLK); 265192152Srmacklem DELAY(150); 266192152Srmacklem SIO_CLR(WB_SIO_EE_CLK); 267192152Srmacklem DELAY(100); 268192152Srmacklem } 269192152Srmacklem 270192152Srmacklem return; 271192152Srmacklem} 272192152Srmacklem 273192152Srmacklem/* 274192152Srmacklem * Read a word of data stored in the EEPROM at address 'addr.' 275192152Srmacklem */ 276192152Srmacklemstatic void 277192152Srmacklemwb_eeprom_getword(sc, addr, dest) 278192152Srmacklem struct wb_softc *sc; 279192152Srmacklem int addr; 280192152Srmacklem u_int16_t *dest; 281192152Srmacklem{ 282192152Srmacklem register int i; 283192152Srmacklem u_int16_t word = 0; 284192152Srmacklem 285192152Srmacklem /* Enter EEPROM access mode. */ 286192152Srmacklem CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 287192152Srmacklem 288192152Srmacklem /* 289192152Srmacklem * Send address of word we want to read. 290192152Srmacklem */ 291192152Srmacklem wb_eeprom_putbyte(sc, addr); 292192152Srmacklem 293192152Srmacklem CSR_WRITE_4(sc, WB_SIO, WB_SIO_EESEL|WB_SIO_EE_CS); 294192152Srmacklem 295192152Srmacklem /* 296192152Srmacklem * Start reading bits from EEPROM. 297192152Srmacklem */ 298192152Srmacklem for (i = 0x8000; i; i >>= 1) { 299192152Srmacklem SIO_SET(WB_SIO_EE_CLK); 300192152Srmacklem DELAY(100); 301192152Srmacklem if (CSR_READ_4(sc, WB_SIO) & WB_SIO_EE_DATAOUT) 302192152Srmacklem word |= i; 303192152Srmacklem SIO_CLR(WB_SIO_EE_CLK); 304192152Srmacklem DELAY(100); 305192152Srmacklem } 306192152Srmacklem 307192152Srmacklem /* Turn off EEPROM access mode. */ 308192152Srmacklem CSR_WRITE_4(sc, WB_SIO, 0); 309192152Srmacklem 310192152Srmacklem *dest = word; 311192152Srmacklem 312192152Srmacklem return; 313192152Srmacklem} 314192152Srmacklem 315192152Srmacklem/* 316192152Srmacklem * Read a sequence of words from the EEPROM. 317192152Srmacklem */ 318192152Srmacklemstatic void 319192152Srmacklemwb_read_eeprom(sc, dest, off, cnt, swap) 320192152Srmacklem struct wb_softc *sc; 321192152Srmacklem caddr_t dest; 322192152Srmacklem int off; 323192152Srmacklem int cnt; 324192152Srmacklem int swap; 325192152Srmacklem{ 326192152Srmacklem int i; 327192152Srmacklem u_int16_t word = 0, *ptr; 328192152Srmacklem 329192152Srmacklem for (i = 0; i < cnt; i++) { 330192152Srmacklem wb_eeprom_getword(sc, off + i, &word); 331192152Srmacklem ptr = (u_int16_t *)(dest + (i * 2)); 332192152Srmacklem if (swap) 333192152Srmacklem *ptr = ntohs(word); 334192152Srmacklem else 335192152Srmacklem *ptr = word; 336192152Srmacklem } 337192152Srmacklem 338192152Srmacklem return; 339192152Srmacklem} 340192152Srmacklem 341192152Srmacklem/* 342192152Srmacklem * Sync the PHYs by setting data bit and strobing the clock 32 times. 343192152Srmacklem */ 344192152Srmacklemstatic void 345192152Srmacklemwb_mii_sync(sc) 346192152Srmacklem struct wb_softc *sc; 347192152Srmacklem{ 348192152Srmacklem register int i; 349192152Srmacklem 350192152Srmacklem SIO_SET(WB_SIO_MII_DIR|WB_SIO_MII_DATAIN); 351192152Srmacklem 352192152Srmacklem for (i = 0; i < 32; i++) { 353192152Srmacklem SIO_SET(WB_SIO_MII_CLK); 354192152Srmacklem DELAY(1); 355192152Srmacklem SIO_CLR(WB_SIO_MII_CLK); 356192152Srmacklem DELAY(1); 357192152Srmacklem } 358192152Srmacklem 359192152Srmacklem return; 360192152Srmacklem} 361192152Srmacklem 362192152Srmacklem/* 363192152Srmacklem * Clock a series of bits through the MII. 364192152Srmacklem */ 365191783Srmacklemstatic void 366191783Srmacklemwb_mii_send(sc, bits, cnt) 367191783Srmacklem struct wb_softc *sc; 368191783Srmacklem u_int32_t bits; 369191783Srmacklem int cnt; 370191783Srmacklem{ 371191783Srmacklem int i; 372191783Srmacklem 373191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 374191783Srmacklem 375191783Srmacklem for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 376191783Srmacklem if (bits & i) { 377191783Srmacklem SIO_SET(WB_SIO_MII_DATAIN); 378191783Srmacklem } else { 379191783Srmacklem SIO_CLR(WB_SIO_MII_DATAIN); 380191783Srmacklem } 381191783Srmacklem DELAY(1); 382191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 383191783Srmacklem DELAY(1); 384191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 385191783Srmacklem } 386191783Srmacklem} 387191783Srmacklem 388191783Srmacklem/* 389191783Srmacklem * Read an PHY register through the MII. 390191783Srmacklem */ 391191783Srmacklemstatic int 392191783Srmacklemwb_mii_readreg(sc, frame) 393191783Srmacklem struct wb_softc *sc; 394191783Srmacklem struct wb_mii_frame *frame; 395191783Srmacklem 396191783Srmacklem{ 397191783Srmacklem int i, ack; 398191783Srmacklem 399191783Srmacklem WB_LOCK(sc); 400191783Srmacklem 401191783Srmacklem /* 402191783Srmacklem * Set up frame for RX. 403191783Srmacklem */ 404191783Srmacklem frame->mii_stdelim = WB_MII_STARTDELIM; 405191783Srmacklem frame->mii_opcode = WB_MII_READOP; 406191783Srmacklem frame->mii_turnaround = 0; 407191783Srmacklem frame->mii_data = 0; 408191783Srmacklem 409191783Srmacklem CSR_WRITE_4(sc, WB_SIO, 0); 410191783Srmacklem 411191783Srmacklem /* 412191783Srmacklem * Turn on data xmit. 413191783Srmacklem */ 414191783Srmacklem SIO_SET(WB_SIO_MII_DIR); 415191783Srmacklem 416191783Srmacklem wb_mii_sync(sc); 417191783Srmacklem 418191783Srmacklem /* 419191783Srmacklem * Send command/address info. 420191783Srmacklem */ 421191783Srmacklem wb_mii_send(sc, frame->mii_stdelim, 2); 422191783Srmacklem wb_mii_send(sc, frame->mii_opcode, 2); 423191783Srmacklem wb_mii_send(sc, frame->mii_phyaddr, 5); 424191783Srmacklem wb_mii_send(sc, frame->mii_regaddr, 5); 425191783Srmacklem 426191783Srmacklem /* Idle bit */ 427191783Srmacklem SIO_CLR((WB_SIO_MII_CLK|WB_SIO_MII_DATAIN)); 428191783Srmacklem DELAY(1); 429191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 430191783Srmacklem DELAY(1); 431191783Srmacklem 432191783Srmacklem /* Turn off xmit. */ 433191783Srmacklem SIO_CLR(WB_SIO_MII_DIR); 434191783Srmacklem /* Check for ack */ 435191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 436191783Srmacklem DELAY(1); 437191783Srmacklem ack = CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT; 438191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 439191783Srmacklem DELAY(1); 440191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 441191783Srmacklem DELAY(1); 442191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 443191783Srmacklem DELAY(1); 444191783Srmacklem 445191783Srmacklem /* 446191783Srmacklem * Now try reading data bits. If the ack failed, we still 447191783Srmacklem * need to clock through 16 cycles to keep the PHY(s) in sync. 448191783Srmacklem */ 449191783Srmacklem if (ack) { 450191783Srmacklem for(i = 0; i < 16; i++) { 451191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 452191783Srmacklem DELAY(1); 453191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 454191783Srmacklem DELAY(1); 455191783Srmacklem } 456191783Srmacklem goto fail; 457191783Srmacklem } 458191783Srmacklem 459191783Srmacklem for (i = 0x8000; i; i >>= 1) { 460191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 461191783Srmacklem DELAY(1); 462191783Srmacklem if (!ack) { 463191783Srmacklem if (CSR_READ_4(sc, WB_SIO) & WB_SIO_MII_DATAOUT) 464191783Srmacklem frame->mii_data |= i; 465191783Srmacklem DELAY(1); 466191783Srmacklem } 467191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 468191783Srmacklem DELAY(1); 469191783Srmacklem } 470191783Srmacklem 471191783Srmacklemfail: 472191783Srmacklem 473191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 474191783Srmacklem DELAY(1); 475191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 476191783Srmacklem DELAY(1); 477191783Srmacklem 478191783Srmacklem WB_UNLOCK(sc); 479191783Srmacklem 480191783Srmacklem if (ack) 481191783Srmacklem return(1); 482191783Srmacklem return(0); 483191783Srmacklem} 484191783Srmacklem 485191783Srmacklem/* 486191783Srmacklem * Write to a PHY register through the MII. 487191783Srmacklem */ 488191783Srmacklemstatic int 489191783Srmacklemwb_mii_writereg(sc, frame) 490191783Srmacklem struct wb_softc *sc; 491191783Srmacklem struct wb_mii_frame *frame; 492191783Srmacklem 493191783Srmacklem{ 494191783Srmacklem WB_LOCK(sc); 495191783Srmacklem 496191783Srmacklem /* 497191783Srmacklem * Set up frame for TX. 498191783Srmacklem */ 499191783Srmacklem 500191783Srmacklem frame->mii_stdelim = WB_MII_STARTDELIM; 501191783Srmacklem frame->mii_opcode = WB_MII_WRITEOP; 502191783Srmacklem frame->mii_turnaround = WB_MII_TURNAROUND; 503191783Srmacklem 504191783Srmacklem /* 505191783Srmacklem * Turn on data output. 506191783Srmacklem */ 507191783Srmacklem SIO_SET(WB_SIO_MII_DIR); 508191783Srmacklem 509191783Srmacklem wb_mii_sync(sc); 510191783Srmacklem 511191783Srmacklem wb_mii_send(sc, frame->mii_stdelim, 2); 512191783Srmacklem wb_mii_send(sc, frame->mii_opcode, 2); 513191783Srmacklem wb_mii_send(sc, frame->mii_phyaddr, 5); 514191783Srmacklem wb_mii_send(sc, frame->mii_regaddr, 5); 515191783Srmacklem wb_mii_send(sc, frame->mii_turnaround, 2); 516191783Srmacklem wb_mii_send(sc, frame->mii_data, 16); 517191783Srmacklem 518191783Srmacklem /* Idle bit. */ 519191783Srmacklem SIO_SET(WB_SIO_MII_CLK); 520191783Srmacklem DELAY(1); 521191783Srmacklem SIO_CLR(WB_SIO_MII_CLK); 522191783Srmacklem DELAY(1); 523191783Srmacklem 524191783Srmacklem /* 525191783Srmacklem * Turn off xmit. 526191783Srmacklem */ 527191783Srmacklem SIO_CLR(WB_SIO_MII_DIR); 528191783Srmacklem 529191783Srmacklem WB_UNLOCK(sc); 530191783Srmacklem 531191783Srmacklem return(0); 532191783Srmacklem} 533191783Srmacklem 534191783Srmacklemstatic int 535191783Srmacklemwb_miibus_readreg(dev, phy, reg) 536191783Srmacklem device_t dev; 537191783Srmacklem int phy, reg; 538191783Srmacklem{ 539191783Srmacklem struct wb_softc *sc; 540191783Srmacklem struct wb_mii_frame frame; 541191783Srmacklem 542191783Srmacklem sc = device_get_softc(dev); 543191783Srmacklem 544191783Srmacklem bzero((char *)&frame, sizeof(frame)); 545191783Srmacklem 546191783Srmacklem frame.mii_phyaddr = phy; 547191783Srmacklem frame.mii_regaddr = reg; 548191783Srmacklem wb_mii_readreg(sc, &frame); 549191783Srmacklem 550191783Srmacklem return(frame.mii_data); 551191783Srmacklem} 552191783Srmacklem 553191783Srmacklemstatic int 554191783Srmacklemwb_miibus_writereg(dev, phy, reg, data) 555191783Srmacklem device_t dev; 556191783Srmacklem int phy, reg, data; 557191783Srmacklem{ 558191783Srmacklem struct wb_softc *sc; 559191783Srmacklem struct wb_mii_frame frame; 560191783Srmacklem 561191783Srmacklem sc = device_get_softc(dev); 562191783Srmacklem 563191783Srmacklem bzero((char *)&frame, sizeof(frame)); 564191783Srmacklem 565191783Srmacklem frame.mii_phyaddr = phy; 566191783Srmacklem frame.mii_regaddr = reg; 567191783Srmacklem frame.mii_data = data; 568191783Srmacklem 569191783Srmacklem wb_mii_writereg(sc, &frame); 570191783Srmacklem 571191783Srmacklem return(0); 572191783Srmacklem} 573191783Srmacklem 574191783Srmacklemstatic void 575191783Srmacklemwb_miibus_statchg(dev) 576191783Srmacklem device_t dev; 577191783Srmacklem{ 578191783Srmacklem struct wb_softc *sc; 579191783Srmacklem struct mii_data *mii; 580191783Srmacklem 581191783Srmacklem sc = device_get_softc(dev); 582191783Srmacklem WB_LOCK(sc); 583191783Srmacklem mii = device_get_softc(sc->wb_miibus); 584191783Srmacklem wb_setcfg(sc, mii->mii_media_active); 585191783Srmacklem WB_UNLOCK(sc); 586191783Srmacklem 587191783Srmacklem return; 588191783Srmacklem} 589191783Srmacklem 590191783Srmacklemstatic u_int8_t wb_calchash(addr) 591191783Srmacklem caddr_t addr; 592191783Srmacklem{ 593191783Srmacklem u_int32_t crc, carry; 594191783Srmacklem int i, j; 595191783Srmacklem u_int8_t c; 596191783Srmacklem 597191783Srmacklem /* Compute CRC for the address value. */ 598191783Srmacklem crc = 0xFFFFFFFF; /* initial value */ 599191783Srmacklem 600191783Srmacklem for (i = 0; i < 6; i++) { 601191783Srmacklem c = *(addr + i); 602191783Srmacklem for (j = 0; j < 8; j++) { 603191783Srmacklem carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 604191783Srmacklem crc <<= 1; 605191783Srmacklem c >>= 1; 606191783Srmacklem if (carry) 607191783Srmacklem crc = (crc ^ 0x04c11db6) | carry; 608191783Srmacklem } 609191783Srmacklem } 610191783Srmacklem 611191783Srmacklem /* 612191783Srmacklem * return the filter bit position 613191783Srmacklem * Note: I arrived at the following nonsense 614191783Srmacklem * through experimentation. It's not the usual way to 615191783Srmacklem * generate the bit position but it's the only thing 616191783Srmacklem * I could come up with that works. 617191783Srmacklem */ 618191783Srmacklem return(~(crc >> 26) & 0x0000003F); 619191783Srmacklem} 620191783Srmacklem 621191783Srmacklem/* 622191783Srmacklem * Program the 64-bit multicast hash filter. 623191783Srmacklem */ 624191783Srmacklemstatic void 625191783Srmacklemwb_setmulti(sc) 626191783Srmacklem struct wb_softc *sc; 627191783Srmacklem{ 628191783Srmacklem struct ifnet *ifp; 629191783Srmacklem int h = 0; 630191783Srmacklem u_int32_t hashes[2] = { 0, 0 }; 631191783Srmacklem struct ifmultiaddr *ifma; 632191783Srmacklem u_int32_t rxfilt; 633191783Srmacklem int mcnt = 0; 634191783Srmacklem 635191783Srmacklem ifp = &sc->arpcom.ac_if; 636191783Srmacklem 637191783Srmacklem rxfilt = CSR_READ_4(sc, WB_NETCFG); 638191783Srmacklem 639191783Srmacklem if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 640191783Srmacklem rxfilt |= WB_NETCFG_RX_MULTI; 641191783Srmacklem CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 642191783Srmacklem CSR_WRITE_4(sc, WB_MAR0, 0xFFFFFFFF); 643191783Srmacklem CSR_WRITE_4(sc, WB_MAR1, 0xFFFFFFFF); 644191783Srmacklem return; 645191783Srmacklem } 646191783Srmacklem 647191783Srmacklem /* first, zot all the existing hash bits */ 648191783Srmacklem CSR_WRITE_4(sc, WB_MAR0, 0); 649191783Srmacklem CSR_WRITE_4(sc, WB_MAR1, 0); 650191783Srmacklem 651191783Srmacklem /* now program new ones */ 652191783Srmacklem TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 653191783Srmacklem if (ifma->ifma_addr->sa_family != AF_LINK) 654191783Srmacklem continue; 655191783Srmacklem h = wb_calchash(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 656191783Srmacklem if (h < 32) 657191783Srmacklem hashes[0] |= (1 << h); 658191783Srmacklem else 659191783Srmacklem hashes[1] |= (1 << (h - 32)); 660191783Srmacklem mcnt++; 661191783Srmacklem } 662191783Srmacklem 663191783Srmacklem if (mcnt) 664191783Srmacklem rxfilt |= WB_NETCFG_RX_MULTI; 665191783Srmacklem else 666191783Srmacklem rxfilt &= ~WB_NETCFG_RX_MULTI; 667191783Srmacklem 668191783Srmacklem CSR_WRITE_4(sc, WB_MAR0, hashes[0]); 669191783Srmacklem CSR_WRITE_4(sc, WB_MAR1, hashes[1]); 670191783Srmacklem CSR_WRITE_4(sc, WB_NETCFG, rxfilt); 671191783Srmacklem 672191783Srmacklem return; 673191783Srmacklem} 674191783Srmacklem 675191783Srmacklem/* 676191783Srmacklem * The Winbond manual states that in order to fiddle with the 677191783Srmacklem * 'full-duplex' and '100Mbps' bits in the netconfig register, we 678191783Srmacklem * first have to put the transmit and/or receive logic in the idle state. 679191783Srmacklem */ 680191783Srmacklemstatic void 681191783Srmacklemwb_setcfg(sc, media) 682191783Srmacklem struct wb_softc *sc; 683191783Srmacklem u_int32_t media; 684191783Srmacklem{ 685191783Srmacklem int i, restart = 0; 686191783Srmacklem 687191783Srmacklem if (CSR_READ_4(sc, WB_NETCFG) & (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)) { 688191783Srmacklem restart = 1; 689191783Srmacklem WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_TX_ON|WB_NETCFG_RX_ON)); 690191783Srmacklem 691191783Srmacklem for (i = 0; i < WB_TIMEOUT; i++) { 692191783Srmacklem DELAY(10); 693191783Srmacklem if ((CSR_READ_4(sc, WB_ISR) & WB_ISR_TX_IDLE) && 694191783Srmacklem (CSR_READ_4(sc, WB_ISR) & WB_ISR_RX_IDLE)) 695191783Srmacklem break; 696191783Srmacklem } 697191783Srmacklem 698191783Srmacklem if (i == WB_TIMEOUT) 699191783Srmacklem printf("wb%d: failed to force tx and " 700191783Srmacklem "rx to idle state\n", sc->wb_unit); 701191783Srmacklem } 702191783Srmacklem 703191783Srmacklem if (IFM_SUBTYPE(media) == IFM_10_T) 704191783Srmacklem WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 705191783Srmacklem else 706191783Srmacklem WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_100MBPS); 707191783Srmacklem 708191783Srmacklem if ((media & IFM_GMASK) == IFM_FDX) 709191783Srmacklem WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 710191783Srmacklem else 711191783Srmacklem WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_FULLDUPLEX); 712191783Srmacklem 713191783Srmacklem if (restart) 714191783Srmacklem WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON|WB_NETCFG_RX_ON); 715191783Srmacklem 716191783Srmacklem return; 717191783Srmacklem} 718191783Srmacklem 719191783Srmacklemstatic void 720191783Srmacklemwb_reset(sc) 721191783Srmacklem struct wb_softc *sc; 722191783Srmacklem{ 723191783Srmacklem register int i; 724191783Srmacklem struct mii_data *mii; 725191783Srmacklem 726191783Srmacklem CSR_WRITE_4(sc, WB_NETCFG, 0); 727191783Srmacklem CSR_WRITE_4(sc, WB_BUSCTL, 0); 728191783Srmacklem CSR_WRITE_4(sc, WB_TXADDR, 0); 729191783Srmacklem CSR_WRITE_4(sc, WB_RXADDR, 0); 730191783Srmacklem 731191783Srmacklem WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 732191783Srmacklem WB_SETBIT(sc, WB_BUSCTL, WB_BUSCTL_RESET); 733191783Srmacklem 734191783Srmacklem for (i = 0; i < WB_TIMEOUT; i++) { 735191783Srmacklem DELAY(10); 736191783Srmacklem if (!(CSR_READ_4(sc, WB_BUSCTL) & WB_BUSCTL_RESET)) 737191783Srmacklem break; 738191783Srmacklem } 739191783Srmacklem if (i == WB_TIMEOUT) 740191783Srmacklem printf("wb%d: reset never completed!\n", sc->wb_unit); 741191783Srmacklem 742191783Srmacklem /* Wait a little while for the chip to get its brains in order. */ 743191783Srmacklem DELAY(1000); 744191783Srmacklem 745191783Srmacklem if (sc->wb_miibus == NULL) 746191783Srmacklem return; 747191783Srmacklem 748191783Srmacklem mii = device_get_softc(sc->wb_miibus); 749191783Srmacklem if (mii == NULL) 750191783Srmacklem return; 751191783Srmacklem 752191783Srmacklem if (mii->mii_instance) { 753191783Srmacklem struct mii_softc *miisc; 754191783Srmacklem LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 755191783Srmacklem mii_phy_reset(miisc); 756191783Srmacklem } 757191783Srmacklem 758191783Srmacklem return; 759191783Srmacklem} 760191783Srmacklem 761191783Srmacklemstatic void 762191783Srmacklemwb_fixmedia(sc) 763191783Srmacklem struct wb_softc *sc; 764191783Srmacklem{ 765191783Srmacklem struct mii_data *mii = NULL; 766191783Srmacklem struct ifnet *ifp; 767191783Srmacklem u_int32_t media; 768191783Srmacklem 769191783Srmacklem if (sc->wb_miibus == NULL) 770191783Srmacklem return; 771191783Srmacklem 772191783Srmacklem mii = device_get_softc(sc->wb_miibus); 773191783Srmacklem ifp = &sc->arpcom.ac_if; 774191783Srmacklem 775191783Srmacklem mii_pollstat(mii); 776191783Srmacklem if (IFM_SUBTYPE(mii->mii_media_active) == IFM_10_T) { 777191783Srmacklem media = mii->mii_media_active & ~IFM_10_T; 778191783Srmacklem media |= IFM_100_TX; 779191783Srmacklem } else if (IFM_SUBTYPE(mii->mii_media_active) == IFM_100_TX) { 780191783Srmacklem media = mii->mii_media_active & ~IFM_100_TX; 781191783Srmacklem media |= IFM_10_T; 782191783Srmacklem } else 783191783Srmacklem return; 784191783Srmacklem 785191783Srmacklem ifmedia_set(&mii->mii_media, media); 786191783Srmacklem 787191783Srmacklem return; 788191783Srmacklem} 789191783Srmacklem 790191783Srmacklem/* 791191783Srmacklem * Probe for a Winbond chip. Check the PCI vendor and device 792191783Srmacklem * IDs against our list and return a device name if we find a match. 793191783Srmacklem */ 794191783Srmacklemstatic int 795191783Srmacklemwb_probe(dev) 796191783Srmacklem device_t dev; 797191783Srmacklem{ 798191783Srmacklem struct wb_type *t; 799191783Srmacklem 800191783Srmacklem t = wb_devs; 801191783Srmacklem 802191783Srmacklem while(t->wb_name != NULL) { 803191783Srmacklem if ((pci_get_vendor(dev) == t->wb_vid) && 804191783Srmacklem (pci_get_device(dev) == t->wb_did)) { 805191783Srmacklem device_set_desc(dev, t->wb_name); 806191783Srmacklem return(0); 807191783Srmacklem } 808191783Srmacklem t++; 809191783Srmacklem } 810191783Srmacklem 811191783Srmacklem return(ENXIO); 812191783Srmacklem} 813191783Srmacklem 814191783Srmacklem/* 815191783Srmacklem * Attach the interface. Allocate softc structures, do ifmedia 816191783Srmacklem * setup and ethernet/BPF attach. 817191783Srmacklem */ 818191783Srmacklemstatic int 819191783Srmacklemwb_attach(dev) 820191783Srmacklem device_t dev; 821191783Srmacklem{ 822191783Srmacklem u_char eaddr[ETHER_ADDR_LEN]; 823191783Srmacklem struct wb_softc *sc; 824191783Srmacklem struct ifnet *ifp; 825191783Srmacklem int unit, error = 0, rid; 826191783Srmacklem 827191783Srmacklem sc = device_get_softc(dev); 828191783Srmacklem unit = device_get_unit(dev); 829191783Srmacklem 830191783Srmacklem mtx_init(&sc->wb_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 831191783Srmacklem MTX_DEF | MTX_RECURSE); 832191783Srmacklem 833191783Srmacklem /* 834191783Srmacklem * Handle power management nonsense. 835191783Srmacklem */ 836191783Srmacklem 837191783Srmacklem if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 838191783Srmacklem u_int32_t iobase, membase, irq; 839191783Srmacklem 840191783Srmacklem /* Save important PCI config data. */ 841191783Srmacklem iobase = pci_read_config(dev, WB_PCI_LOIO, 4); 842191783Srmacklem membase = pci_read_config(dev, WB_PCI_LOMEM, 4); 843191783Srmacklem irq = pci_read_config(dev, WB_PCI_INTLINE, 4); 844191783Srmacklem 845191783Srmacklem /* Reset the power state. */ 846191783Srmacklem printf("wb%d: chip is in D%d power mode " 847191783Srmacklem "-- setting to D0\n", unit, 848191783Srmacklem pci_get_powerstate(dev)); 849191783Srmacklem pci_set_powerstate(dev, PCI_POWERSTATE_D0); 850191783Srmacklem 851191783Srmacklem /* Restore PCI config data. */ 852191783Srmacklem pci_write_config(dev, WB_PCI_LOIO, iobase, 4); 853191783Srmacklem pci_write_config(dev, WB_PCI_LOMEM, membase, 4); 854191783Srmacklem pci_write_config(dev, WB_PCI_INTLINE, irq, 4); 855191783Srmacklem } 856191783Srmacklem 857191783Srmacklem /* 858191783Srmacklem * Map control/status registers. 859191783Srmacklem */ 860191783Srmacklem pci_enable_busmaster(dev); 861191783Srmacklem 862191783Srmacklem rid = WB_RID; 863191783Srmacklem sc->wb_res = bus_alloc_resource(dev, WB_RES, &rid, 864191783Srmacklem 0, ~0, 1, RF_ACTIVE); 865191783Srmacklem 866191783Srmacklem if (sc->wb_res == NULL) { 867191783Srmacklem printf("wb%d: couldn't map ports/memory\n", unit); 868191783Srmacklem error = ENXIO; 869191783Srmacklem goto fail; 870191783Srmacklem } 871191783Srmacklem 872191783Srmacklem sc->wb_btag = rman_get_bustag(sc->wb_res); 873191783Srmacklem sc->wb_bhandle = rman_get_bushandle(sc->wb_res); 874191783Srmacklem 875191783Srmacklem /* Allocate interrupt */ 876191783Srmacklem rid = 0; 877191783Srmacklem sc->wb_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 878191783Srmacklem RF_SHAREABLE | RF_ACTIVE); 879191783Srmacklem 880191783Srmacklem if (sc->wb_irq == NULL) { 881191783Srmacklem printf("wb%d: couldn't map interrupt\n", unit); 882191783Srmacklem error = ENXIO; 883191783Srmacklem goto fail; 884191783Srmacklem } 885191783Srmacklem 886191783Srmacklem /* Save the cache line size. */ 887191783Srmacklem sc->wb_cachesize = pci_read_config(dev, WB_PCI_CACHELEN, 4) & 0xFF; 888191783Srmacklem 889191783Srmacklem /* Reset the adapter. */ 890191783Srmacklem wb_reset(sc); 891191783Srmacklem 892191783Srmacklem /* 893191783Srmacklem * Get station address from the EEPROM. 894191783Srmacklem */ 895191783Srmacklem wb_read_eeprom(sc, (caddr_t)&eaddr, 0, 3, 0); 896191783Srmacklem 897191783Srmacklem /* 898191783Srmacklem * A Winbond chip was detected. Inform the world. 899191783Srmacklem */ 900191783Srmacklem printf("wb%d: Ethernet address: %6D\n", unit, eaddr, ":"); 901191783Srmacklem 902191783Srmacklem sc->wb_unit = unit; 903191783Srmacklem bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 904191783Srmacklem 905191783Srmacklem sc->wb_ldata = contigmalloc(sizeof(struct wb_list_data) + 8, M_DEVBUF, 906191783Srmacklem M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 907191783Srmacklem 908191783Srmacklem if (sc->wb_ldata == NULL) { 909191783Srmacklem printf("wb%d: no memory for list buffers!\n", unit); 910191783Srmacklem error = ENXIO; 911191783Srmacklem goto fail; 912191783Srmacklem } 913 914 bzero(sc->wb_ldata, sizeof(struct wb_list_data)); 915 916 ifp = &sc->arpcom.ac_if; 917 ifp->if_softc = sc; 918 ifp->if_unit = unit; 919 ifp->if_name = "wb"; 920 ifp->if_mtu = ETHERMTU; 921 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 922 ifp->if_ioctl = wb_ioctl; 923 ifp->if_output = ether_output; 924 ifp->if_start = wb_start; 925 ifp->if_watchdog = wb_watchdog; 926 ifp->if_init = wb_init; 927 ifp->if_baudrate = 10000000; 928 ifp->if_snd.ifq_maxlen = WB_TX_LIST_CNT - 1; 929 930 /* 931 * Do MII setup. 932 */ 933 if (mii_phy_probe(dev, &sc->wb_miibus, 934 wb_ifmedia_upd, wb_ifmedia_sts)) { 935 error = ENXIO; 936 goto fail; 937 } 938 939 /* 940 * Call MI attach routine. 941 */ 942 ether_ifattach(ifp, eaddr); 943 944 /* Hook interrupt last to avoid having to lock softc */ 945 error = bus_setup_intr(dev, sc->wb_irq, INTR_TYPE_NET, 946 wb_intr, sc, &sc->wb_intrhand); 947 948 if (error) { 949 printf("wb%d: couldn't set up irq\n", unit); 950 ether_ifdetach(ifp); 951 goto fail; 952 } 953 954fail: 955 if (error) 956 wb_detach(dev); 957 958 return(error); 959} 960 961/* 962 * Shutdown hardware and free up resources. This can be called any 963 * time after the mutex has been initialized. It is called in both 964 * the error case in attach and the normal detach case so it needs 965 * to be careful about only freeing resources that have actually been 966 * allocated. 967 */ 968static int 969wb_detach(dev) 970 device_t dev; 971{ 972 struct wb_softc *sc; 973 struct ifnet *ifp; 974 975 sc = device_get_softc(dev); 976 KASSERT(mtx_initialized(&sc->wb_mtx), ("wb mutex not initialized")); 977 WB_LOCK(sc); 978 ifp = &sc->arpcom.ac_if; 979 980 /* 981 * Delete any miibus and phy devices attached to this interface. 982 * This should only be done if attach succeeded. 983 */ 984 if (device_is_alive(dev)) { 985 wb_stop(sc); 986 ether_ifdetach(ifp); 987 } 988 if (sc->wb_miibus) 989 device_delete_child(dev, sc->wb_miibus); 990 bus_generic_detach(dev); 991 992 if (sc->wb_intrhand) 993 bus_teardown_intr(dev, sc->wb_irq, sc->wb_intrhand); 994 if (sc->wb_irq) 995 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->wb_irq); 996 if (sc->wb_res) 997 bus_release_resource(dev, WB_RES, WB_RID, sc->wb_res); 998 999 if (sc->wb_ldata) { 1000 contigfree(sc->wb_ldata, sizeof(struct wb_list_data) + 8, 1001 M_DEVBUF); 1002 } 1003 1004 WB_UNLOCK(sc); 1005 mtx_destroy(&sc->wb_mtx); 1006 1007 return(0); 1008} 1009 1010/* 1011 * Initialize the transmit descriptors. 1012 */ 1013static int 1014wb_list_tx_init(sc) 1015 struct wb_softc *sc; 1016{ 1017 struct wb_chain_data *cd; 1018 struct wb_list_data *ld; 1019 int i; 1020 1021 cd = &sc->wb_cdata; 1022 ld = sc->wb_ldata; 1023 1024 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1025 cd->wb_tx_chain[i].wb_ptr = &ld->wb_tx_list[i]; 1026 if (i == (WB_TX_LIST_CNT - 1)) { 1027 cd->wb_tx_chain[i].wb_nextdesc = 1028 &cd->wb_tx_chain[0]; 1029 } else { 1030 cd->wb_tx_chain[i].wb_nextdesc = 1031 &cd->wb_tx_chain[i + 1]; 1032 } 1033 } 1034 1035 cd->wb_tx_free = &cd->wb_tx_chain[0]; 1036 cd->wb_tx_tail = cd->wb_tx_head = NULL; 1037 1038 return(0); 1039} 1040 1041 1042/* 1043 * Initialize the RX descriptors and allocate mbufs for them. Note that 1044 * we arrange the descriptors in a closed ring, so that the last descriptor 1045 * points back to the first. 1046 */ 1047static int 1048wb_list_rx_init(sc) 1049 struct wb_softc *sc; 1050{ 1051 struct wb_chain_data *cd; 1052 struct wb_list_data *ld; 1053 int i; 1054 1055 cd = &sc->wb_cdata; 1056 ld = sc->wb_ldata; 1057 1058 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1059 cd->wb_rx_chain[i].wb_ptr = 1060 (struct wb_desc *)&ld->wb_rx_list[i]; 1061 cd->wb_rx_chain[i].wb_buf = (void *)&ld->wb_rxbufs[i]; 1062 if (wb_newbuf(sc, &cd->wb_rx_chain[i], NULL) == ENOBUFS) 1063 return(ENOBUFS); 1064 if (i == (WB_RX_LIST_CNT - 1)) { 1065 cd->wb_rx_chain[i].wb_nextdesc = &cd->wb_rx_chain[0]; 1066 ld->wb_rx_list[i].wb_next = 1067 vtophys(&ld->wb_rx_list[0]); 1068 } else { 1069 cd->wb_rx_chain[i].wb_nextdesc = 1070 &cd->wb_rx_chain[i + 1]; 1071 ld->wb_rx_list[i].wb_next = 1072 vtophys(&ld->wb_rx_list[i + 1]); 1073 } 1074 } 1075 1076 cd->wb_rx_head = &cd->wb_rx_chain[0]; 1077 1078 return(0); 1079} 1080 1081static void 1082wb_bfree(buf, args) 1083 void *buf; 1084 void *args; 1085{ 1086 return; 1087} 1088 1089/* 1090 * Initialize an RX descriptor and attach an MBUF cluster. 1091 */ 1092static int 1093wb_newbuf(sc, c, m) 1094 struct wb_softc *sc; 1095 struct wb_chain_onefrag *c; 1096 struct mbuf *m; 1097{ 1098 struct mbuf *m_new = NULL; 1099 1100 if (m == NULL) { 1101 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1102 if (m_new == NULL) 1103 return(ENOBUFS); 1104 m_new->m_data = c->wb_buf; 1105 m_new->m_pkthdr.len = m_new->m_len = WB_BUFBYTES; 1106 MEXTADD(m_new, c->wb_buf, WB_BUFBYTES, wb_bfree, NULL, 0, 1107 EXT_NET_DRV); 1108 } else { 1109 m_new = m; 1110 m_new->m_len = m_new->m_pkthdr.len = WB_BUFBYTES; 1111 m_new->m_data = m_new->m_ext.ext_buf; 1112 } 1113 1114 m_adj(m_new, sizeof(u_int64_t)); 1115 1116 c->wb_mbuf = m_new; 1117 c->wb_ptr->wb_data = vtophys(mtod(m_new, caddr_t)); 1118 c->wb_ptr->wb_ctl = WB_RXCTL_RLINK | 1536; 1119 c->wb_ptr->wb_status = WB_RXSTAT; 1120 1121 return(0); 1122} 1123 1124/* 1125 * A frame has been uploaded: pass the resulting mbuf chain up to 1126 * the higher level protocols. 1127 */ 1128static void 1129wb_rxeof(sc) 1130 struct wb_softc *sc; 1131{ 1132 struct mbuf *m = NULL; 1133 struct ifnet *ifp; 1134 struct wb_chain_onefrag *cur_rx; 1135 int total_len = 0; 1136 u_int32_t rxstat; 1137 1138 ifp = &sc->arpcom.ac_if; 1139 1140 while(!((rxstat = sc->wb_cdata.wb_rx_head->wb_ptr->wb_status) & 1141 WB_RXSTAT_OWN)) { 1142 struct mbuf *m0 = NULL; 1143 1144 cur_rx = sc->wb_cdata.wb_rx_head; 1145 sc->wb_cdata.wb_rx_head = cur_rx->wb_nextdesc; 1146 1147 m = cur_rx->wb_mbuf; 1148 1149 if ((rxstat & WB_RXSTAT_MIIERR) || 1150 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) < WB_MIN_FRAMELEN) || 1151 (WB_RXBYTES(cur_rx->wb_ptr->wb_status) > 1536) || 1152 !(rxstat & WB_RXSTAT_LASTFRAG) || 1153 !(rxstat & WB_RXSTAT_RXCMP)) { 1154 ifp->if_ierrors++; 1155 wb_newbuf(sc, cur_rx, m); 1156 printf("wb%x: receiver babbling: possible chip " 1157 "bug, forcing reset\n", sc->wb_unit); 1158 wb_fixmedia(sc); 1159 wb_reset(sc); 1160 wb_init(sc); 1161 return; 1162 } 1163 1164 if (rxstat & WB_RXSTAT_RXERR) { 1165 ifp->if_ierrors++; 1166 wb_newbuf(sc, cur_rx, m); 1167 break; 1168 } 1169 1170 /* No errors; receive the packet. */ 1171 total_len = WB_RXBYTES(cur_rx->wb_ptr->wb_status); 1172 1173 /* 1174 * XXX The Winbond chip includes the CRC with every 1175 * received frame, and there's no way to turn this 1176 * behavior off (at least, I can't find anything in 1177 * the manual that explains how to do it) so we have 1178 * to trim off the CRC manually. 1179 */ 1180 total_len -= ETHER_CRC_LEN; 1181 1182 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, ifp, 1183 NULL); 1184 wb_newbuf(sc, cur_rx, m); 1185 if (m0 == NULL) { 1186 ifp->if_ierrors++; 1187 break; 1188 } 1189 m = m0; 1190 1191 ifp->if_ipackets++; 1192 (*ifp->if_input)(ifp, m); 1193 } 1194} 1195 1196static void 1197wb_rxeoc(sc) 1198 struct wb_softc *sc; 1199{ 1200 wb_rxeof(sc); 1201 1202 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1203 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1204 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1205 if (CSR_READ_4(sc, WB_ISR) & WB_RXSTATE_SUSPEND) 1206 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1207 1208 return; 1209} 1210 1211/* 1212 * A frame was downloaded to the chip. It's safe for us to clean up 1213 * the list buffers. 1214 */ 1215static void 1216wb_txeof(sc) 1217 struct wb_softc *sc; 1218{ 1219 struct wb_chain *cur_tx; 1220 struct ifnet *ifp; 1221 1222 ifp = &sc->arpcom.ac_if; 1223 1224 /* Clear the timeout timer. */ 1225 ifp->if_timer = 0; 1226 1227 if (sc->wb_cdata.wb_tx_head == NULL) 1228 return; 1229 1230 /* 1231 * Go through our tx list and free mbufs for those 1232 * frames that have been transmitted. 1233 */ 1234 while(sc->wb_cdata.wb_tx_head->wb_mbuf != NULL) { 1235 u_int32_t txstat; 1236 1237 cur_tx = sc->wb_cdata.wb_tx_head; 1238 txstat = WB_TXSTATUS(cur_tx); 1239 1240 if ((txstat & WB_TXSTAT_OWN) || txstat == WB_UNSENT) 1241 break; 1242 1243 if (txstat & WB_TXSTAT_TXERR) { 1244 ifp->if_oerrors++; 1245 if (txstat & WB_TXSTAT_ABORT) 1246 ifp->if_collisions++; 1247 if (txstat & WB_TXSTAT_LATECOLL) 1248 ifp->if_collisions++; 1249 } 1250 1251 ifp->if_collisions += (txstat & WB_TXSTAT_COLLCNT) >> 3; 1252 1253 ifp->if_opackets++; 1254 m_freem(cur_tx->wb_mbuf); 1255 cur_tx->wb_mbuf = NULL; 1256 1257 if (sc->wb_cdata.wb_tx_head == sc->wb_cdata.wb_tx_tail) { 1258 sc->wb_cdata.wb_tx_head = NULL; 1259 sc->wb_cdata.wb_tx_tail = NULL; 1260 break; 1261 } 1262 1263 sc->wb_cdata.wb_tx_head = cur_tx->wb_nextdesc; 1264 } 1265 1266 return; 1267} 1268 1269/* 1270 * TX 'end of channel' interrupt handler. 1271 */ 1272static void 1273wb_txeoc(sc) 1274 struct wb_softc *sc; 1275{ 1276 struct ifnet *ifp; 1277 1278 ifp = &sc->arpcom.ac_if; 1279 1280 ifp->if_timer = 0; 1281 1282 if (sc->wb_cdata.wb_tx_head == NULL) { 1283 ifp->if_flags &= ~IFF_OACTIVE; 1284 sc->wb_cdata.wb_tx_tail = NULL; 1285 } else { 1286 if (WB_TXOWN(sc->wb_cdata.wb_tx_head) == WB_UNSENT) { 1287 WB_TXOWN(sc->wb_cdata.wb_tx_head) = WB_TXSTAT_OWN; 1288 ifp->if_timer = 5; 1289 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1290 } 1291 } 1292 1293 return; 1294} 1295 1296static void 1297wb_intr(arg) 1298 void *arg; 1299{ 1300 struct wb_softc *sc; 1301 struct ifnet *ifp; 1302 u_int32_t status; 1303 1304 sc = arg; 1305 WB_LOCK(sc); 1306 ifp = &sc->arpcom.ac_if; 1307 1308 if (!(ifp->if_flags & IFF_UP)) { 1309 WB_UNLOCK(sc); 1310 return; 1311 } 1312 1313 /* Disable interrupts. */ 1314 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1315 1316 for (;;) { 1317 1318 status = CSR_READ_4(sc, WB_ISR); 1319 if (status) 1320 CSR_WRITE_4(sc, WB_ISR, status); 1321 1322 if ((status & WB_INTRS) == 0) 1323 break; 1324 1325 if ((status & WB_ISR_RX_NOBUF) || (status & WB_ISR_RX_ERR)) { 1326 ifp->if_ierrors++; 1327 wb_reset(sc); 1328 if (status & WB_ISR_RX_ERR) 1329 wb_fixmedia(sc); 1330 wb_init(sc); 1331 continue; 1332 } 1333 1334 if (status & WB_ISR_RX_OK) 1335 wb_rxeof(sc); 1336 1337 if (status & WB_ISR_RX_IDLE) 1338 wb_rxeoc(sc); 1339 1340 if (status & WB_ISR_TX_OK) 1341 wb_txeof(sc); 1342 1343 if (status & WB_ISR_TX_NOBUF) 1344 wb_txeoc(sc); 1345 1346 if (status & WB_ISR_TX_IDLE) { 1347 wb_txeof(sc); 1348 if (sc->wb_cdata.wb_tx_head != NULL) { 1349 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1350 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1351 } 1352 } 1353 1354 if (status & WB_ISR_TX_UNDERRUN) { 1355 ifp->if_oerrors++; 1356 wb_txeof(sc); 1357 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1358 /* Jack up TX threshold */ 1359 sc->wb_txthresh += WB_TXTHRESH_CHUNK; 1360 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1361 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1362 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1363 } 1364 1365 if (status & WB_ISR_BUS_ERR) { 1366 wb_reset(sc); 1367 wb_init(sc); 1368 } 1369 1370 } 1371 1372 /* Re-enable interrupts. */ 1373 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1374 1375 if (ifp->if_snd.ifq_head != NULL) { 1376 wb_start(ifp); 1377 } 1378 1379 WB_UNLOCK(sc); 1380 1381 return; 1382} 1383 1384static void 1385wb_tick(xsc) 1386 void *xsc; 1387{ 1388 struct wb_softc *sc; 1389 struct mii_data *mii; 1390 1391 sc = xsc; 1392 WB_LOCK(sc); 1393 mii = device_get_softc(sc->wb_miibus); 1394 1395 mii_tick(mii); 1396 1397 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1398 1399 WB_UNLOCK(sc); 1400 1401 return; 1402} 1403 1404/* 1405 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1406 * pointers to the fragment pointers. 1407 */ 1408static int 1409wb_encap(sc, c, m_head) 1410 struct wb_softc *sc; 1411 struct wb_chain *c; 1412 struct mbuf *m_head; 1413{ 1414 int frag = 0; 1415 struct wb_desc *f = NULL; 1416 int total_len; 1417 struct mbuf *m; 1418 1419 /* 1420 * Start packing the mbufs in this chain into 1421 * the fragment pointers. Stop when we run out 1422 * of fragments or hit the end of the mbuf chain. 1423 */ 1424 m = m_head; 1425 total_len = 0; 1426 1427 for (m = m_head, frag = 0; m != NULL; m = m->m_next) { 1428 if (m->m_len != 0) { 1429 if (frag == WB_MAXFRAGS) 1430 break; 1431 total_len += m->m_len; 1432 f = &c->wb_ptr->wb_frag[frag]; 1433 f->wb_ctl = WB_TXCTL_TLINK | m->m_len; 1434 if (frag == 0) { 1435 f->wb_ctl |= WB_TXCTL_FIRSTFRAG; 1436 f->wb_status = 0; 1437 } else 1438 f->wb_status = WB_TXSTAT_OWN; 1439 f->wb_next = vtophys(&c->wb_ptr->wb_frag[frag + 1]); 1440 f->wb_data = vtophys(mtod(m, vm_offset_t)); 1441 frag++; 1442 } 1443 } 1444 1445 /* 1446 * Handle special case: we used up all 16 fragments, 1447 * but we have more mbufs left in the chain. Copy the 1448 * data into an mbuf cluster. Note that we don't 1449 * bother clearing the values in the other fragment 1450 * pointers/counters; it wouldn't gain us anything, 1451 * and would waste cycles. 1452 */ 1453 if (m != NULL) { 1454 struct mbuf *m_new = NULL; 1455 1456 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1457 if (m_new == NULL) 1458 return(1); 1459 if (m_head->m_pkthdr.len > MHLEN) { 1460 MCLGET(m_new, M_DONTWAIT); 1461 if (!(m_new->m_flags & M_EXT)) { 1462 m_freem(m_new); 1463 return(1); 1464 } 1465 } 1466 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1467 mtod(m_new, caddr_t)); 1468 m_new->m_pkthdr.len = m_new->m_len = m_head->m_pkthdr.len; 1469 m_freem(m_head); 1470 m_head = m_new; 1471 f = &c->wb_ptr->wb_frag[0]; 1472 f->wb_status = 0; 1473 f->wb_data = vtophys(mtod(m_new, caddr_t)); 1474 f->wb_ctl = total_len = m_new->m_len; 1475 f->wb_ctl |= WB_TXCTL_TLINK|WB_TXCTL_FIRSTFRAG; 1476 frag = 1; 1477 } 1478 1479 if (total_len < WB_MIN_FRAMELEN) { 1480 f = &c->wb_ptr->wb_frag[frag]; 1481 f->wb_ctl = WB_MIN_FRAMELEN - total_len; 1482 f->wb_data = vtophys(&sc->wb_cdata.wb_pad); 1483 f->wb_ctl |= WB_TXCTL_TLINK; 1484 f->wb_status = WB_TXSTAT_OWN; 1485 frag++; 1486 } 1487 1488 c->wb_mbuf = m_head; 1489 c->wb_lastdesc = frag - 1; 1490 WB_TXCTL(c) |= WB_TXCTL_LASTFRAG; 1491 WB_TXNEXT(c) = vtophys(&c->wb_nextdesc->wb_ptr->wb_frag[0]); 1492 1493 return(0); 1494} 1495 1496/* 1497 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1498 * to the mbuf data regions directly in the transmit lists. We also save a 1499 * copy of the pointers since the transmit list fragment pointers are 1500 * physical addresses. 1501 */ 1502 1503static void 1504wb_start(ifp) 1505 struct ifnet *ifp; 1506{ 1507 struct wb_softc *sc; 1508 struct mbuf *m_head = NULL; 1509 struct wb_chain *cur_tx = NULL, *start_tx; 1510 1511 sc = ifp->if_softc; 1512 WB_LOCK(sc); 1513 1514 /* 1515 * Check for an available queue slot. If there are none, 1516 * punt. 1517 */ 1518 if (sc->wb_cdata.wb_tx_free->wb_mbuf != NULL) { 1519 ifp->if_flags |= IFF_OACTIVE; 1520 WB_UNLOCK(sc); 1521 return; 1522 } 1523 1524 start_tx = sc->wb_cdata.wb_tx_free; 1525 1526 while(sc->wb_cdata.wb_tx_free->wb_mbuf == NULL) { 1527 IF_DEQUEUE(&ifp->if_snd, m_head); 1528 if (m_head == NULL) 1529 break; 1530 1531 /* Pick a descriptor off the free list. */ 1532 cur_tx = sc->wb_cdata.wb_tx_free; 1533 sc->wb_cdata.wb_tx_free = cur_tx->wb_nextdesc; 1534 1535 /* Pack the data into the descriptor. */ 1536 wb_encap(sc, cur_tx, m_head); 1537 1538 if (cur_tx != start_tx) 1539 WB_TXOWN(cur_tx) = WB_TXSTAT_OWN; 1540 1541 /* 1542 * If there's a BPF listener, bounce a copy of this frame 1543 * to him. 1544 */ 1545 BPF_MTAP(ifp, cur_tx->wb_mbuf); 1546 } 1547 1548 /* 1549 * If there are no packets queued, bail. 1550 */ 1551 if (cur_tx == NULL) { 1552 WB_UNLOCK(sc); 1553 return; 1554 } 1555 1556 /* 1557 * Place the request for the upload interrupt 1558 * in the last descriptor in the chain. This way, if 1559 * we're chaining several packets at once, we'll only 1560 * get an interupt once for the whole chain rather than 1561 * once for each packet. 1562 */ 1563 WB_TXCTL(cur_tx) |= WB_TXCTL_FINT; 1564 cur_tx->wb_ptr->wb_frag[0].wb_ctl |= WB_TXCTL_FINT; 1565 sc->wb_cdata.wb_tx_tail = cur_tx; 1566 1567 if (sc->wb_cdata.wb_tx_head == NULL) { 1568 sc->wb_cdata.wb_tx_head = start_tx; 1569 WB_TXOWN(start_tx) = WB_TXSTAT_OWN; 1570 CSR_WRITE_4(sc, WB_TXSTART, 0xFFFFFFFF); 1571 } else { 1572 /* 1573 * We need to distinguish between the case where 1574 * the own bit is clear because the chip cleared it 1575 * and where the own bit is clear because we haven't 1576 * set it yet. The magic value WB_UNSET is just some 1577 * ramdomly chosen number which doesn't have the own 1578 * bit set. When we actually transmit the frame, the 1579 * status word will have _only_ the own bit set, so 1580 * the txeoc handler will be able to tell if it needs 1581 * to initiate another transmission to flush out pending 1582 * frames. 1583 */ 1584 WB_TXOWN(start_tx) = WB_UNSENT; 1585 } 1586 1587 /* 1588 * Set a timeout in case the chip goes out to lunch. 1589 */ 1590 ifp->if_timer = 5; 1591 WB_UNLOCK(sc); 1592 1593 return; 1594} 1595 1596static void 1597wb_init(xsc) 1598 void *xsc; 1599{ 1600 struct wb_softc *sc = xsc; 1601 struct ifnet *ifp = &sc->arpcom.ac_if; 1602 int i; 1603 struct mii_data *mii; 1604 1605 WB_LOCK(sc); 1606 mii = device_get_softc(sc->wb_miibus); 1607 1608 /* 1609 * Cancel pending I/O and free all RX/TX buffers. 1610 */ 1611 wb_stop(sc); 1612 wb_reset(sc); 1613 1614 sc->wb_txthresh = WB_TXTHRESH_INIT; 1615 1616 /* 1617 * Set cache alignment and burst length. 1618 */ 1619#ifdef foo 1620 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_CONFIG); 1621 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_THRESH); 1622 WB_SETBIT(sc, WB_NETCFG, WB_TXTHRESH(sc->wb_txthresh)); 1623#endif 1624 1625 CSR_WRITE_4(sc, WB_BUSCTL, WB_BUSCTL_MUSTBEONE|WB_BUSCTL_ARBITRATION); 1626 WB_SETBIT(sc, WB_BUSCTL, WB_BURSTLEN_16LONG); 1627 switch(sc->wb_cachesize) { 1628 case 32: 1629 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_32LONG); 1630 break; 1631 case 16: 1632 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_16LONG); 1633 break; 1634 case 8: 1635 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_8LONG); 1636 break; 1637 case 0: 1638 default: 1639 WB_SETBIT(sc, WB_BUSCTL, WB_CACHEALIGN_NONE); 1640 break; 1641 } 1642 1643 /* This doesn't tend to work too well at 100Mbps. */ 1644 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_EARLY_ON); 1645 1646 /* Init our MAC address */ 1647 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1648 CSR_WRITE_1(sc, WB_NODE0 + i, sc->arpcom.ac_enaddr[i]); 1649 } 1650 1651 /* Init circular RX list. */ 1652 if (wb_list_rx_init(sc) == ENOBUFS) { 1653 printf("wb%d: initialization failed: no " 1654 "memory for rx buffers\n", sc->wb_unit); 1655 wb_stop(sc); 1656 WB_UNLOCK(sc); 1657 return; 1658 } 1659 1660 /* Init TX descriptors. */ 1661 wb_list_tx_init(sc); 1662 1663 /* If we want promiscuous mode, set the allframes bit. */ 1664 if (ifp->if_flags & IFF_PROMISC) { 1665 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1666 } else { 1667 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ALLPHYS); 1668 } 1669 1670 /* 1671 * Set capture broadcast bit to capture broadcast frames. 1672 */ 1673 if (ifp->if_flags & IFF_BROADCAST) { 1674 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1675 } else { 1676 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_BROAD); 1677 } 1678 1679 /* 1680 * Program the multicast filter, if necessary. 1681 */ 1682 wb_setmulti(sc); 1683 1684 /* 1685 * Load the address of the RX list. 1686 */ 1687 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1688 CSR_WRITE_4(sc, WB_RXADDR, vtophys(&sc->wb_ldata->wb_rx_list[0])); 1689 1690 /* 1691 * Enable interrupts. 1692 */ 1693 CSR_WRITE_4(sc, WB_IMR, WB_INTRS); 1694 CSR_WRITE_4(sc, WB_ISR, 0xFFFFFFFF); 1695 1696 /* Enable receiver and transmitter. */ 1697 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_RX_ON); 1698 CSR_WRITE_4(sc, WB_RXSTART, 0xFFFFFFFF); 1699 1700 WB_CLRBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1701 CSR_WRITE_4(sc, WB_TXADDR, vtophys(&sc->wb_ldata->wb_tx_list[0])); 1702 WB_SETBIT(sc, WB_NETCFG, WB_NETCFG_TX_ON); 1703 1704 mii_mediachg(mii); 1705 1706 ifp->if_flags |= IFF_RUNNING; 1707 ifp->if_flags &= ~IFF_OACTIVE; 1708 1709 sc->wb_stat_ch = timeout(wb_tick, sc, hz); 1710 WB_UNLOCK(sc); 1711 1712 return; 1713} 1714 1715/* 1716 * Set media options. 1717 */ 1718static int 1719wb_ifmedia_upd(ifp) 1720 struct ifnet *ifp; 1721{ 1722 struct wb_softc *sc; 1723 1724 sc = ifp->if_softc; 1725 1726 if (ifp->if_flags & IFF_UP) 1727 wb_init(sc); 1728 1729 return(0); 1730} 1731 1732/* 1733 * Report current media status. 1734 */ 1735static void 1736wb_ifmedia_sts(ifp, ifmr) 1737 struct ifnet *ifp; 1738 struct ifmediareq *ifmr; 1739{ 1740 struct wb_softc *sc; 1741 struct mii_data *mii; 1742 1743 sc = ifp->if_softc; 1744 1745 mii = device_get_softc(sc->wb_miibus); 1746 1747 mii_pollstat(mii); 1748 ifmr->ifm_active = mii->mii_media_active; 1749 ifmr->ifm_status = mii->mii_media_status; 1750 1751 return; 1752} 1753 1754static int 1755wb_ioctl(ifp, command, data) 1756 struct ifnet *ifp; 1757 u_long command; 1758 caddr_t data; 1759{ 1760 struct wb_softc *sc = ifp->if_softc; 1761 struct mii_data *mii; 1762 struct ifreq *ifr = (struct ifreq *) data; 1763 int error = 0; 1764 1765 WB_LOCK(sc); 1766 1767 switch(command) { 1768 case SIOCSIFFLAGS: 1769 if (ifp->if_flags & IFF_UP) { 1770 wb_init(sc); 1771 } else { 1772 if (ifp->if_flags & IFF_RUNNING) 1773 wb_stop(sc); 1774 } 1775 error = 0; 1776 break; 1777 case SIOCADDMULTI: 1778 case SIOCDELMULTI: 1779 wb_setmulti(sc); 1780 error = 0; 1781 break; 1782 case SIOCGIFMEDIA: 1783 case SIOCSIFMEDIA: 1784 mii = device_get_softc(sc->wb_miibus); 1785 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1786 break; 1787 default: 1788 error = ether_ioctl(ifp, command, data); 1789 break; 1790 } 1791 1792 WB_UNLOCK(sc); 1793 1794 return(error); 1795} 1796 1797static void 1798wb_watchdog(ifp) 1799 struct ifnet *ifp; 1800{ 1801 struct wb_softc *sc; 1802 1803 sc = ifp->if_softc; 1804 1805 WB_LOCK(sc); 1806 ifp->if_oerrors++; 1807 printf("wb%d: watchdog timeout\n", sc->wb_unit); 1808#ifdef foo 1809 if (!(wb_phy_readreg(sc, PHY_BMSR) & PHY_BMSR_LINKSTAT)) 1810 printf("wb%d: no carrier - transceiver cable problem?\n", 1811 sc->wb_unit); 1812#endif 1813 wb_stop(sc); 1814 wb_reset(sc); 1815 wb_init(sc); 1816 1817 if (ifp->if_snd.ifq_head != NULL) 1818 wb_start(ifp); 1819 WB_UNLOCK(sc); 1820 1821 return; 1822} 1823 1824/* 1825 * Stop the adapter and free any mbufs allocated to the 1826 * RX and TX lists. 1827 */ 1828static void 1829wb_stop(sc) 1830 struct wb_softc *sc; 1831{ 1832 register int i; 1833 struct ifnet *ifp; 1834 1835 WB_LOCK(sc); 1836 ifp = &sc->arpcom.ac_if; 1837 ifp->if_timer = 0; 1838 1839 untimeout(wb_tick, sc, sc->wb_stat_ch); 1840 1841 WB_CLRBIT(sc, WB_NETCFG, (WB_NETCFG_RX_ON|WB_NETCFG_TX_ON)); 1842 CSR_WRITE_4(sc, WB_IMR, 0x00000000); 1843 CSR_WRITE_4(sc, WB_TXADDR, 0x00000000); 1844 CSR_WRITE_4(sc, WB_RXADDR, 0x00000000); 1845 1846 /* 1847 * Free data in the RX lists. 1848 */ 1849 for (i = 0; i < WB_RX_LIST_CNT; i++) { 1850 if (sc->wb_cdata.wb_rx_chain[i].wb_mbuf != NULL) { 1851 m_freem(sc->wb_cdata.wb_rx_chain[i].wb_mbuf); 1852 sc->wb_cdata.wb_rx_chain[i].wb_mbuf = NULL; 1853 } 1854 } 1855 bzero((char *)&sc->wb_ldata->wb_rx_list, 1856 sizeof(sc->wb_ldata->wb_rx_list)); 1857 1858 /* 1859 * Free the TX list buffers. 1860 */ 1861 for (i = 0; i < WB_TX_LIST_CNT; i++) { 1862 if (sc->wb_cdata.wb_tx_chain[i].wb_mbuf != NULL) { 1863 m_freem(sc->wb_cdata.wb_tx_chain[i].wb_mbuf); 1864 sc->wb_cdata.wb_tx_chain[i].wb_mbuf = NULL; 1865 } 1866 } 1867 1868 bzero((char *)&sc->wb_ldata->wb_tx_list, 1869 sizeof(sc->wb_ldata->wb_tx_list)); 1870 1871 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1872 WB_UNLOCK(sc); 1873 1874 return; 1875} 1876 1877/* 1878 * Stop all chip I/O so that the kernel's probe routines don't 1879 * get confused by errant DMAs when rebooting. 1880 */ 1881static void 1882wb_shutdown(dev) 1883 device_t dev; 1884{ 1885 struct wb_softc *sc; 1886 1887 sc = device_get_softc(dev); 1888 wb_stop(sc); 1889 1890 return; 1891} 1892