if_vge.c revision 200545
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 200545 2009-12-14 21:16:02Z yongari $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102#include <net/if_types.h> 103#include <net/if_vlan_var.h> 104 105#include <net/bpf.h> 106 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/mii/mii.h> 113#include <dev/mii/miivar.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117 118MODULE_DEPEND(vge, pci, 1, 1, 1); 119MODULE_DEPEND(vge, ether, 1, 1, 1); 120MODULE_DEPEND(vge, miibus, 1, 1, 1); 121 122/* "device miibus" required. See GENERIC if you get errors here. */ 123#include "miibus_if.h" 124 125#include <dev/vge/if_vgereg.h> 126#include <dev/vge/if_vgevar.h> 127 128#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 129 130/* Tunables */ 131static int msi_disable = 0; 132TUNABLE_INT("hw.vge.msi_disable", &msi_disable); 133 134/* 135 * Various supported device vendors/types and their names. 136 */ 137static struct vge_type vge_devs[] = { 138 { VIA_VENDORID, VIA_DEVICEID_61XX, 139 "VIA Networking Gigabit Ethernet" }, 140 { 0, 0, NULL } 141}; 142 143static int vge_probe (device_t); 144static int vge_attach (device_t); 145static int vge_detach (device_t); 146 147static int vge_encap (struct vge_softc *, struct mbuf **); 148 149static void vge_dmamap_cb (void *, bus_dma_segment_t *, int, int); 150static int vge_dma_alloc (struct vge_softc *); 151static void vge_dma_free (struct vge_softc *); 152static void vge_discard_rxbuf (struct vge_softc *, int); 153static int vge_newbuf (struct vge_softc *, int); 154static int vge_rx_list_init (struct vge_softc *); 155static int vge_tx_list_init (struct vge_softc *); 156static void vge_freebufs (struct vge_softc *); 157#ifndef __NO_STRICT_ALIGNMENT 158static __inline void vge_fixup_rx 159 (struct mbuf *); 160#endif 161static int vge_rxeof (struct vge_softc *, int); 162static void vge_txeof (struct vge_softc *); 163static void vge_intr (void *); 164static void vge_tick (void *); 165static void vge_start (struct ifnet *); 166static void vge_start_locked (struct ifnet *); 167static int vge_ioctl (struct ifnet *, u_long, caddr_t); 168static void vge_init (void *); 169static void vge_init_locked (struct vge_softc *); 170static void vge_stop (struct vge_softc *); 171static void vge_watchdog (void *); 172static int vge_suspend (device_t); 173static int vge_resume (device_t); 174static int vge_shutdown (device_t); 175static int vge_ifmedia_upd (struct ifnet *); 176static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 177 178#ifdef VGE_EEPROM 179static void vge_eeprom_getword (struct vge_softc *, int, uint16_t *); 180#endif 181static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 182 183static void vge_miipoll_start (struct vge_softc *); 184static void vge_miipoll_stop (struct vge_softc *); 185static int vge_miibus_readreg (device_t, int, int); 186static int vge_miibus_writereg (device_t, int, int, int); 187static void vge_miibus_statchg (device_t); 188 189static void vge_cam_clear (struct vge_softc *); 190static int vge_cam_set (struct vge_softc *, uint8_t *); 191static void vge_setmulti (struct vge_softc *); 192static void vge_reset (struct vge_softc *); 193 194static device_method_t vge_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, vge_probe), 197 DEVMETHOD(device_attach, vge_attach), 198 DEVMETHOD(device_detach, vge_detach), 199 DEVMETHOD(device_suspend, vge_suspend), 200 DEVMETHOD(device_resume, vge_resume), 201 DEVMETHOD(device_shutdown, vge_shutdown), 202 203 /* bus interface */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211 212 { 0, 0 } 213}; 214 215static driver_t vge_driver = { 216 "vge", 217 vge_methods, 218 sizeof(struct vge_softc) 219}; 220 221static devclass_t vge_devclass; 222 223DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226#ifdef VGE_EEPROM 227/* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230static void 231vge_eeprom_getword(struct vge_softc *sc, int addr, uint16_t *dest) 232{ 233 int i; 234 uint16_t word = 0; 235 236 /* 237 * Enter EEPROM embedded programming mode. In order to 238 * access the EEPROM at all, we first have to set the 239 * EELOAD bit in the CHIPCFG2 register. 240 */ 241 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 242 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 243 244 /* Select the address of the word we want to read */ 245 CSR_WRITE_1(sc, VGE_EEADDR, addr); 246 247 /* Issue read command */ 248 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 249 250 /* Wait for the done bit to be set. */ 251 for (i = 0; i < VGE_TIMEOUT; i++) { 252 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 253 break; 254 } 255 256 if (i == VGE_TIMEOUT) { 257 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 258 *dest = 0; 259 return; 260 } 261 262 /* Read the result */ 263 word = CSR_READ_2(sc, VGE_EERDDAT); 264 265 /* Turn off EEPROM access mode. */ 266 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 267 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 268 269 *dest = word; 270} 271#endif 272 273/* 274 * Read a sequence of words from the EEPROM. 275 */ 276static void 277vge_read_eeprom(struct vge_softc *sc, caddr_t dest, int off, int cnt, int swap) 278{ 279 int i; 280#ifdef VGE_EEPROM 281 uint16_t word = 0, *ptr; 282 283 for (i = 0; i < cnt; i++) { 284 vge_eeprom_getword(sc, off + i, &word); 285 ptr = (uint16_t *)(dest + (i * 2)); 286 if (swap) 287 *ptr = ntohs(word); 288 else 289 *ptr = word; 290 } 291#else 292 for (i = 0; i < ETHER_ADDR_LEN; i++) 293 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 294#endif 295} 296 297static void 298vge_miipoll_stop(struct vge_softc *sc) 299{ 300 int i; 301 302 CSR_WRITE_1(sc, VGE_MIICMD, 0); 303 304 for (i = 0; i < VGE_TIMEOUT; i++) { 305 DELAY(1); 306 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 307 break; 308 } 309 310 if (i == VGE_TIMEOUT) 311 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 312} 313 314static void 315vge_miipoll_start(struct vge_softc *sc) 316{ 317 int i; 318 319 /* First, make sure we're idle. */ 320 321 CSR_WRITE_1(sc, VGE_MIICMD, 0); 322 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 323 324 for (i = 0; i < VGE_TIMEOUT; i++) { 325 DELAY(1); 326 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 327 break; 328 } 329 330 if (i == VGE_TIMEOUT) { 331 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 332 return; 333 } 334 335 /* Now enable auto poll mode. */ 336 337 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 338 339 /* And make sure it started. */ 340 341 for (i = 0; i < VGE_TIMEOUT; i++) { 342 DELAY(1); 343 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 344 break; 345 } 346 347 if (i == VGE_TIMEOUT) 348 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 349} 350 351static int 352vge_miibus_readreg(device_t dev, int phy, int reg) 353{ 354 struct vge_softc *sc; 355 int i; 356 uint16_t rval = 0; 357 358 sc = device_get_softc(dev); 359 360 if (phy != sc->vge_phyaddr) 361 return (0); 362 363 vge_miipoll_stop(sc); 364 365 /* Specify the register we want to read. */ 366 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 367 368 /* Issue read command. */ 369 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 370 371 /* Wait for the read command bit to self-clear. */ 372 for (i = 0; i < VGE_TIMEOUT; i++) { 373 DELAY(1); 374 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 375 break; 376 } 377 378 if (i == VGE_TIMEOUT) 379 device_printf(sc->vge_dev, "MII read timed out\n"); 380 else 381 rval = CSR_READ_2(sc, VGE_MIIDATA); 382 383 vge_miipoll_start(sc); 384 385 return (rval); 386} 387 388static int 389vge_miibus_writereg(device_t dev, int phy, int reg, int data) 390{ 391 struct vge_softc *sc; 392 int i, rval = 0; 393 394 sc = device_get_softc(dev); 395 396 if (phy != sc->vge_phyaddr) 397 return (0); 398 399 vge_miipoll_stop(sc); 400 401 /* Specify the register we want to write. */ 402 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 403 404 /* Specify the data we want to write. */ 405 CSR_WRITE_2(sc, VGE_MIIDATA, data); 406 407 /* Issue write command. */ 408 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 409 410 /* Wait for the write command bit to self-clear. */ 411 for (i = 0; i < VGE_TIMEOUT; i++) { 412 DELAY(1); 413 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 414 break; 415 } 416 417 if (i == VGE_TIMEOUT) { 418 device_printf(sc->vge_dev, "MII write timed out\n"); 419 rval = EIO; 420 } 421 422 vge_miipoll_start(sc); 423 424 return (rval); 425} 426 427static void 428vge_cam_clear(struct vge_softc *sc) 429{ 430 int i; 431 432 /* 433 * Turn off all the mask bits. This tells the chip 434 * that none of the entries in the CAM filter are valid. 435 * desired entries will be enabled as we fill the filter in. 436 */ 437 438 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 439 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 440 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 441 for (i = 0; i < 8; i++) 442 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 443 444 /* Clear the VLAN filter too. */ 445 446 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 447 for (i = 0; i < 8; i++) 448 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 449 450 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 451 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 452 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 453 454 sc->vge_camidx = 0; 455} 456 457static int 458vge_cam_set(struct vge_softc *sc, uint8_t *addr) 459{ 460 int i, error = 0; 461 462 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 463 return (ENOSPC); 464 465 /* Select the CAM data page. */ 466 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 467 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 468 469 /* Set the filter entry we want to update and enable writing. */ 470 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 471 472 /* Write the address to the CAM registers */ 473 for (i = 0; i < ETHER_ADDR_LEN; i++) 474 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 475 476 /* Issue a write command. */ 477 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 478 479 /* Wake for it to clear. */ 480 for (i = 0; i < VGE_TIMEOUT; i++) { 481 DELAY(1); 482 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 483 break; 484 } 485 486 if (i == VGE_TIMEOUT) { 487 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 488 error = EIO; 489 goto fail; 490 } 491 492 /* Select the CAM mask page. */ 493 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 494 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 495 496 /* Set the mask bit that enables this filter. */ 497 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 498 1<<(sc->vge_camidx & 7)); 499 500 sc->vge_camidx++; 501 502fail: 503 /* Turn off access to CAM. */ 504 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 505 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 506 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 507 508 return (error); 509} 510 511/* 512 * Program the multicast filter. We use the 64-entry CAM filter 513 * for perfect filtering. If there's more than 64 multicast addresses, 514 * we use the hash filter instead. 515 */ 516static void 517vge_setmulti(struct vge_softc *sc) 518{ 519 struct ifnet *ifp; 520 int error = 0/*, h = 0*/; 521 struct ifmultiaddr *ifma; 522 uint32_t h, hashes[2] = { 0, 0 }; 523 524 VGE_LOCK_ASSERT(sc); 525 526 ifp = sc->vge_ifp; 527 528 /* First, zot all the multicast entries. */ 529 vge_cam_clear(sc); 530 CSR_WRITE_4(sc, VGE_MAR0, 0); 531 CSR_WRITE_4(sc, VGE_MAR1, 0); 532 533 /* 534 * If the user wants allmulti or promisc mode, enable reception 535 * of all multicast frames. 536 */ 537 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 538 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 539 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 540 return; 541 } 542 543 /* Now program new ones */ 544 if_maddr_rlock(ifp); 545 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 546 if (ifma->ifma_addr->sa_family != AF_LINK) 547 continue; 548 error = vge_cam_set(sc, 549 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 550 if (error) 551 break; 552 } 553 554 /* If there were too many addresses, use the hash filter. */ 555 if (error) { 556 vge_cam_clear(sc); 557 558 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 559 if (ifma->ifma_addr->sa_family != AF_LINK) 560 continue; 561 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 562 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 563 if (h < 32) 564 hashes[0] |= (1 << h); 565 else 566 hashes[1] |= (1 << (h - 32)); 567 } 568 569 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 570 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 571 } 572 if_maddr_runlock(ifp); 573} 574 575static void 576vge_reset(struct vge_softc *sc) 577{ 578 int i; 579 580 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 581 582 for (i = 0; i < VGE_TIMEOUT; i++) { 583 DELAY(5); 584 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 585 break; 586 } 587 588 if (i == VGE_TIMEOUT) { 589 device_printf(sc->vge_dev, "soft reset timed out\n"); 590 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 591 DELAY(2000); 592 } 593 594 DELAY(5000); 595} 596 597/* 598 * Probe for a VIA gigabit chip. Check the PCI vendor and device 599 * IDs against our list and return a device name if we find a match. 600 */ 601static int 602vge_probe(device_t dev) 603{ 604 struct vge_type *t; 605 606 t = vge_devs; 607 608 while (t->vge_name != NULL) { 609 if ((pci_get_vendor(dev) == t->vge_vid) && 610 (pci_get_device(dev) == t->vge_did)) { 611 device_set_desc(dev, t->vge_name); 612 return (BUS_PROBE_DEFAULT); 613 } 614 t++; 615 } 616 617 return (ENXIO); 618} 619 620/* 621 * Map a single buffer address. 622 */ 623 624struct vge_dmamap_arg { 625 bus_addr_t vge_busaddr; 626}; 627 628static void 629vge_dmamap_cb(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 630{ 631 struct vge_dmamap_arg *ctx; 632 633 if (error != 0) 634 return; 635 636 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 637 638 ctx = (struct vge_dmamap_arg *)arg; 639 ctx->vge_busaddr = segs[0].ds_addr; 640} 641 642static int 643vge_dma_alloc(struct vge_softc *sc) 644{ 645 struct vge_dmamap_arg ctx; 646 struct vge_txdesc *txd; 647 struct vge_rxdesc *rxd; 648 bus_addr_t lowaddr, tx_ring_end, rx_ring_end; 649 int error, i; 650 651 lowaddr = BUS_SPACE_MAXADDR; 652 653again: 654 /* Create parent ring tag. */ 655 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 656 1, 0, /* algnmnt, boundary */ 657 lowaddr, /* lowaddr */ 658 BUS_SPACE_MAXADDR, /* highaddr */ 659 NULL, NULL, /* filter, filterarg */ 660 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 661 0, /* nsegments */ 662 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 663 0, /* flags */ 664 NULL, NULL, /* lockfunc, lockarg */ 665 &sc->vge_cdata.vge_ring_tag); 666 if (error != 0) { 667 device_printf(sc->vge_dev, 668 "could not create parent DMA tag.\n"); 669 goto fail; 670 } 671 672 /* Create tag for Tx ring. */ 673 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 674 VGE_TX_RING_ALIGN, 0, /* algnmnt, boundary */ 675 BUS_SPACE_MAXADDR, /* lowaddr */ 676 BUS_SPACE_MAXADDR, /* highaddr */ 677 NULL, NULL, /* filter, filterarg */ 678 VGE_TX_LIST_SZ, /* maxsize */ 679 1, /* nsegments */ 680 VGE_TX_LIST_SZ, /* maxsegsize */ 681 0, /* flags */ 682 NULL, NULL, /* lockfunc, lockarg */ 683 &sc->vge_cdata.vge_tx_ring_tag); 684 if (error != 0) { 685 device_printf(sc->vge_dev, 686 "could not allocate Tx ring DMA tag.\n"); 687 goto fail; 688 } 689 690 /* Create tag for Rx ring. */ 691 error = bus_dma_tag_create(sc->vge_cdata.vge_ring_tag,/* parent */ 692 VGE_RX_RING_ALIGN, 0, /* algnmnt, boundary */ 693 BUS_SPACE_MAXADDR, /* lowaddr */ 694 BUS_SPACE_MAXADDR, /* highaddr */ 695 NULL, NULL, /* filter, filterarg */ 696 VGE_RX_LIST_SZ, /* maxsize */ 697 1, /* nsegments */ 698 VGE_RX_LIST_SZ, /* maxsegsize */ 699 0, /* flags */ 700 NULL, NULL, /* lockfunc, lockarg */ 701 &sc->vge_cdata.vge_rx_ring_tag); 702 if (error != 0) { 703 device_printf(sc->vge_dev, 704 "could not allocate Rx ring DMA tag.\n"); 705 goto fail; 706 } 707 708 /* Allocate DMA'able memory and load the DMA map for Tx ring. */ 709 error = bus_dmamem_alloc(sc->vge_cdata.vge_tx_ring_tag, 710 (void **)&sc->vge_rdata.vge_tx_ring, 711 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 712 &sc->vge_cdata.vge_tx_ring_map); 713 if (error != 0) { 714 device_printf(sc->vge_dev, 715 "could not allocate DMA'able memory for Tx ring.\n"); 716 goto fail; 717 } 718 719 ctx.vge_busaddr = 0; 720 error = bus_dmamap_load(sc->vge_cdata.vge_tx_ring_tag, 721 sc->vge_cdata.vge_tx_ring_map, sc->vge_rdata.vge_tx_ring, 722 VGE_TX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 723 if (error != 0 || ctx.vge_busaddr == 0) { 724 device_printf(sc->vge_dev, 725 "could not load DMA'able memory for Tx ring.\n"); 726 goto fail; 727 } 728 sc->vge_rdata.vge_tx_ring_paddr = ctx.vge_busaddr; 729 730 /* Allocate DMA'able memory and load the DMA map for Rx ring. */ 731 error = bus_dmamem_alloc(sc->vge_cdata.vge_rx_ring_tag, 732 (void **)&sc->vge_rdata.vge_rx_ring, 733 BUS_DMA_WAITOK | BUS_DMA_ZERO | BUS_DMA_COHERENT, 734 &sc->vge_cdata.vge_rx_ring_map); 735 if (error != 0) { 736 device_printf(sc->vge_dev, 737 "could not allocate DMA'able memory for Rx ring.\n"); 738 goto fail; 739 } 740 741 ctx.vge_busaddr = 0; 742 error = bus_dmamap_load(sc->vge_cdata.vge_rx_ring_tag, 743 sc->vge_cdata.vge_rx_ring_map, sc->vge_rdata.vge_rx_ring, 744 VGE_RX_LIST_SZ, vge_dmamap_cb, &ctx, BUS_DMA_NOWAIT); 745 if (error != 0 || ctx.vge_busaddr == 0) { 746 device_printf(sc->vge_dev, 747 "could not load DMA'able memory for Rx ring.\n"); 748 goto fail; 749 } 750 sc->vge_rdata.vge_rx_ring_paddr = ctx.vge_busaddr; 751 752 /* Tx/Rx descriptor queue should reside within 4GB boundary. */ 753 tx_ring_end = sc->vge_rdata.vge_tx_ring_paddr + VGE_TX_LIST_SZ; 754 rx_ring_end = sc->vge_rdata.vge_rx_ring_paddr + VGE_RX_LIST_SZ; 755 if ((VGE_ADDR_HI(tx_ring_end) != 756 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)) || 757 (VGE_ADDR_HI(rx_ring_end) != 758 VGE_ADDR_HI(sc->vge_rdata.vge_rx_ring_paddr)) || 759 VGE_ADDR_HI(tx_ring_end) != VGE_ADDR_HI(rx_ring_end)) { 760 device_printf(sc->vge_dev, "4GB boundary crossed, " 761 "switching to 32bit DMA address mode.\n"); 762 vge_dma_free(sc); 763 /* Limit DMA address space to 32bit and try again. */ 764 lowaddr = BUS_SPACE_MAXADDR_32BIT; 765 goto again; 766 } 767 768 /* Create parent buffer tag. */ 769 error = bus_dma_tag_create(bus_get_dma_tag(sc->vge_dev),/* parent */ 770 1, 0, /* algnmnt, boundary */ 771 VGE_BUF_DMA_MAXADDR, /* lowaddr */ 772 BUS_SPACE_MAXADDR, /* highaddr */ 773 NULL, NULL, /* filter, filterarg */ 774 BUS_SPACE_MAXSIZE_32BIT, /* maxsize */ 775 0, /* nsegments */ 776 BUS_SPACE_MAXSIZE_32BIT, /* maxsegsize */ 777 0, /* flags */ 778 NULL, NULL, /* lockfunc, lockarg */ 779 &sc->vge_cdata.vge_buffer_tag); 780 if (error != 0) { 781 device_printf(sc->vge_dev, 782 "could not create parent buffer DMA tag.\n"); 783 goto fail; 784 } 785 786 /* Create tag for Tx buffers. */ 787 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 788 1, 0, /* algnmnt, boundary */ 789 BUS_SPACE_MAXADDR, /* lowaddr */ 790 BUS_SPACE_MAXADDR, /* highaddr */ 791 NULL, NULL, /* filter, filterarg */ 792 MCLBYTES * VGE_MAXTXSEGS, /* maxsize */ 793 VGE_MAXTXSEGS, /* nsegments */ 794 MCLBYTES, /* maxsegsize */ 795 0, /* flags */ 796 NULL, NULL, /* lockfunc, lockarg */ 797 &sc->vge_cdata.vge_tx_tag); 798 if (error != 0) { 799 device_printf(sc->vge_dev, "could not create Tx DMA tag.\n"); 800 goto fail; 801 } 802 803 /* Create tag for Rx buffers. */ 804 error = bus_dma_tag_create(sc->vge_cdata.vge_buffer_tag,/* parent */ 805 VGE_RX_BUF_ALIGN, 0, /* algnmnt, boundary */ 806 BUS_SPACE_MAXADDR, /* lowaddr */ 807 BUS_SPACE_MAXADDR, /* highaddr */ 808 NULL, NULL, /* filter, filterarg */ 809 MCLBYTES, /* maxsize */ 810 1, /* nsegments */ 811 MCLBYTES, /* maxsegsize */ 812 0, /* flags */ 813 NULL, NULL, /* lockfunc, lockarg */ 814 &sc->vge_cdata.vge_rx_tag); 815 if (error != 0) { 816 device_printf(sc->vge_dev, "could not create Rx DMA tag.\n"); 817 goto fail; 818 } 819 820 /* Create DMA maps for Tx buffers. */ 821 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 822 txd = &sc->vge_cdata.vge_txdesc[i]; 823 txd->tx_m = NULL; 824 txd->tx_dmamap = NULL; 825 error = bus_dmamap_create(sc->vge_cdata.vge_tx_tag, 0, 826 &txd->tx_dmamap); 827 if (error != 0) { 828 device_printf(sc->vge_dev, 829 "could not create Tx dmamap.\n"); 830 goto fail; 831 } 832 } 833 /* Create DMA maps for Rx buffers. */ 834 if ((error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 835 &sc->vge_cdata.vge_rx_sparemap)) != 0) { 836 device_printf(sc->vge_dev, 837 "could not create spare Rx dmamap.\n"); 838 goto fail; 839 } 840 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 841 rxd = &sc->vge_cdata.vge_rxdesc[i]; 842 rxd->rx_m = NULL; 843 rxd->rx_dmamap = NULL; 844 error = bus_dmamap_create(sc->vge_cdata.vge_rx_tag, 0, 845 &rxd->rx_dmamap); 846 if (error != 0) { 847 device_printf(sc->vge_dev, 848 "could not create Rx dmamap.\n"); 849 goto fail; 850 } 851 } 852 853fail: 854 return (error); 855} 856 857static void 858vge_dma_free(struct vge_softc *sc) 859{ 860 struct vge_txdesc *txd; 861 struct vge_rxdesc *rxd; 862 int i; 863 864 /* Tx ring. */ 865 if (sc->vge_cdata.vge_tx_ring_tag != NULL) { 866 if (sc->vge_cdata.vge_tx_ring_map) 867 bus_dmamap_unload(sc->vge_cdata.vge_tx_ring_tag, 868 sc->vge_cdata.vge_tx_ring_map); 869 if (sc->vge_cdata.vge_tx_ring_map && 870 sc->vge_rdata.vge_tx_ring) 871 bus_dmamem_free(sc->vge_cdata.vge_tx_ring_tag, 872 sc->vge_rdata.vge_tx_ring, 873 sc->vge_cdata.vge_tx_ring_map); 874 sc->vge_rdata.vge_tx_ring = NULL; 875 sc->vge_cdata.vge_tx_ring_map = NULL; 876 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_ring_tag); 877 sc->vge_cdata.vge_tx_ring_tag = NULL; 878 } 879 /* Rx ring. */ 880 if (sc->vge_cdata.vge_rx_ring_tag != NULL) { 881 if (sc->vge_cdata.vge_rx_ring_map) 882 bus_dmamap_unload(sc->vge_cdata.vge_rx_ring_tag, 883 sc->vge_cdata.vge_rx_ring_map); 884 if (sc->vge_cdata.vge_rx_ring_map && 885 sc->vge_rdata.vge_rx_ring) 886 bus_dmamem_free(sc->vge_cdata.vge_rx_ring_tag, 887 sc->vge_rdata.vge_rx_ring, 888 sc->vge_cdata.vge_rx_ring_map); 889 sc->vge_rdata.vge_rx_ring = NULL; 890 sc->vge_cdata.vge_rx_ring_map = NULL; 891 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_ring_tag); 892 sc->vge_cdata.vge_rx_ring_tag = NULL; 893 } 894 /* Tx buffers. */ 895 if (sc->vge_cdata.vge_tx_tag != NULL) { 896 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 897 txd = &sc->vge_cdata.vge_txdesc[i]; 898 if (txd->tx_dmamap != NULL) { 899 bus_dmamap_destroy(sc->vge_cdata.vge_tx_tag, 900 txd->tx_dmamap); 901 txd->tx_dmamap = NULL; 902 } 903 } 904 bus_dma_tag_destroy(sc->vge_cdata.vge_tx_tag); 905 sc->vge_cdata.vge_tx_tag = NULL; 906 } 907 /* Rx buffers. */ 908 if (sc->vge_cdata.vge_rx_tag != NULL) { 909 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 910 rxd = &sc->vge_cdata.vge_rxdesc[i]; 911 if (rxd->rx_dmamap != NULL) { 912 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 913 rxd->rx_dmamap); 914 rxd->rx_dmamap = NULL; 915 } 916 } 917 if (sc->vge_cdata.vge_rx_sparemap != NULL) { 918 bus_dmamap_destroy(sc->vge_cdata.vge_rx_tag, 919 sc->vge_cdata.vge_rx_sparemap); 920 sc->vge_cdata.vge_rx_sparemap = NULL; 921 } 922 bus_dma_tag_destroy(sc->vge_cdata.vge_rx_tag); 923 sc->vge_cdata.vge_rx_tag = NULL; 924 } 925 926 if (sc->vge_cdata.vge_buffer_tag != NULL) { 927 bus_dma_tag_destroy(sc->vge_cdata.vge_buffer_tag); 928 sc->vge_cdata.vge_buffer_tag = NULL; 929 } 930 if (sc->vge_cdata.vge_ring_tag != NULL) { 931 bus_dma_tag_destroy(sc->vge_cdata.vge_ring_tag); 932 sc->vge_cdata.vge_ring_tag = NULL; 933 } 934} 935 936/* 937 * Attach the interface. Allocate softc structures, do ifmedia 938 * setup and ethernet/BPF attach. 939 */ 940static int 941vge_attach(device_t dev) 942{ 943 u_char eaddr[ETHER_ADDR_LEN]; 944 struct vge_softc *sc; 945 struct ifnet *ifp; 946 int error = 0, cap, i, msic, rid; 947 948 sc = device_get_softc(dev); 949 sc->vge_dev = dev; 950 951 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 952 MTX_DEF); 953 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 954 955 /* 956 * Map control/status registers. 957 */ 958 pci_enable_busmaster(dev); 959 960 rid = PCIR_BAR(1); 961 sc->vge_res = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &rid, 962 RF_ACTIVE); 963 964 if (sc->vge_res == NULL) { 965 device_printf(dev, "couldn't map ports/memory\n"); 966 error = ENXIO; 967 goto fail; 968 } 969 970 if (pci_find_extcap(dev, PCIY_EXPRESS, &cap) == 0) { 971 sc->vge_flags |= VGE_FLAG_PCIE; 972 sc->vge_expcap = cap; 973 } 974 rid = 0; 975 msic = pci_msi_count(dev); 976 if (msi_disable == 0 && msic > 0) { 977 msic = 1; 978 if (pci_alloc_msi(dev, &msic) == 0) { 979 if (msic == 1) { 980 sc->vge_flags |= VGE_FLAG_MSI; 981 device_printf(dev, "Using %d MSI message\n", 982 msic); 983 rid = 1; 984 } else 985 pci_release_msi(dev); 986 } 987 } 988 989 /* Allocate interrupt */ 990 sc->vge_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 991 ((sc->vge_flags & VGE_FLAG_MSI) ? 0 : RF_SHAREABLE) | RF_ACTIVE); 992 if (sc->vge_irq == NULL) { 993 device_printf(dev, "couldn't map interrupt\n"); 994 error = ENXIO; 995 goto fail; 996 } 997 998 /* Reset the adapter. */ 999 vge_reset(sc); 1000 /* Reload EEPROM. */ 1001 CSR_WRITE_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 1002 for (i = 0; i < VGE_TIMEOUT; i++) { 1003 DELAY(5); 1004 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 1005 break; 1006 } 1007 if (i == VGE_TIMEOUT) 1008 device_printf(dev, "EEPROM reload timed out\n"); 1009 /* 1010 * Clear PACPI as EEPROM reload will set the bit. Otherwise 1011 * MAC will receive magic packet which in turn confuses 1012 * controller. 1013 */ 1014 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 1015 1016 /* 1017 * Get station address from the EEPROM. 1018 */ 1019 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1020 /* 1021 * Save configured PHY address. 1022 * It seems the PHY address of PCIe controllers just 1023 * reflects media jump strapping status so we assume the 1024 * internal PHY address of PCIe controller is at 1. 1025 */ 1026 if ((sc->vge_flags & VGE_FLAG_PCIE) != 0) 1027 sc->vge_phyaddr = 1; 1028 else 1029 sc->vge_phyaddr = CSR_READ_1(sc, VGE_MIICFG) & 1030 VGE_MIICFG_PHYADDR; 1031 error = vge_dma_alloc(sc); 1032 if (error) 1033 goto fail; 1034 1035 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1036 if (ifp == NULL) { 1037 device_printf(dev, "can not if_alloc()\n"); 1038 error = ENOSPC; 1039 goto fail; 1040 } 1041 1042 /* Do MII setup */ 1043 if (mii_phy_probe(dev, &sc->vge_miibus, 1044 vge_ifmedia_upd, vge_ifmedia_sts)) { 1045 device_printf(dev, "MII without any phy!\n"); 1046 error = ENXIO; 1047 goto fail; 1048 } 1049 1050 ifp->if_softc = sc; 1051 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1052 ifp->if_mtu = ETHERMTU; 1053 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1054 ifp->if_ioctl = vge_ioctl; 1055 ifp->if_capabilities = IFCAP_VLAN_MTU; 1056 ifp->if_start = vge_start; 1057 ifp->if_hwassist = VGE_CSUM_FEATURES; 1058 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1059 ifp->if_capenable = ifp->if_capabilities; 1060#ifdef DEVICE_POLLING 1061 ifp->if_capabilities |= IFCAP_POLLING; 1062#endif 1063 ifp->if_init = vge_init; 1064 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_TX_DESC_CNT - 1); 1065 ifp->if_snd.ifq_drv_maxlen = VGE_TX_DESC_CNT - 1; 1066 IFQ_SET_READY(&ifp->if_snd); 1067 1068 /* 1069 * Call MI attach routine. 1070 */ 1071 ether_ifattach(ifp, eaddr); 1072 1073 /* Hook interrupt last to avoid having to lock softc */ 1074 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1075 NULL, vge_intr, sc, &sc->vge_intrhand); 1076 1077 if (error) { 1078 device_printf(dev, "couldn't set up irq\n"); 1079 ether_ifdetach(ifp); 1080 goto fail; 1081 } 1082 1083fail: 1084 if (error) 1085 vge_detach(dev); 1086 1087 return (error); 1088} 1089 1090/* 1091 * Shutdown hardware and free up resources. This can be called any 1092 * time after the mutex has been initialized. It is called in both 1093 * the error case in attach and the normal detach case so it needs 1094 * to be careful about only freeing resources that have actually been 1095 * allocated. 1096 */ 1097static int 1098vge_detach(device_t dev) 1099{ 1100 struct vge_softc *sc; 1101 struct ifnet *ifp; 1102 1103 sc = device_get_softc(dev); 1104 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1105 ifp = sc->vge_ifp; 1106 1107#ifdef DEVICE_POLLING 1108 if (ifp->if_capenable & IFCAP_POLLING) 1109 ether_poll_deregister(ifp); 1110#endif 1111 1112 /* These should only be active if attach succeeded */ 1113 if (device_is_attached(dev)) { 1114 ether_ifdetach(ifp); 1115 VGE_LOCK(sc); 1116 vge_stop(sc); 1117 VGE_UNLOCK(sc); 1118 callout_drain(&sc->vge_watchdog); 1119 } 1120 if (sc->vge_miibus) 1121 device_delete_child(dev, sc->vge_miibus); 1122 bus_generic_detach(dev); 1123 1124 if (sc->vge_intrhand) 1125 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1126 if (sc->vge_irq) 1127 bus_release_resource(dev, SYS_RES_IRQ, 1128 sc->vge_flags & VGE_FLAG_MSI ? 1 : 0, sc->vge_irq); 1129 if (sc->vge_flags & VGE_FLAG_MSI) 1130 pci_release_msi(dev); 1131 if (sc->vge_res) 1132 bus_release_resource(dev, SYS_RES_MEMORY, 1133 PCIR_BAR(1), sc->vge_res); 1134 if (ifp) 1135 if_free(ifp); 1136 1137 vge_dma_free(sc); 1138 mtx_destroy(&sc->vge_mtx); 1139 1140 return (0); 1141} 1142 1143static void 1144vge_discard_rxbuf(struct vge_softc *sc, int prod) 1145{ 1146 struct vge_rxdesc *rxd; 1147 int i; 1148 1149 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1150 rxd->rx_desc->vge_sts = 0; 1151 rxd->rx_desc->vge_ctl = 0; 1152 1153 /* 1154 * Note: the manual fails to document the fact that for 1155 * proper opration, the driver needs to replentish the RX 1156 * DMA ring 4 descriptors at a time (rather than one at a 1157 * time, like most chips). We can allocate the new buffers 1158 * but we should not set the OWN bits until we're ready 1159 * to hand back 4 of them in one shot. 1160 */ 1161 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1162 for (i = VGE_RXCHUNK; i > 0; i--) { 1163 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1164 rxd = rxd->rxd_prev; 1165 } 1166 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1167 } 1168} 1169 1170static int 1171vge_newbuf(struct vge_softc *sc, int prod) 1172{ 1173 struct vge_rxdesc *rxd; 1174 struct mbuf *m; 1175 bus_dma_segment_t segs[1]; 1176 bus_dmamap_t map; 1177 int i, nsegs; 1178 1179 m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1180 if (m == NULL) 1181 return (ENOBUFS); 1182 /* 1183 * This is part of an evil trick to deal with strict-alignment 1184 * architectures. The VIA chip requires RX buffers to be aligned 1185 * on 32-bit boundaries, but that will hose strict-alignment 1186 * architectures. To get around this, we leave some empty space 1187 * at the start of each buffer and for non-strict-alignment hosts, 1188 * we copy the buffer back two bytes to achieve word alignment. 1189 * This is slightly more efficient than allocating a new buffer, 1190 * copying the contents, and discarding the old buffer. 1191 */ 1192 m->m_len = m->m_pkthdr.len = MCLBYTES; 1193 m_adj(m, VGE_RX_BUF_ALIGN); 1194 1195 if (bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_rx_tag, 1196 sc->vge_cdata.vge_rx_sparemap, m, segs, &nsegs, 0) != 0) { 1197 m_freem(m); 1198 return (ENOBUFS); 1199 } 1200 KASSERT(nsegs == 1, ("%s: %d segments returned!", __func__, nsegs)); 1201 1202 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1203 if (rxd->rx_m != NULL) { 1204 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1205 BUS_DMASYNC_POSTREAD); 1206 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap); 1207 } 1208 map = rxd->rx_dmamap; 1209 rxd->rx_dmamap = sc->vge_cdata.vge_rx_sparemap; 1210 sc->vge_cdata.vge_rx_sparemap = map; 1211 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, rxd->rx_dmamap, 1212 BUS_DMASYNC_PREREAD); 1213 rxd->rx_m = m; 1214 1215 rxd->rx_desc->vge_sts = 0; 1216 rxd->rx_desc->vge_ctl = 0; 1217 rxd->rx_desc->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 1218 rxd->rx_desc->vge_addrhi = htole32(VGE_ADDR_HI(segs[0].ds_addr) | 1219 (VGE_BUFLEN(segs[0].ds_len) << 16) | VGE_RXDESC_I); 1220 1221 /* 1222 * Note: the manual fails to document the fact that for 1223 * proper operation, the driver needs to replenish the RX 1224 * DMA ring 4 descriptors at a time (rather than one at a 1225 * time, like most chips). We can allocate the new buffers 1226 * but we should not set the OWN bits until we're ready 1227 * to hand back 4 of them in one shot. 1228 */ 1229 if ((prod % VGE_RXCHUNK) == (VGE_RXCHUNK - 1)) { 1230 for (i = VGE_RXCHUNK; i > 0; i--) { 1231 rxd->rx_desc->vge_sts = htole32(VGE_RDSTS_OWN); 1232 rxd = rxd->rxd_prev; 1233 } 1234 sc->vge_cdata.vge_rx_commit += VGE_RXCHUNK; 1235 } 1236 1237 return (0); 1238} 1239 1240static int 1241vge_tx_list_init(struct vge_softc *sc) 1242{ 1243 struct vge_ring_data *rd; 1244 struct vge_txdesc *txd; 1245 int i; 1246 1247 VGE_LOCK_ASSERT(sc); 1248 1249 sc->vge_cdata.vge_tx_prodidx = 0; 1250 sc->vge_cdata.vge_tx_considx = 0; 1251 sc->vge_cdata.vge_tx_cnt = 0; 1252 1253 rd = &sc->vge_rdata; 1254 bzero(rd->vge_tx_ring, VGE_TX_LIST_SZ); 1255 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1256 txd = &sc->vge_cdata.vge_txdesc[i]; 1257 txd->tx_m = NULL; 1258 txd->tx_desc = &rd->vge_tx_ring[i]; 1259 } 1260 1261 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1262 sc->vge_cdata.vge_tx_ring_map, 1263 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1264 1265 return (0); 1266} 1267 1268static int 1269vge_rx_list_init(struct vge_softc *sc) 1270{ 1271 struct vge_ring_data *rd; 1272 struct vge_rxdesc *rxd; 1273 int i; 1274 1275 VGE_LOCK_ASSERT(sc); 1276 1277 sc->vge_cdata.vge_rx_prodidx = 0; 1278 sc->vge_cdata.vge_head = NULL; 1279 sc->vge_cdata.vge_tail = NULL; 1280 sc->vge_cdata.vge_rx_commit = 0; 1281 1282 rd = &sc->vge_rdata; 1283 bzero(rd->vge_rx_ring, VGE_RX_LIST_SZ); 1284 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1285 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1286 rxd->rx_m = NULL; 1287 rxd->rx_desc = &rd->vge_rx_ring[i]; 1288 if (i == 0) 1289 rxd->rxd_prev = 1290 &sc->vge_cdata.vge_rxdesc[VGE_RX_DESC_CNT - 1]; 1291 else 1292 rxd->rxd_prev = &sc->vge_cdata.vge_rxdesc[i - 1]; 1293 if (vge_newbuf(sc, i) != 0) 1294 return (ENOBUFS); 1295 } 1296 1297 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1298 sc->vge_cdata.vge_rx_ring_map, 1299 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1300 1301 sc->vge_cdata.vge_rx_commit = 0; 1302 1303 return (0); 1304} 1305 1306static void 1307vge_freebufs(struct vge_softc *sc) 1308{ 1309 struct vge_txdesc *txd; 1310 struct vge_rxdesc *rxd; 1311 struct ifnet *ifp; 1312 int i; 1313 1314 VGE_LOCK_ASSERT(sc); 1315 1316 ifp = sc->vge_ifp; 1317 /* 1318 * Free RX and TX mbufs still in the queues. 1319 */ 1320 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1321 rxd = &sc->vge_cdata.vge_rxdesc[i]; 1322 if (rxd->rx_m != NULL) { 1323 bus_dmamap_sync(sc->vge_cdata.vge_rx_tag, 1324 rxd->rx_dmamap, BUS_DMASYNC_POSTREAD); 1325 bus_dmamap_unload(sc->vge_cdata.vge_rx_tag, 1326 rxd->rx_dmamap); 1327 m_freem(rxd->rx_m); 1328 rxd->rx_m = NULL; 1329 } 1330 } 1331 1332 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 1333 txd = &sc->vge_cdata.vge_txdesc[i]; 1334 if (txd->tx_m != NULL) { 1335 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, 1336 txd->tx_dmamap, BUS_DMASYNC_POSTWRITE); 1337 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, 1338 txd->tx_dmamap); 1339 m_freem(txd->tx_m); 1340 txd->tx_m = NULL; 1341 ifp->if_oerrors++; 1342 } 1343 } 1344} 1345 1346#ifndef __NO_STRICT_ALIGNMENT 1347static __inline void 1348vge_fixup_rx(struct mbuf *m) 1349{ 1350 int i; 1351 uint16_t *src, *dst; 1352 1353 src = mtod(m, uint16_t *); 1354 dst = src - 1; 1355 1356 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1357 *dst++ = *src++; 1358 1359 m->m_data -= ETHER_ALIGN; 1360} 1361#endif 1362 1363/* 1364 * RX handler. We support the reception of jumbo frames that have 1365 * been fragmented across multiple 2K mbuf cluster buffers. 1366 */ 1367static int 1368vge_rxeof(struct vge_softc *sc, int count) 1369{ 1370 struct mbuf *m; 1371 struct ifnet *ifp; 1372 int prod, prog, total_len; 1373 struct vge_rxdesc *rxd; 1374 struct vge_rx_desc *cur_rx; 1375 uint32_t rxstat, rxctl; 1376 1377 VGE_LOCK_ASSERT(sc); 1378 1379 ifp = sc->vge_ifp; 1380 1381 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1382 sc->vge_cdata.vge_rx_ring_map, 1383 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1384 1385 prod = sc->vge_cdata.vge_rx_prodidx; 1386 for (prog = 0; count > 0 && 1387 (ifp->if_drv_flags & IFF_DRV_RUNNING) != 0; 1388 VGE_RX_DESC_INC(prod)) { 1389 cur_rx = &sc->vge_rdata.vge_rx_ring[prod]; 1390 rxstat = le32toh(cur_rx->vge_sts); 1391 if ((rxstat & VGE_RDSTS_OWN) != 0) 1392 break; 1393 count--; 1394 prog++; 1395 rxctl = le32toh(cur_rx->vge_ctl); 1396 total_len = VGE_RXBYTES(rxstat); 1397 rxd = &sc->vge_cdata.vge_rxdesc[prod]; 1398 m = rxd->rx_m; 1399 1400 /* 1401 * If the 'start of frame' bit is set, this indicates 1402 * either the first fragment in a multi-fragment receive, 1403 * or an intermediate fragment. Either way, we want to 1404 * accumulate the buffers. 1405 */ 1406 if ((rxstat & VGE_RXPKT_SOF) != 0) { 1407 if (vge_newbuf(sc, prod) != 0) { 1408 ifp->if_iqdrops++; 1409 VGE_CHAIN_RESET(sc); 1410 vge_discard_rxbuf(sc, prod); 1411 continue; 1412 } 1413 m->m_len = MCLBYTES - VGE_RX_BUF_ALIGN; 1414 if (sc->vge_cdata.vge_head == NULL) { 1415 sc->vge_cdata.vge_head = m; 1416 sc->vge_cdata.vge_tail = m; 1417 } else { 1418 m->m_flags &= ~M_PKTHDR; 1419 sc->vge_cdata.vge_tail->m_next = m; 1420 sc->vge_cdata.vge_tail = m; 1421 } 1422 continue; 1423 } 1424 1425 /* 1426 * Bad/error frames will have the RXOK bit cleared. 1427 * However, there's one error case we want to allow: 1428 * if a VLAN tagged frame arrives and the chip can't 1429 * match it against the CAM filter, it considers this 1430 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1431 * We don't want to drop the frame though: our VLAN 1432 * filtering is done in software. 1433 * We also want to receive bad-checksummed frames and 1434 * and frames with bad-length. 1435 */ 1436 if ((rxstat & VGE_RDSTS_RXOK) == 0 && 1437 (rxstat & (VGE_RDSTS_VIDM | VGE_RDSTS_RLERR | 1438 VGE_RDSTS_CSUMERR)) == 0) { 1439 ifp->if_ierrors++; 1440 /* 1441 * If this is part of a multi-fragment packet, 1442 * discard all the pieces. 1443 */ 1444 VGE_CHAIN_RESET(sc); 1445 vge_discard_rxbuf(sc, prod); 1446 continue; 1447 } 1448 1449 if (vge_newbuf(sc, prod) != 0) { 1450 ifp->if_iqdrops++; 1451 VGE_CHAIN_RESET(sc); 1452 vge_discard_rxbuf(sc, prod); 1453 continue; 1454 } 1455 1456 /* Chain received mbufs. */ 1457 if (sc->vge_cdata.vge_head != NULL) { 1458 m->m_len = total_len % (MCLBYTES - VGE_RX_BUF_ALIGN); 1459 /* 1460 * Special case: if there's 4 bytes or less 1461 * in this buffer, the mbuf can be discarded: 1462 * the last 4 bytes is the CRC, which we don't 1463 * care about anyway. 1464 */ 1465 if (m->m_len <= ETHER_CRC_LEN) { 1466 sc->vge_cdata.vge_tail->m_len -= 1467 (ETHER_CRC_LEN - m->m_len); 1468 m_freem(m); 1469 } else { 1470 m->m_len -= ETHER_CRC_LEN; 1471 m->m_flags &= ~M_PKTHDR; 1472 sc->vge_cdata.vge_tail->m_next = m; 1473 } 1474 m = sc->vge_cdata.vge_head; 1475 m->m_flags |= M_PKTHDR; 1476 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1477 } else { 1478 m->m_flags |= M_PKTHDR; 1479 m->m_pkthdr.len = m->m_len = 1480 (total_len - ETHER_CRC_LEN); 1481 } 1482 1483#ifndef __NO_STRICT_ALIGNMENT 1484 vge_fixup_rx(m); 1485#endif 1486 m->m_pkthdr.rcvif = ifp; 1487 1488 /* Do RX checksumming if enabled */ 1489 if ((ifp->if_capenable & IFCAP_RXCSUM) != 0 && 1490 (rxctl & VGE_RDCTL_FRAG) == 0) { 1491 /* Check IP header checksum */ 1492 if ((rxctl & VGE_RDCTL_IPPKT) != 0) 1493 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1494 if ((rxctl & VGE_RDCTL_IPCSUMOK) != 0) 1495 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1496 1497 /* Check TCP/UDP checksum */ 1498 if (rxctl & (VGE_RDCTL_TCPPKT | VGE_RDCTL_UDPPKT) && 1499 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1500 m->m_pkthdr.csum_flags |= 1501 CSUM_DATA_VALID | CSUM_PSEUDO_HDR; 1502 m->m_pkthdr.csum_data = 0xffff; 1503 } 1504 } 1505 1506 if ((rxstat & VGE_RDSTS_VTAG) != 0) { 1507 /* 1508 * The 32-bit rxctl register is stored in little-endian. 1509 * However, the 16-bit vlan tag is stored in big-endian, 1510 * so we have to byte swap it. 1511 */ 1512 m->m_pkthdr.ether_vtag = 1513 bswap16(rxctl & VGE_RDCTL_VLANID); 1514 m->m_flags |= M_VLANTAG; 1515 } 1516 1517 VGE_UNLOCK(sc); 1518 (*ifp->if_input)(ifp, m); 1519 VGE_LOCK(sc); 1520 sc->vge_cdata.vge_head = NULL; 1521 sc->vge_cdata.vge_tail = NULL; 1522 } 1523 1524 if (prog > 0) { 1525 sc->vge_cdata.vge_rx_prodidx = prod; 1526 bus_dmamap_sync(sc->vge_cdata.vge_rx_ring_tag, 1527 sc->vge_cdata.vge_rx_ring_map, 1528 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1529 /* Update residue counter. */ 1530 if (sc->vge_cdata.vge_rx_commit != 0) { 1531 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, 1532 sc->vge_cdata.vge_rx_commit); 1533 sc->vge_cdata.vge_rx_commit = 0; 1534 } 1535 } 1536 return (prog); 1537} 1538 1539static void 1540vge_txeof(struct vge_softc *sc) 1541{ 1542 struct ifnet *ifp; 1543 struct vge_tx_desc *cur_tx; 1544 struct vge_txdesc *txd; 1545 uint32_t txstat; 1546 int cons, prod; 1547 1548 VGE_LOCK_ASSERT(sc); 1549 1550 ifp = sc->vge_ifp; 1551 1552 if (sc->vge_cdata.vge_tx_cnt == 0) 1553 return; 1554 1555 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1556 sc->vge_cdata.vge_tx_ring_map, 1557 BUS_DMASYNC_POSTREAD | BUS_DMASYNC_POSTWRITE); 1558 1559 /* 1560 * Go through our tx list and free mbufs for those 1561 * frames that have been transmitted. 1562 */ 1563 cons = sc->vge_cdata.vge_tx_considx; 1564 prod = sc->vge_cdata.vge_tx_prodidx; 1565 for (; cons != prod; VGE_TX_DESC_INC(cons)) { 1566 cur_tx = &sc->vge_rdata.vge_tx_ring[cons]; 1567 txstat = le32toh(cur_tx->vge_sts); 1568 if ((txstat & VGE_TDSTS_OWN) != 0) 1569 break; 1570 sc->vge_cdata.vge_tx_cnt--; 1571 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1572 1573 txd = &sc->vge_cdata.vge_txdesc[cons]; 1574 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1575 BUS_DMASYNC_POSTWRITE); 1576 bus_dmamap_unload(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap); 1577 1578 KASSERT(txd->tx_m != NULL, ("%s: freeing NULL mbuf!\n", 1579 __func__)); 1580 m_freem(txd->tx_m); 1581 txd->tx_m = NULL; 1582 txd->tx_desc->vge_frag[0].vge_addrhi = 0; 1583 } 1584 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1585 sc->vge_cdata.vge_tx_ring_map, 1586 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1587 sc->vge_cdata.vge_tx_considx = cons; 1588 if (sc->vge_cdata.vge_tx_cnt == 0) 1589 sc->vge_timer = 0; 1590 else { 1591 /* 1592 * If not all descriptors have been released reaped yet, 1593 * reload the timer so that we will eventually get another 1594 * interrupt that will cause us to re-enter this routine. 1595 * This is done in case the transmitter has gone idle. 1596 */ 1597 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1598 } 1599} 1600 1601static void 1602vge_tick(void *xsc) 1603{ 1604 struct vge_softc *sc; 1605 struct ifnet *ifp; 1606 struct mii_data *mii; 1607 1608 sc = xsc; 1609 ifp = sc->vge_ifp; 1610 VGE_LOCK_ASSERT(sc); 1611 mii = device_get_softc(sc->vge_miibus); 1612 1613 mii_tick(mii); 1614 if ((sc->vge_flags & VGE_FLAG_LINK) != 0) { 1615 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1616 sc->vge_flags &= ~VGE_FLAG_LINK; 1617 if_link_state_change(sc->vge_ifp, 1618 LINK_STATE_DOWN); 1619 } 1620 } else { 1621 if (mii->mii_media_status & IFM_ACTIVE && 1622 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1623 sc->vge_flags |= VGE_FLAG_LINK; 1624 if_link_state_change(sc->vge_ifp, 1625 LINK_STATE_UP); 1626 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1627 vge_start_locked(ifp); 1628 } 1629 } 1630} 1631 1632#ifdef DEVICE_POLLING 1633static int 1634vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1635{ 1636 struct vge_softc *sc = ifp->if_softc; 1637 int rx_npkts = 0; 1638 1639 VGE_LOCK(sc); 1640 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1641 goto done; 1642 1643 rx_npkts = vge_rxeof(sc, count); 1644 vge_txeof(sc); 1645 1646 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1647 vge_start_locked(ifp); 1648 1649 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1650 uint32_t status; 1651 status = CSR_READ_4(sc, VGE_ISR); 1652 if (status == 0xFFFFFFFF) 1653 goto done; 1654 if (status) 1655 CSR_WRITE_4(sc, VGE_ISR, status); 1656 1657 /* 1658 * XXX check behaviour on receiver stalls. 1659 */ 1660 1661 if (status & VGE_ISR_TXDMA_STALL || 1662 status & VGE_ISR_RXDMA_STALL) { 1663 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1664 vge_init_locked(sc); 1665 } 1666 1667 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1668 vge_rxeof(sc, count); 1669 ifp->if_ierrors++; 1670 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1671 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1672 } 1673 } 1674done: 1675 VGE_UNLOCK(sc); 1676 return (rx_npkts); 1677} 1678#endif /* DEVICE_POLLING */ 1679 1680static void 1681vge_intr(void *arg) 1682{ 1683 struct vge_softc *sc; 1684 struct ifnet *ifp; 1685 uint32_t status; 1686 1687 sc = arg; 1688 1689 if (sc->suspended) { 1690 return; 1691 } 1692 1693 VGE_LOCK(sc); 1694 ifp = sc->vge_ifp; 1695 1696 if (!(ifp->if_flags & IFF_UP)) { 1697 VGE_UNLOCK(sc); 1698 return; 1699 } 1700 1701#ifdef DEVICE_POLLING 1702 if (ifp->if_capenable & IFCAP_POLLING) { 1703 VGE_UNLOCK(sc); 1704 return; 1705 } 1706#endif 1707 1708 /* Disable interrupts */ 1709 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1710 1711 for (;;) { 1712 1713 status = CSR_READ_4(sc, VGE_ISR); 1714 /* If the card has gone away the read returns 0xffff. */ 1715 if (status == 0xFFFFFFFF) 1716 break; 1717 1718 if (status) 1719 CSR_WRITE_4(sc, VGE_ISR, status); 1720 1721 if ((status & VGE_INTRS) == 0) 1722 break; 1723 1724 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1725 vge_rxeof(sc, VGE_RX_DESC_CNT); 1726 1727 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1728 vge_rxeof(sc, VGE_RX_DESC_CNT); 1729 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1730 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1731 } 1732 1733 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1734 vge_txeof(sc); 1735 1736 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) { 1737 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 1738 vge_init_locked(sc); 1739 } 1740 1741 if (status & VGE_ISR_LINKSTS) 1742 vge_tick(sc); 1743 } 1744 1745 /* Re-enable interrupts */ 1746 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1747 1748 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1749 vge_start_locked(ifp); 1750 1751 VGE_UNLOCK(sc); 1752} 1753 1754static int 1755vge_encap(struct vge_softc *sc, struct mbuf **m_head) 1756{ 1757 struct vge_txdesc *txd; 1758 struct vge_tx_frag *frag; 1759 struct mbuf *m; 1760 bus_dma_segment_t txsegs[VGE_MAXTXSEGS]; 1761 int error, i, nsegs, padlen; 1762 uint32_t cflags; 1763 1764 VGE_LOCK_ASSERT(sc); 1765 1766 M_ASSERTPKTHDR((*m_head)); 1767 1768 /* Argh. This chip does not autopad short frames. */ 1769 if ((*m_head)->m_pkthdr.len < VGE_MIN_FRAMELEN) { 1770 m = *m_head; 1771 padlen = VGE_MIN_FRAMELEN - m->m_pkthdr.len; 1772 if (M_WRITABLE(m) == 0) { 1773 /* Get a writable copy. */ 1774 m = m_dup(*m_head, M_DONTWAIT); 1775 m_freem(*m_head); 1776 if (m == NULL) { 1777 *m_head = NULL; 1778 return (ENOBUFS); 1779 } 1780 *m_head = m; 1781 } 1782 if (M_TRAILINGSPACE(m) < padlen) { 1783 m = m_defrag(m, M_DONTWAIT); 1784 if (m == NULL) { 1785 m_freem(*m_head); 1786 *m_head = NULL; 1787 return (ENOBUFS); 1788 } 1789 } 1790 /* 1791 * Manually pad short frames, and zero the pad space 1792 * to avoid leaking data. 1793 */ 1794 bzero(mtod(m, char *) + m->m_pkthdr.len, padlen); 1795 m->m_pkthdr.len += padlen; 1796 m->m_len = m->m_pkthdr.len; 1797 *m_head = m; 1798 } 1799 1800 txd = &sc->vge_cdata.vge_txdesc[sc->vge_cdata.vge_tx_prodidx]; 1801 1802 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1803 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1804 if (error == EFBIG) { 1805 m = m_collapse(*m_head, M_DONTWAIT, VGE_MAXTXSEGS); 1806 if (m == NULL) { 1807 m_freem(*m_head); 1808 *m_head = NULL; 1809 return (ENOMEM); 1810 } 1811 *m_head = m; 1812 error = bus_dmamap_load_mbuf_sg(sc->vge_cdata.vge_tx_tag, 1813 txd->tx_dmamap, *m_head, txsegs, &nsegs, 0); 1814 if (error != 0) { 1815 m_freem(*m_head); 1816 *m_head = NULL; 1817 return (error); 1818 } 1819 } else if (error != 0) 1820 return (error); 1821 bus_dmamap_sync(sc->vge_cdata.vge_tx_tag, txd->tx_dmamap, 1822 BUS_DMASYNC_PREWRITE); 1823 1824 m = *m_head; 1825 cflags = 0; 1826 1827 /* Configure checksum offload. */ 1828 if ((m->m_pkthdr.csum_flags & CSUM_IP) != 0) 1829 cflags |= VGE_TDCTL_IPCSUM; 1830 if ((m->m_pkthdr.csum_flags & CSUM_TCP) != 0) 1831 cflags |= VGE_TDCTL_TCPCSUM; 1832 if ((m->m_pkthdr.csum_flags & CSUM_UDP) != 0) 1833 cflags |= VGE_TDCTL_UDPCSUM; 1834 1835 /* Configure VLAN. */ 1836 if ((m->m_flags & M_VLANTAG) != 0) 1837 cflags |= m->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG; 1838 txd->tx_desc->vge_sts = htole32(m->m_pkthdr.len << 16); 1839 /* 1840 * XXX 1841 * Velocity family seems to support TSO but no information 1842 * for MSS configuration is available. Also the number of 1843 * fragments supported by a descriptor is too small to hold 1844 * entire 64KB TCP/IP segment. Maybe VGE_TD_LS_MOF, 1845 * VGE_TD_LS_SOF and VGE_TD_LS_EOF could be used to build 1846 * longer chain of buffers but no additional information is 1847 * available. 1848 * 1849 * When telling the chip how many segments there are, we 1850 * must use nsegs + 1 instead of just nsegs. Darned if I 1851 * know why. This also means we can't use the last fragment 1852 * field of Tx descriptor. 1853 */ 1854 txd->tx_desc->vge_ctl = htole32(cflags | ((nsegs + 1) << 28) | 1855 VGE_TD_LS_NORM); 1856 for (i = 0; i < nsegs; i++) { 1857 frag = &txd->tx_desc->vge_frag[i]; 1858 frag->vge_addrlo = htole32(VGE_ADDR_LO(txsegs[i].ds_addr)); 1859 frag->vge_addrhi = htole32(VGE_ADDR_HI(txsegs[i].ds_addr) | 1860 (VGE_BUFLEN(txsegs[i].ds_len) << 16)); 1861 } 1862 1863 sc->vge_cdata.vge_tx_cnt++; 1864 VGE_TX_DESC_INC(sc->vge_cdata.vge_tx_prodidx); 1865 1866 /* 1867 * Finally request interrupt and give the first descriptor 1868 * ownership to hardware. 1869 */ 1870 txd->tx_desc->vge_ctl |= htole32(VGE_TDCTL_TIC); 1871 txd->tx_desc->vge_sts |= htole32(VGE_TDSTS_OWN); 1872 txd->tx_m = m; 1873 1874 return (0); 1875} 1876 1877/* 1878 * Main transmit routine. 1879 */ 1880 1881static void 1882vge_start(struct ifnet *ifp) 1883{ 1884 struct vge_softc *sc; 1885 1886 sc = ifp->if_softc; 1887 VGE_LOCK(sc); 1888 vge_start_locked(ifp); 1889 VGE_UNLOCK(sc); 1890} 1891 1892 1893static void 1894vge_start_locked(struct ifnet *ifp) 1895{ 1896 struct vge_softc *sc; 1897 struct vge_txdesc *txd; 1898 struct mbuf *m_head; 1899 int enq, idx; 1900 1901 sc = ifp->if_softc; 1902 1903 VGE_LOCK_ASSERT(sc); 1904 1905 if ((sc->vge_flags & VGE_FLAG_LINK) == 0 || 1906 (ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) != 1907 IFF_DRV_RUNNING) 1908 return; 1909 1910 idx = sc->vge_cdata.vge_tx_prodidx; 1911 VGE_TX_DESC_DEC(idx); 1912 for (enq = 0; !IFQ_DRV_IS_EMPTY(&ifp->if_snd) && 1913 sc->vge_cdata.vge_tx_cnt < VGE_TX_DESC_CNT - 1; ) { 1914 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1915 if (m_head == NULL) 1916 break; 1917 /* 1918 * Pack the data into the transmit ring. If we 1919 * don't have room, set the OACTIVE flag and wait 1920 * for the NIC to drain the ring. 1921 */ 1922 if (vge_encap(sc, &m_head)) { 1923 if (m_head == NULL) 1924 break; 1925 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1926 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1927 break; 1928 } 1929 1930 txd = &sc->vge_cdata.vge_txdesc[idx]; 1931 txd->tx_desc->vge_frag[0].vge_addrhi |= htole32(VGE_TXDESC_Q); 1932 VGE_TX_DESC_INC(idx); 1933 1934 enq++; 1935 /* 1936 * If there's a BPF listener, bounce a copy of this frame 1937 * to him. 1938 */ 1939 ETHER_BPF_MTAP(ifp, m_head); 1940 } 1941 1942 if (enq > 0) { 1943 bus_dmamap_sync(sc->vge_cdata.vge_tx_ring_tag, 1944 sc->vge_cdata.vge_tx_ring_map, 1945 BUS_DMASYNC_PREREAD | BUS_DMASYNC_PREWRITE); 1946 /* Issue a transmit command. */ 1947 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1948 /* 1949 * Use the countdown timer for interrupt moderation. 1950 * 'TX done' interrupts are disabled. Instead, we reset the 1951 * countdown timer, which will begin counting until it hits 1952 * the value in the SSTIMER register, and then trigger an 1953 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1954 * the timer count is reloaded. Only when the transmitter 1955 * is idle will the timer hit 0 and an interrupt fire. 1956 */ 1957 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1958 1959 /* 1960 * Set a timeout in case the chip goes out to lunch. 1961 */ 1962 sc->vge_timer = 5; 1963 } 1964} 1965 1966static void 1967vge_init(void *xsc) 1968{ 1969 struct vge_softc *sc = xsc; 1970 1971 VGE_LOCK(sc); 1972 vge_init_locked(sc); 1973 VGE_UNLOCK(sc); 1974} 1975 1976static void 1977vge_init_locked(struct vge_softc *sc) 1978{ 1979 struct ifnet *ifp = sc->vge_ifp; 1980 struct mii_data *mii; 1981 int error, i; 1982 1983 VGE_LOCK_ASSERT(sc); 1984 mii = device_get_softc(sc->vge_miibus); 1985 1986 if ((ifp->if_drv_flags & IFF_DRV_RUNNING) != 0) 1987 return; 1988 1989 /* 1990 * Cancel pending I/O and free all RX/TX buffers. 1991 */ 1992 vge_stop(sc); 1993 vge_reset(sc); 1994 1995 /* 1996 * Initialize the RX and TX descriptors and mbufs. 1997 */ 1998 1999 error = vge_rx_list_init(sc); 2000 if (error != 0) { 2001 device_printf(sc->vge_dev, "no memory for Rx buffers.\n"); 2002 return; 2003 } 2004 vge_tx_list_init(sc); 2005 2006 /* Set our station address */ 2007 for (i = 0; i < ETHER_ADDR_LEN; i++) 2008 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 2009 2010 /* 2011 * Set receive FIFO threshold. Also allow transmission and 2012 * reception of VLAN tagged frames. 2013 */ 2014 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 2015 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 2016 2017 /* Set DMA burst length */ 2018 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 2019 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 2020 2021 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 2022 2023 /* Set collision backoff algorithm */ 2024 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 2025 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 2026 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 2027 2028 /* Disable LPSEL field in priority resolution */ 2029 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 2030 2031 /* 2032 * Load the addresses of the DMA queues into the chip. 2033 * Note that we only use one transmit queue. 2034 */ 2035 2036 CSR_WRITE_4(sc, VGE_TXDESC_HIADDR, 2037 VGE_ADDR_HI(sc->vge_rdata.vge_tx_ring_paddr)); 2038 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2039 VGE_ADDR_LO(sc->vge_rdata.vge_tx_ring_paddr)); 2040 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2041 2042 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2043 VGE_ADDR_LO(sc->vge_rdata.vge_rx_ring_paddr)); 2044 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2045 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2046 2047 /* Enable and wake up the RX descriptor queue */ 2048 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2049 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2050 2051 /* Enable the TX descriptor queue */ 2052 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2053 2054 /* Set up the receive filter -- allow large frames for VLANs. */ 2055 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2056 2057 /* If we want promiscuous mode, set the allframes bit. */ 2058 if (ifp->if_flags & IFF_PROMISC) { 2059 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2060 } 2061 2062 /* Set capture broadcast bit to capture broadcast frames. */ 2063 if (ifp->if_flags & IFF_BROADCAST) { 2064 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2065 } 2066 2067 /* Set multicast bit to capture multicast frames. */ 2068 if (ifp->if_flags & IFF_MULTICAST) { 2069 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2070 } 2071 2072 /* Init the cam filter. */ 2073 vge_cam_clear(sc); 2074 2075 /* Init the multicast filter. */ 2076 vge_setmulti(sc); 2077 2078 /* Enable flow control */ 2079 2080 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2081 2082 /* Enable jumbo frame reception (if desired) */ 2083 2084 /* Start the MAC. */ 2085 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2086 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2087 CSR_WRITE_1(sc, VGE_CRS0, 2088 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2089 2090 /* 2091 * Configure one-shot timer for microsecond 2092 * resolution and load it for 500 usecs. 2093 */ 2094 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2095 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2096 2097 /* 2098 * Configure interrupt moderation for receive. Enable 2099 * the holdoff counter and load it, and set the RX 2100 * suppression count to the number of descriptors we 2101 * want to allow before triggering an interrupt. 2102 * The holdoff timer is in units of 20 usecs. 2103 */ 2104 2105#ifdef notyet 2106 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2107 /* Select the interrupt holdoff timer page. */ 2108 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2109 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2110 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2111 2112 /* Enable use of the holdoff timer. */ 2113 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2114 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2115 2116 /* Select the RX suppression threshold page. */ 2117 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2118 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2119 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2120 2121 /* Restore the page select bits. */ 2122 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2123 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2124#endif 2125 2126#ifdef DEVICE_POLLING 2127 /* 2128 * Disable interrupts if we are polling. 2129 */ 2130 if (ifp->if_capenable & IFCAP_POLLING) { 2131 CSR_WRITE_4(sc, VGE_IMR, 0); 2132 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2133 } else /* otherwise ... */ 2134#endif 2135 { 2136 /* 2137 * Enable interrupts. 2138 */ 2139 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2140 CSR_WRITE_4(sc, VGE_ISR, 0); 2141 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2142 } 2143 2144 sc->vge_flags &= ~VGE_FLAG_LINK; 2145 mii_mediachg(mii); 2146 2147 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2148 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2149 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2150} 2151 2152/* 2153 * Set media options. 2154 */ 2155static int 2156vge_ifmedia_upd(struct ifnet *ifp) 2157{ 2158 struct vge_softc *sc; 2159 struct mii_data *mii; 2160 2161 sc = ifp->if_softc; 2162 VGE_LOCK(sc); 2163 mii = device_get_softc(sc->vge_miibus); 2164 mii_mediachg(mii); 2165 VGE_UNLOCK(sc); 2166 2167 return (0); 2168} 2169 2170/* 2171 * Report current media status. 2172 */ 2173static void 2174vge_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 2175{ 2176 struct vge_softc *sc; 2177 struct mii_data *mii; 2178 2179 sc = ifp->if_softc; 2180 mii = device_get_softc(sc->vge_miibus); 2181 2182 VGE_LOCK(sc); 2183 mii_pollstat(mii); 2184 VGE_UNLOCK(sc); 2185 ifmr->ifm_active = mii->mii_media_active; 2186 ifmr->ifm_status = mii->mii_media_status; 2187} 2188 2189static void 2190vge_miibus_statchg(device_t dev) 2191{ 2192 struct vge_softc *sc; 2193 struct mii_data *mii; 2194 struct ifmedia_entry *ife; 2195 2196 sc = device_get_softc(dev); 2197 mii = device_get_softc(sc->vge_miibus); 2198 ife = mii->mii_media.ifm_cur; 2199 2200 /* 2201 * If the user manually selects a media mode, we need to turn 2202 * on the forced MAC mode bit in the DIAGCTL register. If the 2203 * user happens to choose a full duplex mode, we also need to 2204 * set the 'force full duplex' bit. This applies only to 2205 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2206 * mode is disabled, and in 1000baseT mode, full duplex is 2207 * always implied, so we turn on the forced mode bit but leave 2208 * the FDX bit cleared. 2209 */ 2210 2211 switch (IFM_SUBTYPE(ife->ifm_media)) { 2212 case IFM_AUTO: 2213 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2214 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2215 break; 2216 case IFM_1000_T: 2217 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2218 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2219 break; 2220 case IFM_100_TX: 2221 case IFM_10_T: 2222 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2223 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2224 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2225 } else { 2226 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2227 } 2228 break; 2229 default: 2230 device_printf(dev, "unknown media type: %x\n", 2231 IFM_SUBTYPE(ife->ifm_media)); 2232 break; 2233 } 2234} 2235 2236static int 2237vge_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2238{ 2239 struct vge_softc *sc = ifp->if_softc; 2240 struct ifreq *ifr = (struct ifreq *) data; 2241 struct mii_data *mii; 2242 int error = 0; 2243 2244 switch (command) { 2245 case SIOCSIFMTU: 2246 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2247 error = EINVAL; 2248 ifp->if_mtu = ifr->ifr_mtu; 2249 break; 2250 case SIOCSIFFLAGS: 2251 VGE_LOCK(sc); 2252 if (ifp->if_flags & IFF_UP) { 2253 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2254 ifp->if_flags & IFF_PROMISC && 2255 !(sc->vge_if_flags & IFF_PROMISC)) { 2256 CSR_SETBIT_1(sc, VGE_RXCTL, 2257 VGE_RXCTL_RX_PROMISC); 2258 vge_setmulti(sc); 2259 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2260 !(ifp->if_flags & IFF_PROMISC) && 2261 sc->vge_if_flags & IFF_PROMISC) { 2262 CSR_CLRBIT_1(sc, VGE_RXCTL, 2263 VGE_RXCTL_RX_PROMISC); 2264 vge_setmulti(sc); 2265 } else 2266 vge_init_locked(sc); 2267 } else { 2268 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2269 vge_stop(sc); 2270 } 2271 sc->vge_if_flags = ifp->if_flags; 2272 VGE_UNLOCK(sc); 2273 break; 2274 case SIOCADDMULTI: 2275 case SIOCDELMULTI: 2276 VGE_LOCK(sc); 2277 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2278 vge_setmulti(sc); 2279 VGE_UNLOCK(sc); 2280 break; 2281 case SIOCGIFMEDIA: 2282 case SIOCSIFMEDIA: 2283 mii = device_get_softc(sc->vge_miibus); 2284 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2285 break; 2286 case SIOCSIFCAP: 2287 { 2288 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2289#ifdef DEVICE_POLLING 2290 if (mask & IFCAP_POLLING) { 2291 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2292 error = ether_poll_register(vge_poll, ifp); 2293 if (error) 2294 return (error); 2295 VGE_LOCK(sc); 2296 /* Disable interrupts */ 2297 CSR_WRITE_4(sc, VGE_IMR, 0); 2298 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2299 ifp->if_capenable |= IFCAP_POLLING; 2300 VGE_UNLOCK(sc); 2301 } else { 2302 error = ether_poll_deregister(ifp); 2303 /* Enable interrupts. */ 2304 VGE_LOCK(sc); 2305 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2306 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2307 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2308 ifp->if_capenable &= ~IFCAP_POLLING; 2309 VGE_UNLOCK(sc); 2310 } 2311 } 2312#endif /* DEVICE_POLLING */ 2313 VGE_LOCK(sc); 2314 if ((mask & IFCAP_TXCSUM) != 0 && 2315 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2316 ifp->if_capenable ^= IFCAP_TXCSUM; 2317 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2318 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2319 else 2320 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2321 } 2322 if ((mask & IFCAP_RXCSUM) != 0 && 2323 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2324 ifp->if_capenable ^= IFCAP_RXCSUM; 2325 VGE_UNLOCK(sc); 2326 } 2327 break; 2328 default: 2329 error = ether_ioctl(ifp, command, data); 2330 break; 2331 } 2332 2333 return (error); 2334} 2335 2336static void 2337vge_watchdog(void *arg) 2338{ 2339 struct vge_softc *sc; 2340 struct ifnet *ifp; 2341 2342 sc = arg; 2343 VGE_LOCK_ASSERT(sc); 2344 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2345 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2346 return; 2347 2348 ifp = sc->vge_ifp; 2349 if_printf(ifp, "watchdog timeout\n"); 2350 ifp->if_oerrors++; 2351 2352 vge_txeof(sc); 2353 vge_rxeof(sc, VGE_RX_DESC_CNT); 2354 2355 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2356 vge_init_locked(sc); 2357} 2358 2359/* 2360 * Stop the adapter and free any mbufs allocated to the 2361 * RX and TX lists. 2362 */ 2363static void 2364vge_stop(struct vge_softc *sc) 2365{ 2366 struct ifnet *ifp; 2367 2368 VGE_LOCK_ASSERT(sc); 2369 ifp = sc->vge_ifp; 2370 sc->vge_timer = 0; 2371 callout_stop(&sc->vge_watchdog); 2372 2373 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2374 2375 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2376 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2377 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2378 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2379 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2380 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2381 2382 VGE_CHAIN_RESET(sc); 2383 vge_txeof(sc); 2384 vge_freebufs(sc); 2385} 2386 2387/* 2388 * Device suspend routine. Stop the interface and save some PCI 2389 * settings in case the BIOS doesn't restore them properly on 2390 * resume. 2391 */ 2392static int 2393vge_suspend(device_t dev) 2394{ 2395 struct vge_softc *sc; 2396 2397 sc = device_get_softc(dev); 2398 2399 VGE_LOCK(sc); 2400 vge_stop(sc); 2401 2402 sc->suspended = 1; 2403 VGE_UNLOCK(sc); 2404 2405 return (0); 2406} 2407 2408/* 2409 * Device resume routine. Restore some PCI settings in case the BIOS 2410 * doesn't, re-enable busmastering, and restart the interface if 2411 * appropriate. 2412 */ 2413static int 2414vge_resume(device_t dev) 2415{ 2416 struct vge_softc *sc; 2417 struct ifnet *ifp; 2418 2419 sc = device_get_softc(dev); 2420 ifp = sc->vge_ifp; 2421 2422 /* reenable busmastering */ 2423 pci_enable_busmaster(dev); 2424 pci_enable_io(dev, SYS_RES_MEMORY); 2425 2426 /* reinitialize interface if necessary */ 2427 VGE_LOCK(sc); 2428 if (ifp->if_flags & IFF_UP) { 2429 ifp->if_drv_flags &= ~IFF_DRV_RUNNING; 2430 vge_init_locked(sc); 2431 } 2432 sc->suspended = 0; 2433 VGE_UNLOCK(sc); 2434 2435 return (0); 2436} 2437 2438/* 2439 * Stop all chip I/O so that the kernel's probe routines don't 2440 * get confused by errant DMAs when rebooting. 2441 */ 2442static int 2443vge_shutdown(device_t dev) 2444{ 2445 struct vge_softc *sc; 2446 2447 sc = device_get_softc(dev); 2448 2449 VGE_LOCK(sc); 2450 vge_stop(sc); 2451 VGE_UNLOCK(sc); 2452 2453 return (0); 2454} 2455