if_vge.c revision 200519
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 200519 2009-12-14 17:53:10Z yongari $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96 97#include <net/if.h> 98#include <net/if_arp.h> 99#include <net/ethernet.h> 100#include <net/if_dl.h> 101#include <net/if_media.h> 102#include <net/if_types.h> 103#include <net/if_vlan_var.h> 104 105#include <net/bpf.h> 106 107#include <machine/bus.h> 108#include <machine/resource.h> 109#include <sys/bus.h> 110#include <sys/rman.h> 111 112#include <dev/mii/mii.h> 113#include <dev/mii/miivar.h> 114 115#include <dev/pci/pcireg.h> 116#include <dev/pci/pcivar.h> 117 118MODULE_DEPEND(vge, pci, 1, 1, 1); 119MODULE_DEPEND(vge, ether, 1, 1, 1); 120MODULE_DEPEND(vge, miibus, 1, 1, 1); 121 122/* "device miibus" required. See GENERIC if you get errors here. */ 123#include "miibus_if.h" 124 125#include <dev/vge/if_vgereg.h> 126#include <dev/vge/if_vgevar.h> 127 128#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 129 130/* 131 * Various supported device vendors/types and their names. 132 */ 133static struct vge_type vge_devs[] = { 134 { VIA_VENDORID, VIA_DEVICEID_61XX, 135 "VIA Networking Gigabit Ethernet" }, 136 { 0, 0, NULL } 137}; 138 139static int vge_probe (device_t); 140static int vge_attach (device_t); 141static int vge_detach (device_t); 142 143static int vge_encap (struct vge_softc *, struct mbuf *, int); 144 145static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 146static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 147 bus_size_t, int); 148static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 149 bus_size_t, int); 150static int vge_allocmem (device_t, struct vge_softc *); 151static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 152static int vge_rx_list_init (struct vge_softc *); 153static int vge_tx_list_init (struct vge_softc *); 154#ifdef VGE_FIXUP_RX 155static __inline void vge_fixup_rx 156 (struct mbuf *); 157#endif 158static int vge_rxeof (struct vge_softc *); 159static void vge_txeof (struct vge_softc *); 160static void vge_intr (void *); 161static void vge_tick (void *); 162static void vge_start (struct ifnet *); 163static void vge_start_locked (struct ifnet *); 164static int vge_ioctl (struct ifnet *, u_long, caddr_t); 165static void vge_init (void *); 166static void vge_init_locked (struct vge_softc *); 167static void vge_stop (struct vge_softc *); 168static void vge_watchdog (void *); 169static int vge_suspend (device_t); 170static int vge_resume (device_t); 171static int vge_shutdown (device_t); 172static int vge_ifmedia_upd (struct ifnet *); 173static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174 175#ifdef VGE_EEPROM 176static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177#endif 178static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179 180static void vge_miipoll_start (struct vge_softc *); 181static void vge_miipoll_stop (struct vge_softc *); 182static int vge_miibus_readreg (device_t, int, int); 183static int vge_miibus_writereg (device_t, int, int, int); 184static void vge_miibus_statchg (device_t); 185 186static void vge_cam_clear (struct vge_softc *); 187static int vge_cam_set (struct vge_softc *, uint8_t *); 188static void vge_setmulti (struct vge_softc *); 189static void vge_reset (struct vge_softc *); 190 191#define VGE_PCI_LOIO 0x10 192#define VGE_PCI_LOMEM 0x14 193 194static device_method_t vge_methods[] = { 195 /* Device interface */ 196 DEVMETHOD(device_probe, vge_probe), 197 DEVMETHOD(device_attach, vge_attach), 198 DEVMETHOD(device_detach, vge_detach), 199 DEVMETHOD(device_suspend, vge_suspend), 200 DEVMETHOD(device_resume, vge_resume), 201 DEVMETHOD(device_shutdown, vge_shutdown), 202 203 /* bus interface */ 204 DEVMETHOD(bus_print_child, bus_generic_print_child), 205 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 206 207 /* MII interface */ 208 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 209 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 210 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 211 212 { 0, 0 } 213}; 214 215static driver_t vge_driver = { 216 "vge", 217 vge_methods, 218 sizeof(struct vge_softc) 219}; 220 221static devclass_t vge_devclass; 222 223DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 224DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 225 226#ifdef VGE_EEPROM 227/* 228 * Read a word of data stored in the EEPROM at address 'addr.' 229 */ 230static void 231vge_eeprom_getword(sc, addr, dest) 232 struct vge_softc *sc; 233 int addr; 234 u_int16_t *dest; 235{ 236 int i; 237 u_int16_t word = 0; 238 239 /* 240 * Enter EEPROM embedded programming mode. In order to 241 * access the EEPROM at all, we first have to set the 242 * EELOAD bit in the CHIPCFG2 register. 243 */ 244 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 245 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 246 247 /* Select the address of the word we want to read */ 248 CSR_WRITE_1(sc, VGE_EEADDR, addr); 249 250 /* Issue read command */ 251 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 252 253 /* Wait for the done bit to be set. */ 254 for (i = 0; i < VGE_TIMEOUT; i++) { 255 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 256 break; 257 } 258 259 if (i == VGE_TIMEOUT) { 260 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 261 *dest = 0; 262 return; 263 } 264 265 /* Read the result */ 266 word = CSR_READ_2(sc, VGE_EERDDAT); 267 268 /* Turn off EEPROM access mode. */ 269 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 270 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 271 272 *dest = word; 273 274 return; 275} 276#endif 277 278/* 279 * Read a sequence of words from the EEPROM. 280 */ 281static void 282vge_read_eeprom(sc, dest, off, cnt, swap) 283 struct vge_softc *sc; 284 caddr_t dest; 285 int off; 286 int cnt; 287 int swap; 288{ 289 int i; 290#ifdef VGE_EEPROM 291 u_int16_t word = 0, *ptr; 292 293 for (i = 0; i < cnt; i++) { 294 vge_eeprom_getword(sc, off + i, &word); 295 ptr = (u_int16_t *)(dest + (i * 2)); 296 if (swap) 297 *ptr = ntohs(word); 298 else 299 *ptr = word; 300 } 301#else 302 for (i = 0; i < ETHER_ADDR_LEN; i++) 303 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 304#endif 305} 306 307static void 308vge_miipoll_stop(sc) 309 struct vge_softc *sc; 310{ 311 int i; 312 313 CSR_WRITE_1(sc, VGE_MIICMD, 0); 314 315 for (i = 0; i < VGE_TIMEOUT; i++) { 316 DELAY(1); 317 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 318 break; 319 } 320 321 if (i == VGE_TIMEOUT) 322 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 323 324 return; 325} 326 327static void 328vge_miipoll_start(sc) 329 struct vge_softc *sc; 330{ 331 int i; 332 333 /* First, make sure we're idle. */ 334 335 CSR_WRITE_1(sc, VGE_MIICMD, 0); 336 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 337 338 for (i = 0; i < VGE_TIMEOUT; i++) { 339 DELAY(1); 340 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 341 break; 342 } 343 344 if (i == VGE_TIMEOUT) { 345 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 346 return; 347 } 348 349 /* Now enable auto poll mode. */ 350 351 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 352 353 /* And make sure it started. */ 354 355 for (i = 0; i < VGE_TIMEOUT; i++) { 356 DELAY(1); 357 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 358 break; 359 } 360 361 if (i == VGE_TIMEOUT) 362 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 363 364 return; 365} 366 367static int 368vge_miibus_readreg(dev, phy, reg) 369 device_t dev; 370 int phy, reg; 371{ 372 struct vge_softc *sc; 373 int i; 374 u_int16_t rval = 0; 375 376 sc = device_get_softc(dev); 377 378 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 379 return(0); 380 381 vge_miipoll_stop(sc); 382 383 /* Specify the register we want to read. */ 384 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 385 386 /* Issue read command. */ 387 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 388 389 /* Wait for the read command bit to self-clear. */ 390 for (i = 0; i < VGE_TIMEOUT; i++) { 391 DELAY(1); 392 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 393 break; 394 } 395 396 if (i == VGE_TIMEOUT) 397 device_printf(sc->vge_dev, "MII read timed out\n"); 398 else 399 rval = CSR_READ_2(sc, VGE_MIIDATA); 400 401 vge_miipoll_start(sc); 402 403 return (rval); 404} 405 406static int 407vge_miibus_writereg(dev, phy, reg, data) 408 device_t dev; 409 int phy, reg, data; 410{ 411 struct vge_softc *sc; 412 int i, rval = 0; 413 414 sc = device_get_softc(dev); 415 416 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 417 return(0); 418 419 vge_miipoll_stop(sc); 420 421 /* Specify the register we want to write. */ 422 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 423 424 /* Specify the data we want to write. */ 425 CSR_WRITE_2(sc, VGE_MIIDATA, data); 426 427 /* Issue write command. */ 428 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 429 430 /* Wait for the write command bit to self-clear. */ 431 for (i = 0; i < VGE_TIMEOUT; i++) { 432 DELAY(1); 433 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 434 break; 435 } 436 437 if (i == VGE_TIMEOUT) { 438 device_printf(sc->vge_dev, "MII write timed out\n"); 439 rval = EIO; 440 } 441 442 vge_miipoll_start(sc); 443 444 return (rval); 445} 446 447static void 448vge_cam_clear(sc) 449 struct vge_softc *sc; 450{ 451 int i; 452 453 /* 454 * Turn off all the mask bits. This tells the chip 455 * that none of the entries in the CAM filter are valid. 456 * desired entries will be enabled as we fill the filter in. 457 */ 458 459 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 460 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 461 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 462 for (i = 0; i < 8; i++) 463 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 464 465 /* Clear the VLAN filter too. */ 466 467 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 468 for (i = 0; i < 8; i++) 469 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 470 471 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 472 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 473 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 474 475 sc->vge_camidx = 0; 476 477 return; 478} 479 480static int 481vge_cam_set(sc, addr) 482 struct vge_softc *sc; 483 uint8_t *addr; 484{ 485 int i, error = 0; 486 487 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 488 return(ENOSPC); 489 490 /* Select the CAM data page. */ 491 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 492 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 493 494 /* Set the filter entry we want to update and enable writing. */ 495 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 496 497 /* Write the address to the CAM registers */ 498 for (i = 0; i < ETHER_ADDR_LEN; i++) 499 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 500 501 /* Issue a write command. */ 502 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 503 504 /* Wake for it to clear. */ 505 for (i = 0; i < VGE_TIMEOUT; i++) { 506 DELAY(1); 507 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 508 break; 509 } 510 511 if (i == VGE_TIMEOUT) { 512 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 513 error = EIO; 514 goto fail; 515 } 516 517 /* Select the CAM mask page. */ 518 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 519 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 520 521 /* Set the mask bit that enables this filter. */ 522 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 523 1<<(sc->vge_camidx & 7)); 524 525 sc->vge_camidx++; 526 527fail: 528 /* Turn off access to CAM. */ 529 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 530 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 531 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 532 533 return (error); 534} 535 536/* 537 * Program the multicast filter. We use the 64-entry CAM filter 538 * for perfect filtering. If there's more than 64 multicast addresses, 539 * we use the hash filter insted. 540 */ 541static void 542vge_setmulti(sc) 543 struct vge_softc *sc; 544{ 545 struct ifnet *ifp; 546 int error = 0/*, h = 0*/; 547 struct ifmultiaddr *ifma; 548 u_int32_t h, hashes[2] = { 0, 0 }; 549 550 ifp = sc->vge_ifp; 551 552 /* First, zot all the multicast entries. */ 553 vge_cam_clear(sc); 554 CSR_WRITE_4(sc, VGE_MAR0, 0); 555 CSR_WRITE_4(sc, VGE_MAR1, 0); 556 557 /* 558 * If the user wants allmulti or promisc mode, enable reception 559 * of all multicast frames. 560 */ 561 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 562 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 563 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 564 return; 565 } 566 567 /* Now program new ones */ 568 if_maddr_rlock(ifp); 569 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 570 if (ifma->ifma_addr->sa_family != AF_LINK) 571 continue; 572 error = vge_cam_set(sc, 573 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 574 if (error) 575 break; 576 } 577 578 /* If there were too many addresses, use the hash filter. */ 579 if (error) { 580 vge_cam_clear(sc); 581 582 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 583 if (ifma->ifma_addr->sa_family != AF_LINK) 584 continue; 585 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 586 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 587 if (h < 32) 588 hashes[0] |= (1 << h); 589 else 590 hashes[1] |= (1 << (h - 32)); 591 } 592 593 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 594 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 595 } 596 if_maddr_runlock(ifp); 597 598 return; 599} 600 601static void 602vge_reset(sc) 603 struct vge_softc *sc; 604{ 605 int i; 606 607 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 608 609 for (i = 0; i < VGE_TIMEOUT; i++) { 610 DELAY(5); 611 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 612 break; 613 } 614 615 if (i == VGE_TIMEOUT) { 616 device_printf(sc->vge_dev, "soft reset timed out"); 617 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 618 DELAY(2000); 619 } 620 621 DELAY(5000); 622 623 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 624 625 for (i = 0; i < VGE_TIMEOUT; i++) { 626 DELAY(5); 627 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 628 break; 629 } 630 631 if (i == VGE_TIMEOUT) { 632 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 633 return; 634 } 635 636 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 637 638 return; 639} 640 641/* 642 * Probe for a VIA gigabit chip. Check the PCI vendor and device 643 * IDs against our list and return a device name if we find a match. 644 */ 645static int 646vge_probe(dev) 647 device_t dev; 648{ 649 struct vge_type *t; 650 651 t = vge_devs; 652 653 while (t->vge_name != NULL) { 654 if ((pci_get_vendor(dev) == t->vge_vid) && 655 (pci_get_device(dev) == t->vge_did)) { 656 device_set_desc(dev, t->vge_name); 657 return (BUS_PROBE_DEFAULT); 658 } 659 t++; 660 } 661 662 return (ENXIO); 663} 664 665static void 666vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 667 void *arg; 668 bus_dma_segment_t *segs; 669 int nseg; 670 bus_size_t mapsize; 671 int error; 672{ 673 674 struct vge_dmaload_arg *ctx; 675 struct vge_rx_desc *d = NULL; 676 677 if (error) 678 return; 679 680 ctx = arg; 681 682 /* Signal error to caller if there's too many segments */ 683 if (nseg > ctx->vge_maxsegs) { 684 ctx->vge_maxsegs = 0; 685 return; 686 } 687 688 /* 689 * Map the segment array into descriptors. 690 */ 691 692 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 693 694 /* If this descriptor is still owned by the chip, bail. */ 695 696 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 697 device_printf(ctx->sc->vge_dev, 698 "tried to map busy descriptor\n"); 699 ctx->vge_maxsegs = 0; 700 return; 701 } 702 703 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 704 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 705 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 706 d->vge_sts = 0; 707 d->vge_ctl = 0; 708 709 ctx->vge_maxsegs = 1; 710 711 return; 712} 713 714static void 715vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 716 void *arg; 717 bus_dma_segment_t *segs; 718 int nseg; 719 bus_size_t mapsize; 720 int error; 721{ 722 struct vge_dmaload_arg *ctx; 723 struct vge_tx_desc *d = NULL; 724 struct vge_tx_frag *f; 725 int i = 0; 726 727 if (error) 728 return; 729 730 ctx = arg; 731 732 /* Signal error to caller if there's too many segments */ 733 if (nseg > ctx->vge_maxsegs) { 734 ctx->vge_maxsegs = 0; 735 return; 736 } 737 738 /* Map the segment array into descriptors. */ 739 740 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 741 742 /* If this descriptor is still owned by the chip, bail. */ 743 744 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 745 ctx->vge_maxsegs = 0; 746 return; 747 } 748 749 for (i = 0; i < nseg; i++) { 750 f = &d->vge_frag[i]; 751 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 752 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 753 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 754 } 755 756 /* Argh. This chip does not autopad short frames */ 757 758 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 759 f = &d->vge_frag[i]; 760 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 761 ctx->vge_m0->m_pkthdr.len)); 762 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 763 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 764 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 765 i++; 766 } 767 768 /* 769 * When telling the chip how many segments there are, we 770 * must use nsegs + 1 instead of just nsegs. Darned if I 771 * know why. 772 */ 773 i++; 774 775 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 776 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 777 778 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 779 d->vge_ctl |= VGE_TDCTL_JUMBO; 780 781 ctx->vge_maxsegs = nseg; 782 783 return; 784} 785 786/* 787 * Map a single buffer address. 788 */ 789 790static void 791vge_dma_map_addr(arg, segs, nseg, error) 792 void *arg; 793 bus_dma_segment_t *segs; 794 int nseg; 795 int error; 796{ 797 bus_addr_t *addr; 798 799 if (error) 800 return; 801 802 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 803 addr = arg; 804 *addr = segs->ds_addr; 805 806 return; 807} 808 809static int 810vge_allocmem(dev, sc) 811 device_t dev; 812 struct vge_softc *sc; 813{ 814 int error; 815 int nseg; 816 int i; 817 818 /* 819 * Allocate map for RX mbufs. 820 */ 821 nseg = 32; 822 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 823 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 824 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 825 NULL, NULL, &sc->vge_ldata.vge_mtag); 826 if (error) { 827 device_printf(dev, "could not allocate dma tag\n"); 828 return (ENOMEM); 829 } 830 831 /* 832 * Allocate map for TX descriptor list. 833 */ 834 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 835 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 836 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 837 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 838 if (error) { 839 device_printf(dev, "could not allocate dma tag\n"); 840 return (ENOMEM); 841 } 842 843 /* Allocate DMA'able memory for the TX ring */ 844 845 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 846 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 847 &sc->vge_ldata.vge_tx_list_map); 848 if (error) 849 return (ENOMEM); 850 851 /* Load the map for the TX ring. */ 852 853 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 854 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 855 VGE_TX_LIST_SZ, vge_dma_map_addr, 856 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 857 858 /* Create DMA maps for TX buffers */ 859 860 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 861 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 862 &sc->vge_ldata.vge_tx_dmamap[i]); 863 if (error) { 864 device_printf(dev, "can't create DMA map for TX\n"); 865 return (ENOMEM); 866 } 867 } 868 869 /* 870 * Allocate map for RX descriptor list. 871 */ 872 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 873 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 874 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 875 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 876 if (error) { 877 device_printf(dev, "could not allocate dma tag\n"); 878 return (ENOMEM); 879 } 880 881 /* Allocate DMA'able memory for the RX ring */ 882 883 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 884 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 885 &sc->vge_ldata.vge_rx_list_map); 886 if (error) 887 return (ENOMEM); 888 889 /* Load the map for the RX ring. */ 890 891 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 892 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 893 VGE_TX_LIST_SZ, vge_dma_map_addr, 894 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 895 896 /* Create DMA maps for RX buffers */ 897 898 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 899 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 900 &sc->vge_ldata.vge_rx_dmamap[i]); 901 if (error) { 902 device_printf(dev, "can't create DMA map for RX\n"); 903 return (ENOMEM); 904 } 905 } 906 907 return (0); 908} 909 910/* 911 * Attach the interface. Allocate softc structures, do ifmedia 912 * setup and ethernet/BPF attach. 913 */ 914static int 915vge_attach(dev) 916 device_t dev; 917{ 918 u_char eaddr[ETHER_ADDR_LEN]; 919 struct vge_softc *sc; 920 struct ifnet *ifp; 921 int unit, error = 0, rid; 922 923 sc = device_get_softc(dev); 924 unit = device_get_unit(dev); 925 sc->vge_dev = dev; 926 927 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 928 MTX_DEF); 929 callout_init_mtx(&sc->vge_watchdog, &sc->vge_mtx, 0); 930 931 /* 932 * Map control/status registers. 933 */ 934 pci_enable_busmaster(dev); 935 936 rid = VGE_PCI_LOMEM; 937 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 938 0, ~0, 1, RF_ACTIVE); 939 940 if (sc->vge_res == NULL) { 941 printf ("vge%d: couldn't map ports/memory\n", unit); 942 error = ENXIO; 943 goto fail; 944 } 945 946 /* Allocate interrupt */ 947 rid = 0; 948 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 949 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 950 951 if (sc->vge_irq == NULL) { 952 printf("vge%d: couldn't map interrupt\n", unit); 953 error = ENXIO; 954 goto fail; 955 } 956 957 /* Reset the adapter. */ 958 vge_reset(sc); 959 960 /* 961 * Get station address from the EEPROM. 962 */ 963 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 964 965 /* 966 * Allocate the parent bus DMA tag appropriate for PCI. 967 */ 968#define VGE_NSEG_NEW 32 969 error = bus_dma_tag_create(NULL, /* parent */ 970 1, 0, /* alignment, boundary */ 971 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 972 BUS_SPACE_MAXADDR, /* highaddr */ 973 NULL, NULL, /* filter, filterarg */ 974 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 975 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 976 BUS_DMA_ALLOCNOW, /* flags */ 977 NULL, NULL, /* lockfunc, lockarg */ 978 &sc->vge_parent_tag); 979 if (error) 980 goto fail; 981 982 error = vge_allocmem(dev, sc); 983 984 if (error) 985 goto fail; 986 987 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 988 if (ifp == NULL) { 989 device_printf(dev, "can not if_alloc()\n"); 990 error = ENOSPC; 991 goto fail; 992 } 993 994 /* Do MII setup */ 995 if (mii_phy_probe(dev, &sc->vge_miibus, 996 vge_ifmedia_upd, vge_ifmedia_sts)) { 997 device_printf(dev, "MII without any phy!\n"); 998 error = ENXIO; 999 goto fail; 1000 } 1001 1002 ifp->if_softc = sc; 1003 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1004 ifp->if_mtu = ETHERMTU; 1005 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1006 ifp->if_ioctl = vge_ioctl; 1007 ifp->if_capabilities = IFCAP_VLAN_MTU; 1008 ifp->if_start = vge_start; 1009 ifp->if_hwassist = VGE_CSUM_FEATURES; 1010 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1011 ifp->if_capenable = ifp->if_capabilities; 1012#ifdef DEVICE_POLLING 1013 ifp->if_capabilities |= IFCAP_POLLING; 1014#endif 1015 ifp->if_init = vge_init; 1016 IFQ_SET_MAXLEN(&ifp->if_snd, VGE_IFQ_MAXLEN); 1017 ifp->if_snd.ifq_drv_maxlen = VGE_IFQ_MAXLEN; 1018 IFQ_SET_READY(&ifp->if_snd); 1019 1020 /* 1021 * Call MI attach routine. 1022 */ 1023 ether_ifattach(ifp, eaddr); 1024 1025 /* Hook interrupt last to avoid having to lock softc */ 1026 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1027 NULL, vge_intr, sc, &sc->vge_intrhand); 1028 1029 if (error) { 1030 printf("vge%d: couldn't set up irq\n", unit); 1031 ether_ifdetach(ifp); 1032 goto fail; 1033 } 1034 1035fail: 1036 if (error) 1037 vge_detach(dev); 1038 1039 return (error); 1040} 1041 1042/* 1043 * Shutdown hardware and free up resources. This can be called any 1044 * time after the mutex has been initialized. It is called in both 1045 * the error case in attach and the normal detach case so it needs 1046 * to be careful about only freeing resources that have actually been 1047 * allocated. 1048 */ 1049static int 1050vge_detach(dev) 1051 device_t dev; 1052{ 1053 struct vge_softc *sc; 1054 struct ifnet *ifp; 1055 int i; 1056 1057 sc = device_get_softc(dev); 1058 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1059 ifp = sc->vge_ifp; 1060 1061#ifdef DEVICE_POLLING 1062 if (ifp->if_capenable & IFCAP_POLLING) 1063 ether_poll_deregister(ifp); 1064#endif 1065 1066 /* These should only be active if attach succeeded */ 1067 if (device_is_attached(dev)) { 1068 ether_ifdetach(ifp); 1069 VGE_LOCK(sc); 1070 vge_stop(sc); 1071 VGE_UNLOCK(sc); 1072 callout_drain(&sc->vge_watchdog); 1073 } 1074 if (sc->vge_miibus) 1075 device_delete_child(dev, sc->vge_miibus); 1076 bus_generic_detach(dev); 1077 1078 if (sc->vge_intrhand) 1079 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1080 if (sc->vge_irq) 1081 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1082 if (sc->vge_res) 1083 bus_release_resource(dev, SYS_RES_MEMORY, 1084 VGE_PCI_LOMEM, sc->vge_res); 1085 if (ifp) 1086 if_free(ifp); 1087 1088 /* Unload and free the RX DMA ring memory and map */ 1089 1090 if (sc->vge_ldata.vge_rx_list_tag) { 1091 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1092 sc->vge_ldata.vge_rx_list_map); 1093 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1094 sc->vge_ldata.vge_rx_list, 1095 sc->vge_ldata.vge_rx_list_map); 1096 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1097 } 1098 1099 /* Unload and free the TX DMA ring memory and map */ 1100 1101 if (sc->vge_ldata.vge_tx_list_tag) { 1102 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1103 sc->vge_ldata.vge_tx_list_map); 1104 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1105 sc->vge_ldata.vge_tx_list, 1106 sc->vge_ldata.vge_tx_list_map); 1107 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1108 } 1109 1110 /* Destroy all the RX and TX buffer maps */ 1111 1112 if (sc->vge_ldata.vge_mtag) { 1113 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1114 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1115 sc->vge_ldata.vge_tx_dmamap[i]); 1116 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1117 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1118 sc->vge_ldata.vge_rx_dmamap[i]); 1119 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1120 } 1121 1122 if (sc->vge_parent_tag) 1123 bus_dma_tag_destroy(sc->vge_parent_tag); 1124 1125 mtx_destroy(&sc->vge_mtx); 1126 1127 return (0); 1128} 1129 1130static int 1131vge_newbuf(sc, idx, m) 1132 struct vge_softc *sc; 1133 int idx; 1134 struct mbuf *m; 1135{ 1136 struct vge_dmaload_arg arg; 1137 struct mbuf *n = NULL; 1138 int i, error; 1139 1140 if (m == NULL) { 1141 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1142 if (n == NULL) 1143 return (ENOBUFS); 1144 m = n; 1145 } else 1146 m->m_data = m->m_ext.ext_buf; 1147 1148 1149#ifdef VGE_FIXUP_RX 1150 /* 1151 * This is part of an evil trick to deal with non-x86 platforms. 1152 * The VIA chip requires RX buffers to be aligned on 32-bit 1153 * boundaries, but that will hose non-x86 machines. To get around 1154 * this, we leave some empty space at the start of each buffer 1155 * and for non-x86 hosts, we copy the buffer back two bytes 1156 * to achieve word alignment. This is slightly more efficient 1157 * than allocating a new buffer, copying the contents, and 1158 * discarding the old buffer. 1159 */ 1160 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1161 m_adj(m, VGE_ETHER_ALIGN); 1162#else 1163 m->m_len = m->m_pkthdr.len = MCLBYTES; 1164#endif 1165 1166 arg.sc = sc; 1167 arg.vge_idx = idx; 1168 arg.vge_maxsegs = 1; 1169 arg.vge_flags = 0; 1170 1171 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1172 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1173 &arg, BUS_DMA_NOWAIT); 1174 if (error || arg.vge_maxsegs != 1) { 1175 if (n != NULL) 1176 m_freem(n); 1177 return (ENOMEM); 1178 } 1179 1180 /* 1181 * Note: the manual fails to document the fact that for 1182 * proper opration, the driver needs to replentish the RX 1183 * DMA ring 4 descriptors at a time (rather than one at a 1184 * time, like most chips). We can allocate the new buffers 1185 * but we should not set the OWN bits until we're ready 1186 * to hand back 4 of them in one shot. 1187 */ 1188 1189#define VGE_RXCHUNK 4 1190 sc->vge_rx_consumed++; 1191 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1192 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1193 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1194 htole32(VGE_RDSTS_OWN); 1195 sc->vge_rx_consumed = 0; 1196 } 1197 1198 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1199 1200 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1201 sc->vge_ldata.vge_rx_dmamap[idx], 1202 BUS_DMASYNC_PREREAD); 1203 1204 return (0); 1205} 1206 1207static int 1208vge_tx_list_init(sc) 1209 struct vge_softc *sc; 1210{ 1211 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1212 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1213 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1214 1215 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1216 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1217 sc->vge_ldata.vge_tx_prodidx = 0; 1218 sc->vge_ldata.vge_tx_considx = 0; 1219 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1220 1221 return (0); 1222} 1223 1224static int 1225vge_rx_list_init(sc) 1226 struct vge_softc *sc; 1227{ 1228 int i; 1229 1230 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1231 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1232 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1233 1234 sc->vge_rx_consumed = 0; 1235 1236 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1237 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1238 return (ENOBUFS); 1239 } 1240 1241 /* Flush the RX descriptors */ 1242 1243 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1244 sc->vge_ldata.vge_rx_list_map, 1245 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1246 1247 sc->vge_ldata.vge_rx_prodidx = 0; 1248 sc->vge_rx_consumed = 0; 1249 sc->vge_head = sc->vge_tail = NULL; 1250 1251 return (0); 1252} 1253 1254#ifdef VGE_FIXUP_RX 1255static __inline void 1256vge_fixup_rx(m) 1257 struct mbuf *m; 1258{ 1259 int i; 1260 uint16_t *src, *dst; 1261 1262 src = mtod(m, uint16_t *); 1263 dst = src - 1; 1264 1265 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1266 *dst++ = *src++; 1267 1268 m->m_data -= ETHER_ALIGN; 1269 1270 return; 1271} 1272#endif 1273 1274/* 1275 * RX handler. We support the reception of jumbo frames that have 1276 * been fragmented across multiple 2K mbuf cluster buffers. 1277 */ 1278static int 1279vge_rxeof(sc) 1280 struct vge_softc *sc; 1281{ 1282 struct mbuf *m; 1283 struct ifnet *ifp; 1284 int i, total_len; 1285 int lim = 0; 1286 struct vge_rx_desc *cur_rx; 1287 u_int32_t rxstat, rxctl; 1288 1289 VGE_LOCK_ASSERT(sc); 1290 ifp = sc->vge_ifp; 1291 i = sc->vge_ldata.vge_rx_prodidx; 1292 1293 /* Invalidate the descriptor memory */ 1294 1295 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1296 sc->vge_ldata.vge_rx_list_map, 1297 BUS_DMASYNC_POSTREAD); 1298 1299 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1300 1301#ifdef DEVICE_POLLING 1302 if (ifp->if_capenable & IFCAP_POLLING) { 1303 if (sc->rxcycles <= 0) 1304 break; 1305 sc->rxcycles--; 1306 } 1307#endif 1308 1309 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1310 m = sc->vge_ldata.vge_rx_mbuf[i]; 1311 total_len = VGE_RXBYTES(cur_rx); 1312 rxstat = le32toh(cur_rx->vge_sts); 1313 rxctl = le32toh(cur_rx->vge_ctl); 1314 1315 /* Invalidate the RX mbuf and unload its map */ 1316 1317 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1318 sc->vge_ldata.vge_rx_dmamap[i], 1319 BUS_DMASYNC_POSTWRITE); 1320 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1321 sc->vge_ldata.vge_rx_dmamap[i]); 1322 1323 /* 1324 * If the 'start of frame' bit is set, this indicates 1325 * either the first fragment in a multi-fragment receive, 1326 * or an intermediate fragment. Either way, we want to 1327 * accumulate the buffers. 1328 */ 1329 if (rxstat & VGE_RXPKT_SOF) { 1330 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1331 if (sc->vge_head == NULL) 1332 sc->vge_head = sc->vge_tail = m; 1333 else { 1334 m->m_flags &= ~M_PKTHDR; 1335 sc->vge_tail->m_next = m; 1336 sc->vge_tail = m; 1337 } 1338 vge_newbuf(sc, i, NULL); 1339 VGE_RX_DESC_INC(i); 1340 continue; 1341 } 1342 1343 /* 1344 * Bad/error frames will have the RXOK bit cleared. 1345 * However, there's one error case we want to allow: 1346 * if a VLAN tagged frame arrives and the chip can't 1347 * match it against the CAM filter, it considers this 1348 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1349 * We don't want to drop the frame though: our VLAN 1350 * filtering is done in software. 1351 */ 1352 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1353 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1354 ifp->if_ierrors++; 1355 /* 1356 * If this is part of a multi-fragment packet, 1357 * discard all the pieces. 1358 */ 1359 if (sc->vge_head != NULL) { 1360 m_freem(sc->vge_head); 1361 sc->vge_head = sc->vge_tail = NULL; 1362 } 1363 vge_newbuf(sc, i, m); 1364 VGE_RX_DESC_INC(i); 1365 continue; 1366 } 1367 1368 /* 1369 * If allocating a replacement mbuf fails, 1370 * reload the current one. 1371 */ 1372 1373 if (vge_newbuf(sc, i, NULL)) { 1374 ifp->if_ierrors++; 1375 if (sc->vge_head != NULL) { 1376 m_freem(sc->vge_head); 1377 sc->vge_head = sc->vge_tail = NULL; 1378 } 1379 vge_newbuf(sc, i, m); 1380 VGE_RX_DESC_INC(i); 1381 continue; 1382 } 1383 1384 VGE_RX_DESC_INC(i); 1385 1386 if (sc->vge_head != NULL) { 1387 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1388 /* 1389 * Special case: if there's 4 bytes or less 1390 * in this buffer, the mbuf can be discarded: 1391 * the last 4 bytes is the CRC, which we don't 1392 * care about anyway. 1393 */ 1394 if (m->m_len <= ETHER_CRC_LEN) { 1395 sc->vge_tail->m_len -= 1396 (ETHER_CRC_LEN - m->m_len); 1397 m_freem(m); 1398 } else { 1399 m->m_len -= ETHER_CRC_LEN; 1400 m->m_flags &= ~M_PKTHDR; 1401 sc->vge_tail->m_next = m; 1402 } 1403 m = sc->vge_head; 1404 sc->vge_head = sc->vge_tail = NULL; 1405 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1406 } else 1407 m->m_pkthdr.len = m->m_len = 1408 (total_len - ETHER_CRC_LEN); 1409 1410#ifdef VGE_FIXUP_RX 1411 vge_fixup_rx(m); 1412#endif 1413 ifp->if_ipackets++; 1414 m->m_pkthdr.rcvif = ifp; 1415 1416 /* Do RX checksumming if enabled */ 1417 if (ifp->if_capenable & IFCAP_RXCSUM) { 1418 1419 /* Check IP header checksum */ 1420 if (rxctl & VGE_RDCTL_IPPKT) 1421 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1422 if (rxctl & VGE_RDCTL_IPCSUMOK) 1423 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1424 1425 /* Check TCP/UDP checksum */ 1426 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1427 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1428 m->m_pkthdr.csum_flags |= 1429 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1430 m->m_pkthdr.csum_data = 0xffff; 1431 } 1432 } 1433 1434 if (rxstat & VGE_RDSTS_VTAG) { 1435 /* 1436 * The 32-bit rxctl register is stored in little-endian. 1437 * However, the 16-bit vlan tag is stored in big-endian, 1438 * so we have to byte swap it. 1439 */ 1440 m->m_pkthdr.ether_vtag = 1441 bswap16(rxctl & VGE_RDCTL_VLANID); 1442 m->m_flags |= M_VLANTAG; 1443 } 1444 1445 VGE_UNLOCK(sc); 1446 (*ifp->if_input)(ifp, m); 1447 VGE_LOCK(sc); 1448 1449 lim++; 1450 if (lim == VGE_RX_DESC_CNT) 1451 break; 1452 1453 } 1454 1455 /* Flush the RX DMA ring */ 1456 1457 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1458 sc->vge_ldata.vge_rx_list_map, 1459 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1460 1461 sc->vge_ldata.vge_rx_prodidx = i; 1462 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1463 1464 1465 return (lim); 1466} 1467 1468static void 1469vge_txeof(sc) 1470 struct vge_softc *sc; 1471{ 1472 struct ifnet *ifp; 1473 u_int32_t txstat; 1474 int idx; 1475 1476 ifp = sc->vge_ifp; 1477 idx = sc->vge_ldata.vge_tx_considx; 1478 1479 /* Invalidate the TX descriptor list */ 1480 1481 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1482 sc->vge_ldata.vge_tx_list_map, 1483 BUS_DMASYNC_POSTREAD); 1484 1485 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1486 1487 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1488 if (txstat & VGE_TDSTS_OWN) 1489 break; 1490 1491 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1492 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1493 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1494 sc->vge_ldata.vge_tx_dmamap[idx]); 1495 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1496 ifp->if_collisions++; 1497 if (txstat & VGE_TDSTS_TXERR) 1498 ifp->if_oerrors++; 1499 else 1500 ifp->if_opackets++; 1501 1502 sc->vge_ldata.vge_tx_free++; 1503 VGE_TX_DESC_INC(idx); 1504 } 1505 1506 /* No changes made to the TX ring, so no flush needed */ 1507 1508 if (idx != sc->vge_ldata.vge_tx_considx) { 1509 sc->vge_ldata.vge_tx_considx = idx; 1510 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1511 sc->vge_timer = 0; 1512 } 1513 1514 /* 1515 * If not all descriptors have been released reaped yet, 1516 * reload the timer so that we will eventually get another 1517 * interrupt that will cause us to re-enter this routine. 1518 * This is done in case the transmitter has gone idle. 1519 */ 1520 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1521 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1522 } 1523 1524 return; 1525} 1526 1527static void 1528vge_tick(xsc) 1529 void *xsc; 1530{ 1531 struct vge_softc *sc; 1532 struct ifnet *ifp; 1533 struct mii_data *mii; 1534 1535 sc = xsc; 1536 ifp = sc->vge_ifp; 1537 VGE_LOCK_ASSERT(sc); 1538 mii = device_get_softc(sc->vge_miibus); 1539 1540 mii_tick(mii); 1541 if (sc->vge_link) { 1542 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1543 sc->vge_link = 0; 1544 if_link_state_change(sc->vge_ifp, 1545 LINK_STATE_DOWN); 1546 } 1547 } else { 1548 if (mii->mii_media_status & IFM_ACTIVE && 1549 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1550 sc->vge_link = 1; 1551 if_link_state_change(sc->vge_ifp, 1552 LINK_STATE_UP); 1553 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1554 vge_start_locked(ifp); 1555 } 1556 } 1557 1558 return; 1559} 1560 1561#ifdef DEVICE_POLLING 1562static int 1563vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1564{ 1565 struct vge_softc *sc = ifp->if_softc; 1566 int rx_npkts = 0; 1567 1568 VGE_LOCK(sc); 1569 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1570 goto done; 1571 1572 sc->rxcycles = count; 1573 rx_npkts = vge_rxeof(sc); 1574 vge_txeof(sc); 1575 1576 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1577 vge_start_locked(ifp); 1578 1579 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1580 u_int32_t status; 1581 status = CSR_READ_4(sc, VGE_ISR); 1582 if (status == 0xFFFFFFFF) 1583 goto done; 1584 if (status) 1585 CSR_WRITE_4(sc, VGE_ISR, status); 1586 1587 /* 1588 * XXX check behaviour on receiver stalls. 1589 */ 1590 1591 if (status & VGE_ISR_TXDMA_STALL || 1592 status & VGE_ISR_RXDMA_STALL) 1593 vge_init_locked(sc); 1594 1595 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1596 vge_rxeof(sc); 1597 ifp->if_ierrors++; 1598 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1599 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1600 } 1601 } 1602done: 1603 VGE_UNLOCK(sc); 1604 return (rx_npkts); 1605} 1606#endif /* DEVICE_POLLING */ 1607 1608static void 1609vge_intr(arg) 1610 void *arg; 1611{ 1612 struct vge_softc *sc; 1613 struct ifnet *ifp; 1614 u_int32_t status; 1615 1616 sc = arg; 1617 1618 if (sc->suspended) { 1619 return; 1620 } 1621 1622 VGE_LOCK(sc); 1623 ifp = sc->vge_ifp; 1624 1625 if (!(ifp->if_flags & IFF_UP)) { 1626 VGE_UNLOCK(sc); 1627 return; 1628 } 1629 1630#ifdef DEVICE_POLLING 1631 if (ifp->if_capenable & IFCAP_POLLING) { 1632 VGE_UNLOCK(sc); 1633 return; 1634 } 1635#endif 1636 1637 /* Disable interrupts */ 1638 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1639 1640 for (;;) { 1641 1642 status = CSR_READ_4(sc, VGE_ISR); 1643 /* If the card has gone away the read returns 0xffff. */ 1644 if (status == 0xFFFFFFFF) 1645 break; 1646 1647 if (status) 1648 CSR_WRITE_4(sc, VGE_ISR, status); 1649 1650 if ((status & VGE_INTRS) == 0) 1651 break; 1652 1653 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1654 vge_rxeof(sc); 1655 1656 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1657 vge_rxeof(sc); 1658 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1659 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1660 } 1661 1662 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1663 vge_txeof(sc); 1664 1665 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1666 vge_init_locked(sc); 1667 1668 if (status & VGE_ISR_LINKSTS) 1669 vge_tick(sc); 1670 } 1671 1672 /* Re-enable interrupts */ 1673 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1674 1675 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1676 vge_start_locked(ifp); 1677 1678 VGE_UNLOCK(sc); 1679 1680 return; 1681} 1682 1683static int 1684vge_encap(sc, m_head, idx) 1685 struct vge_softc *sc; 1686 struct mbuf *m_head; 1687 int idx; 1688{ 1689 struct mbuf *m_new = NULL; 1690 struct vge_dmaload_arg arg; 1691 bus_dmamap_t map; 1692 int error; 1693 1694 if (sc->vge_ldata.vge_tx_free <= 2) 1695 return (EFBIG); 1696 1697 arg.vge_flags = 0; 1698 1699 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1700 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1701 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1702 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1703 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1704 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1705 1706 arg.sc = sc; 1707 arg.vge_idx = idx; 1708 arg.vge_m0 = m_head; 1709 arg.vge_maxsegs = VGE_TX_FRAGS; 1710 1711 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1712 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1713 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1714 1715 if (error && error != EFBIG) { 1716 if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", error); 1717 return (ENOBUFS); 1718 } 1719 1720 /* Too many segments to map, coalesce into a single mbuf */ 1721 1722 if (error || arg.vge_maxsegs == 0) { 1723 m_new = m_defrag(m_head, M_DONTWAIT); 1724 if (m_new == NULL) 1725 return (1); 1726 else 1727 m_head = m_new; 1728 1729 arg.sc = sc; 1730 arg.vge_m0 = m_head; 1731 arg.vge_idx = idx; 1732 arg.vge_maxsegs = 1; 1733 1734 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1735 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1736 if (error) { 1737 if_printf(sc->vge_ifp, "can't map mbuf (error %d)\n", 1738 error); 1739 return (EFBIG); 1740 } 1741 } 1742 1743 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1744 sc->vge_ldata.vge_tx_free--; 1745 1746 /* 1747 * Set up hardware VLAN tagging. 1748 */ 1749 1750 if (m_head->m_flags & M_VLANTAG) 1751 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1752 htole32(m_head->m_pkthdr.ether_vtag | VGE_TDCTL_VTAG); 1753 1754 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1755 1756 return (0); 1757} 1758 1759/* 1760 * Main transmit routine. 1761 */ 1762 1763static void 1764vge_start(ifp) 1765 struct ifnet *ifp; 1766{ 1767 struct vge_softc *sc; 1768 1769 sc = ifp->if_softc; 1770 VGE_LOCK(sc); 1771 vge_start_locked(ifp); 1772 VGE_UNLOCK(sc); 1773} 1774 1775static void 1776vge_start_locked(ifp) 1777 struct ifnet *ifp; 1778{ 1779 struct vge_softc *sc; 1780 struct mbuf *m_head = NULL; 1781 int idx, pidx = 0; 1782 1783 sc = ifp->if_softc; 1784 VGE_LOCK_ASSERT(sc); 1785 1786 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) 1787 return; 1788 1789 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1790 return; 1791 1792 idx = sc->vge_ldata.vge_tx_prodidx; 1793 1794 pidx = idx - 1; 1795 if (pidx < 0) 1796 pidx = VGE_TX_DESC_CNT - 1; 1797 1798 1799 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1800 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1801 if (m_head == NULL) 1802 break; 1803 1804 if (vge_encap(sc, m_head, idx)) { 1805 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1806 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1807 break; 1808 } 1809 1810 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1811 htole16(VGE_TXDESC_Q); 1812 1813 pidx = idx; 1814 VGE_TX_DESC_INC(idx); 1815 1816 /* 1817 * If there's a BPF listener, bounce a copy of this frame 1818 * to him. 1819 */ 1820 ETHER_BPF_MTAP(ifp, m_head); 1821 } 1822 1823 if (idx == sc->vge_ldata.vge_tx_prodidx) 1824 return; 1825 1826 /* Flush the TX descriptors */ 1827 1828 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1829 sc->vge_ldata.vge_tx_list_map, 1830 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1831 1832 /* Issue a transmit command. */ 1833 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1834 1835 sc->vge_ldata.vge_tx_prodidx = idx; 1836 1837 /* 1838 * Use the countdown timer for interrupt moderation. 1839 * 'TX done' interrupts are disabled. Instead, we reset the 1840 * countdown timer, which will begin counting until it hits 1841 * the value in the SSTIMER register, and then trigger an 1842 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1843 * the timer count is reloaded. Only when the transmitter 1844 * is idle will the timer hit 0 and an interrupt fire. 1845 */ 1846 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1847 1848 /* 1849 * Set a timeout in case the chip goes out to lunch. 1850 */ 1851 sc->vge_timer = 5; 1852 1853 return; 1854} 1855 1856static void 1857vge_init(xsc) 1858 void *xsc; 1859{ 1860 struct vge_softc *sc = xsc; 1861 1862 VGE_LOCK(sc); 1863 vge_init_locked(sc); 1864 VGE_UNLOCK(sc); 1865} 1866 1867static void 1868vge_init_locked(struct vge_softc *sc) 1869{ 1870 struct ifnet *ifp = sc->vge_ifp; 1871 struct mii_data *mii; 1872 int i; 1873 1874 VGE_LOCK_ASSERT(sc); 1875 mii = device_get_softc(sc->vge_miibus); 1876 1877 /* 1878 * Cancel pending I/O and free all RX/TX buffers. 1879 */ 1880 vge_stop(sc); 1881 vge_reset(sc); 1882 1883 /* 1884 * Initialize the RX and TX descriptors and mbufs. 1885 */ 1886 1887 vge_rx_list_init(sc); 1888 vge_tx_list_init(sc); 1889 1890 /* Set our station address */ 1891 for (i = 0; i < ETHER_ADDR_LEN; i++) 1892 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1893 1894 /* 1895 * Set receive FIFO threshold. Also allow transmission and 1896 * reception of VLAN tagged frames. 1897 */ 1898 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1899 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1900 1901 /* Set DMA burst length */ 1902 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1903 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1904 1905 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1906 1907 /* Set collision backoff algorithm */ 1908 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1909 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1910 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1911 1912 /* Disable LPSEL field in priority resolution */ 1913 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1914 1915 /* 1916 * Load the addresses of the DMA queues into the chip. 1917 * Note that we only use one transmit queue. 1918 */ 1919 1920 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 1921 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 1922 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 1923 1924 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 1925 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 1926 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 1927 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 1928 1929 /* Enable and wake up the RX descriptor queue */ 1930 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1931 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1932 1933 /* Enable the TX descriptor queue */ 1934 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 1935 1936 /* Set up the receive filter -- allow large frames for VLANs. */ 1937 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 1938 1939 /* If we want promiscuous mode, set the allframes bit. */ 1940 if (ifp->if_flags & IFF_PROMISC) { 1941 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 1942 } 1943 1944 /* Set capture broadcast bit to capture broadcast frames. */ 1945 if (ifp->if_flags & IFF_BROADCAST) { 1946 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 1947 } 1948 1949 /* Set multicast bit to capture multicast frames. */ 1950 if (ifp->if_flags & IFF_MULTICAST) { 1951 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 1952 } 1953 1954 /* Init the cam filter. */ 1955 vge_cam_clear(sc); 1956 1957 /* Init the multicast filter. */ 1958 vge_setmulti(sc); 1959 1960 /* Enable flow control */ 1961 1962 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 1963 1964 /* Enable jumbo frame reception (if desired) */ 1965 1966 /* Start the MAC. */ 1967 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 1968 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 1969 CSR_WRITE_1(sc, VGE_CRS0, 1970 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 1971 1972 /* 1973 * Configure one-shot timer for microsecond 1974 * resulution and load it for 500 usecs. 1975 */ 1976 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 1977 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 1978 1979 /* 1980 * Configure interrupt moderation for receive. Enable 1981 * the holdoff counter and load it, and set the RX 1982 * suppression count to the number of descriptors we 1983 * want to allow before triggering an interrupt. 1984 * The holdoff timer is in units of 20 usecs. 1985 */ 1986 1987#ifdef notyet 1988 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 1989 /* Select the interrupt holdoff timer page. */ 1990 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 1991 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 1992 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 1993 1994 /* Enable use of the holdoff timer. */ 1995 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 1996 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 1997 1998 /* Select the RX suppression threshold page. */ 1999 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2000 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2001 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2002 2003 /* Restore the page select bits. */ 2004 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2005 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2006#endif 2007 2008#ifdef DEVICE_POLLING 2009 /* 2010 * Disable interrupts if we are polling. 2011 */ 2012 if (ifp->if_capenable & IFCAP_POLLING) { 2013 CSR_WRITE_4(sc, VGE_IMR, 0); 2014 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2015 } else /* otherwise ... */ 2016#endif 2017 { 2018 /* 2019 * Enable interrupts. 2020 */ 2021 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2022 CSR_WRITE_4(sc, VGE_ISR, 0); 2023 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2024 } 2025 2026 mii_mediachg(mii); 2027 2028 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2029 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2030 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2031 2032 sc->vge_if_flags = 0; 2033 sc->vge_link = 0; 2034 2035 return; 2036} 2037 2038/* 2039 * Set media options. 2040 */ 2041static int 2042vge_ifmedia_upd(ifp) 2043 struct ifnet *ifp; 2044{ 2045 struct vge_softc *sc; 2046 struct mii_data *mii; 2047 2048 sc = ifp->if_softc; 2049 VGE_LOCK(sc); 2050 mii = device_get_softc(sc->vge_miibus); 2051 mii_mediachg(mii); 2052 VGE_UNLOCK(sc); 2053 2054 return (0); 2055} 2056 2057/* 2058 * Report current media status. 2059 */ 2060static void 2061vge_ifmedia_sts(ifp, ifmr) 2062 struct ifnet *ifp; 2063 struct ifmediareq *ifmr; 2064{ 2065 struct vge_softc *sc; 2066 struct mii_data *mii; 2067 2068 sc = ifp->if_softc; 2069 mii = device_get_softc(sc->vge_miibus); 2070 2071 VGE_LOCK(sc); 2072 mii_pollstat(mii); 2073 VGE_UNLOCK(sc); 2074 ifmr->ifm_active = mii->mii_media_active; 2075 ifmr->ifm_status = mii->mii_media_status; 2076 2077 return; 2078} 2079 2080static void 2081vge_miibus_statchg(dev) 2082 device_t dev; 2083{ 2084 struct vge_softc *sc; 2085 struct mii_data *mii; 2086 struct ifmedia_entry *ife; 2087 2088 sc = device_get_softc(dev); 2089 mii = device_get_softc(sc->vge_miibus); 2090 ife = mii->mii_media.ifm_cur; 2091 2092 /* 2093 * If the user manually selects a media mode, we need to turn 2094 * on the forced MAC mode bit in the DIAGCTL register. If the 2095 * user happens to choose a full duplex mode, we also need to 2096 * set the 'force full duplex' bit. This applies only to 2097 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2098 * mode is disabled, and in 1000baseT mode, full duplex is 2099 * always implied, so we turn on the forced mode bit but leave 2100 * the FDX bit cleared. 2101 */ 2102 2103 switch (IFM_SUBTYPE(ife->ifm_media)) { 2104 case IFM_AUTO: 2105 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2106 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2107 break; 2108 case IFM_1000_T: 2109 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2110 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2111 break; 2112 case IFM_100_TX: 2113 case IFM_10_T: 2114 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2115 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2116 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2117 } else { 2118 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2119 } 2120 break; 2121 default: 2122 device_printf(dev, "unknown media type: %x\n", 2123 IFM_SUBTYPE(ife->ifm_media)); 2124 break; 2125 } 2126 2127 return; 2128} 2129 2130static int 2131vge_ioctl(ifp, command, data) 2132 struct ifnet *ifp; 2133 u_long command; 2134 caddr_t data; 2135{ 2136 struct vge_softc *sc = ifp->if_softc; 2137 struct ifreq *ifr = (struct ifreq *) data; 2138 struct mii_data *mii; 2139 int error = 0; 2140 2141 switch (command) { 2142 case SIOCSIFMTU: 2143 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2144 error = EINVAL; 2145 ifp->if_mtu = ifr->ifr_mtu; 2146 break; 2147 case SIOCSIFFLAGS: 2148 VGE_LOCK(sc); 2149 if (ifp->if_flags & IFF_UP) { 2150 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2151 ifp->if_flags & IFF_PROMISC && 2152 !(sc->vge_if_flags & IFF_PROMISC)) { 2153 CSR_SETBIT_1(sc, VGE_RXCTL, 2154 VGE_RXCTL_RX_PROMISC); 2155 vge_setmulti(sc); 2156 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2157 !(ifp->if_flags & IFF_PROMISC) && 2158 sc->vge_if_flags & IFF_PROMISC) { 2159 CSR_CLRBIT_1(sc, VGE_RXCTL, 2160 VGE_RXCTL_RX_PROMISC); 2161 vge_setmulti(sc); 2162 } else 2163 vge_init_locked(sc); 2164 } else { 2165 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2166 vge_stop(sc); 2167 } 2168 sc->vge_if_flags = ifp->if_flags; 2169 VGE_UNLOCK(sc); 2170 break; 2171 case SIOCADDMULTI: 2172 case SIOCDELMULTI: 2173 VGE_LOCK(sc); 2174 vge_setmulti(sc); 2175 VGE_UNLOCK(sc); 2176 break; 2177 case SIOCGIFMEDIA: 2178 case SIOCSIFMEDIA: 2179 mii = device_get_softc(sc->vge_miibus); 2180 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2181 break; 2182 case SIOCSIFCAP: 2183 { 2184 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2185#ifdef DEVICE_POLLING 2186 if (mask & IFCAP_POLLING) { 2187 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2188 error = ether_poll_register(vge_poll, ifp); 2189 if (error) 2190 return(error); 2191 VGE_LOCK(sc); 2192 /* Disable interrupts */ 2193 CSR_WRITE_4(sc, VGE_IMR, 0); 2194 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2195 ifp->if_capenable |= IFCAP_POLLING; 2196 VGE_UNLOCK(sc); 2197 } else { 2198 error = ether_poll_deregister(ifp); 2199 /* Enable interrupts. */ 2200 VGE_LOCK(sc); 2201 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2202 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2203 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2204 ifp->if_capenable &= ~IFCAP_POLLING; 2205 VGE_UNLOCK(sc); 2206 } 2207 } 2208#endif /* DEVICE_POLLING */ 2209 VGE_LOCK(sc); 2210 if ((mask & IFCAP_TXCSUM) != 0 && 2211 (ifp->if_capabilities & IFCAP_TXCSUM) != 0) { 2212 ifp->if_capenable ^= IFCAP_TXCSUM; 2213 if ((ifp->if_capenable & IFCAP_TXCSUM) != 0) 2214 ifp->if_hwassist |= VGE_CSUM_FEATURES; 2215 else 2216 ifp->if_hwassist &= ~VGE_CSUM_FEATURES; 2217 } 2218 if ((mask & IFCAP_RXCSUM) != 0 && 2219 (ifp->if_capabilities & IFCAP_RXCSUM) != 0) 2220 ifp->if_capenable ^= IFCAP_RXCSUM; 2221 VGE_UNLOCK(sc); 2222 } 2223 break; 2224 default: 2225 error = ether_ioctl(ifp, command, data); 2226 break; 2227 } 2228 2229 return (error); 2230} 2231 2232static void 2233vge_watchdog(void *arg) 2234{ 2235 struct vge_softc *sc; 2236 struct ifnet *ifp; 2237 2238 sc = arg; 2239 VGE_LOCK_ASSERT(sc); 2240 callout_reset(&sc->vge_watchdog, hz, vge_watchdog, sc); 2241 if (sc->vge_timer == 0 || --sc->vge_timer > 0) 2242 return; 2243 2244 ifp = sc->vge_ifp; 2245 if_printf(ifp, "watchdog timeout\n"); 2246 ifp->if_oerrors++; 2247 2248 vge_txeof(sc); 2249 vge_rxeof(sc); 2250 2251 vge_init_locked(sc); 2252 2253 return; 2254} 2255 2256/* 2257 * Stop the adapter and free any mbufs allocated to the 2258 * RX and TX lists. 2259 */ 2260static void 2261vge_stop(sc) 2262 struct vge_softc *sc; 2263{ 2264 int i; 2265 struct ifnet *ifp; 2266 2267 VGE_LOCK_ASSERT(sc); 2268 ifp = sc->vge_ifp; 2269 sc->vge_timer = 0; 2270 callout_stop(&sc->vge_watchdog); 2271 2272 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2273 2274 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2275 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2276 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2277 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2278 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2279 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2280 2281 if (sc->vge_head != NULL) { 2282 m_freem(sc->vge_head); 2283 sc->vge_head = sc->vge_tail = NULL; 2284 } 2285 2286 /* Free the TX list buffers. */ 2287 2288 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2289 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2290 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2291 sc->vge_ldata.vge_tx_dmamap[i]); 2292 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2293 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2294 } 2295 } 2296 2297 /* Free the RX list buffers. */ 2298 2299 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2300 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2301 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2302 sc->vge_ldata.vge_rx_dmamap[i]); 2303 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2304 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2305 } 2306 } 2307 2308 return; 2309} 2310 2311/* 2312 * Device suspend routine. Stop the interface and save some PCI 2313 * settings in case the BIOS doesn't restore them properly on 2314 * resume. 2315 */ 2316static int 2317vge_suspend(dev) 2318 device_t dev; 2319{ 2320 struct vge_softc *sc; 2321 2322 sc = device_get_softc(dev); 2323 2324 VGE_LOCK(sc); 2325 vge_stop(sc); 2326 2327 sc->suspended = 1; 2328 VGE_UNLOCK(sc); 2329 2330 return (0); 2331} 2332 2333/* 2334 * Device resume routine. Restore some PCI settings in case the BIOS 2335 * doesn't, re-enable busmastering, and restart the interface if 2336 * appropriate. 2337 */ 2338static int 2339vge_resume(dev) 2340 device_t dev; 2341{ 2342 struct vge_softc *sc; 2343 struct ifnet *ifp; 2344 2345 sc = device_get_softc(dev); 2346 ifp = sc->vge_ifp; 2347 2348 /* reenable busmastering */ 2349 pci_enable_busmaster(dev); 2350 pci_enable_io(dev, SYS_RES_MEMORY); 2351 2352 /* reinitialize interface if necessary */ 2353 VGE_LOCK(sc); 2354 if (ifp->if_flags & IFF_UP) 2355 vge_init_locked(sc); 2356 2357 sc->suspended = 0; 2358 VGE_UNLOCK(sc); 2359 2360 return (0); 2361} 2362 2363/* 2364 * Stop all chip I/O so that the kernel's probe routines don't 2365 * get confused by errant DMAs when rebooting. 2366 */ 2367static int 2368vge_shutdown(dev) 2369 device_t dev; 2370{ 2371 struct vge_softc *sc; 2372 2373 sc = device_get_softc(dev); 2374 2375 VGE_LOCK(sc); 2376 vge_stop(sc); 2377 VGE_UNLOCK(sc); 2378 2379 return (0); 2380} 2381