if_vge.c revision 155671
1/*- 2 * Copyright (c) 2004 3 * Bill Paul <wpaul@windriver.com>. All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 3. All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by Bill Paul. 16 * 4. Neither the name of the author nor the names of any co-contributors 17 * may be used to endorse or promote products derived from this software 18 * without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 30 * THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33#include <sys/cdefs.h> 34__FBSDID("$FreeBSD: head/sys/dev/vge/if_vge.c 155671 2006-02-14 12:44:56Z glebius $"); 35 36/* 37 * VIA Networking Technologies VT612x PCI gigabit ethernet NIC driver. 38 * 39 * Written by Bill Paul <wpaul@windriver.com> 40 * Senior Networking Software Engineer 41 * Wind River Systems 42 */ 43 44/* 45 * The VIA Networking VT6122 is a 32bit, 33/66Mhz PCI device that 46 * combines a tri-speed ethernet MAC and PHY, with the following 47 * features: 48 * 49 * o Jumbo frame support up to 16K 50 * o Transmit and receive flow control 51 * o IPv4 checksum offload 52 * o VLAN tag insertion and stripping 53 * o TCP large send 54 * o 64-bit multicast hash table filter 55 * o 64 entry CAM filter 56 * o 16K RX FIFO and 48K TX FIFO memory 57 * o Interrupt moderation 58 * 59 * The VT6122 supports up to four transmit DMA queues. The descriptors 60 * in the transmit ring can address up to 7 data fragments; frames which 61 * span more than 7 data buffers must be coalesced, but in general the 62 * BSD TCP/IP stack rarely generates frames more than 2 or 3 fragments 63 * long. The receive descriptors address only a single buffer. 64 * 65 * There are two peculiar design issues with the VT6122. One is that 66 * receive data buffers must be aligned on a 32-bit boundary. This is 67 * not a problem where the VT6122 is used as a LOM device in x86-based 68 * systems, but on architectures that generate unaligned access traps, we 69 * have to do some copying. 70 * 71 * The other issue has to do with the way 64-bit addresses are handled. 72 * The DMA descriptors only allow you to specify 48 bits of addressing 73 * information. The remaining 16 bits are specified using one of the 74 * I/O registers. If you only have a 32-bit system, then this isn't 75 * an issue, but if you have a 64-bit system and more than 4GB of 76 * memory, you must have to make sure your network data buffers reside 77 * in the same 48-bit 'segment.' 78 * 79 * Special thanks to Ryan Fu at VIA Networking for providing documentation 80 * and sample NICs for testing. 81 */ 82 83#ifdef HAVE_KERNEL_OPTION_HEADERS 84#include "opt_device_polling.h" 85#endif 86 87#include <sys/param.h> 88#include <sys/endian.h> 89#include <sys/systm.h> 90#include <sys/sockio.h> 91#include <sys/mbuf.h> 92#include <sys/malloc.h> 93#include <sys/module.h> 94#include <sys/kernel.h> 95#include <sys/socket.h> 96#include <sys/taskqueue.h> 97 98#include <net/if.h> 99#include <net/if_arp.h> 100#include <net/ethernet.h> 101#include <net/if_dl.h> 102#include <net/if_media.h> 103#include <net/if_types.h> 104#include <net/if_vlan_var.h> 105 106#include <net/bpf.h> 107 108#include <machine/bus.h> 109#include <machine/resource.h> 110#include <sys/bus.h> 111#include <sys/rman.h> 112 113#include <dev/mii/mii.h> 114#include <dev/mii/miivar.h> 115 116#include <dev/pci/pcireg.h> 117#include <dev/pci/pcivar.h> 118 119MODULE_DEPEND(vge, pci, 1, 1, 1); 120MODULE_DEPEND(vge, ether, 1, 1, 1); 121MODULE_DEPEND(vge, miibus, 1, 1, 1); 122 123/* "device miibus" required. See GENERIC if you get errors here. */ 124#include "miibus_if.h" 125 126#include <dev/vge/if_vgereg.h> 127#include <dev/vge/if_vgevar.h> 128 129#define VGE_CSUM_FEATURES (CSUM_IP | CSUM_TCP | CSUM_UDP) 130 131/* 132 * Various supported device vendors/types and their names. 133 */ 134static struct vge_type vge_devs[] = { 135 { VIA_VENDORID, VIA_DEVICEID_61XX, 136 "VIA Networking Gigabit Ethernet" }, 137 { 0, 0, NULL } 138}; 139 140static int vge_probe (device_t); 141static int vge_attach (device_t); 142static int vge_detach (device_t); 143 144static int vge_encap (struct vge_softc *, struct mbuf *, int); 145 146static void vge_dma_map_addr (void *, bus_dma_segment_t *, int, int); 147static void vge_dma_map_rx_desc (void *, bus_dma_segment_t *, int, 148 bus_size_t, int); 149static void vge_dma_map_tx_desc (void *, bus_dma_segment_t *, int, 150 bus_size_t, int); 151static int vge_allocmem (device_t, struct vge_softc *); 152static int vge_newbuf (struct vge_softc *, int, struct mbuf *); 153static int vge_rx_list_init (struct vge_softc *); 154static int vge_tx_list_init (struct vge_softc *); 155#ifdef VGE_FIXUP_RX 156static __inline void vge_fixup_rx 157 (struct mbuf *); 158#endif 159static void vge_rxeof (struct vge_softc *); 160static void vge_txeof (struct vge_softc *); 161static void vge_intr (void *); 162static void vge_tick (void *); 163static void vge_tx_task (void *, int); 164static void vge_start (struct ifnet *); 165static int vge_ioctl (struct ifnet *, u_long, caddr_t); 166static void vge_init (void *); 167static void vge_stop (struct vge_softc *); 168static void vge_watchdog (struct ifnet *); 169static int vge_suspend (device_t); 170static int vge_resume (device_t); 171static void vge_shutdown (device_t); 172static int vge_ifmedia_upd (struct ifnet *); 173static void vge_ifmedia_sts (struct ifnet *, struct ifmediareq *); 174 175#ifdef VGE_EEPROM 176static void vge_eeprom_getword (struct vge_softc *, int, u_int16_t *); 177#endif 178static void vge_read_eeprom (struct vge_softc *, caddr_t, int, int, int); 179 180static void vge_miipoll_start (struct vge_softc *); 181static void vge_miipoll_stop (struct vge_softc *); 182static int vge_miibus_readreg (device_t, int, int); 183static int vge_miibus_writereg (device_t, int, int, int); 184static void vge_miibus_statchg (device_t); 185 186static void vge_cam_clear (struct vge_softc *); 187static int vge_cam_set (struct vge_softc *, uint8_t *); 188#if __FreeBSD_version < 502113 189static uint32_t vge_mchash (uint8_t *); 190#endif 191static void vge_setmulti (struct vge_softc *); 192static void vge_reset (struct vge_softc *); 193 194#define VGE_PCI_LOIO 0x10 195#define VGE_PCI_LOMEM 0x14 196 197static device_method_t vge_methods[] = { 198 /* Device interface */ 199 DEVMETHOD(device_probe, vge_probe), 200 DEVMETHOD(device_attach, vge_attach), 201 DEVMETHOD(device_detach, vge_detach), 202 DEVMETHOD(device_suspend, vge_suspend), 203 DEVMETHOD(device_resume, vge_resume), 204 DEVMETHOD(device_shutdown, vge_shutdown), 205 206 /* bus interface */ 207 DEVMETHOD(bus_print_child, bus_generic_print_child), 208 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 209 210 /* MII interface */ 211 DEVMETHOD(miibus_readreg, vge_miibus_readreg), 212 DEVMETHOD(miibus_writereg, vge_miibus_writereg), 213 DEVMETHOD(miibus_statchg, vge_miibus_statchg), 214 215 { 0, 0 } 216}; 217 218static driver_t vge_driver = { 219 "vge", 220 vge_methods, 221 sizeof(struct vge_softc) 222}; 223 224static devclass_t vge_devclass; 225 226DRIVER_MODULE(vge, pci, vge_driver, vge_devclass, 0, 0); 227DRIVER_MODULE(vge, cardbus, vge_driver, vge_devclass, 0, 0); 228DRIVER_MODULE(miibus, vge, miibus_driver, miibus_devclass, 0, 0); 229 230#ifdef VGE_EEPROM 231/* 232 * Read a word of data stored in the EEPROM at address 'addr.' 233 */ 234static void 235vge_eeprom_getword(sc, addr, dest) 236 struct vge_softc *sc; 237 int addr; 238 u_int16_t *dest; 239{ 240 register int i; 241 u_int16_t word = 0; 242 243 /* 244 * Enter EEPROM embedded programming mode. In order to 245 * access the EEPROM at all, we first have to set the 246 * EELOAD bit in the CHIPCFG2 register. 247 */ 248 CSR_SETBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 249 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 250 251 /* Select the address of the word we want to read */ 252 CSR_WRITE_1(sc, VGE_EEADDR, addr); 253 254 /* Issue read command */ 255 CSR_SETBIT_1(sc, VGE_EECMD, VGE_EECMD_ERD); 256 257 /* Wait for the done bit to be set. */ 258 for (i = 0; i < VGE_TIMEOUT; i++) { 259 if (CSR_READ_1(sc, VGE_EECMD) & VGE_EECMD_EDONE) 260 break; 261 } 262 263 if (i == VGE_TIMEOUT) { 264 device_printf(sc->vge_dev, "EEPROM read timed out\n"); 265 *dest = 0; 266 return; 267 } 268 269 /* Read the result */ 270 word = CSR_READ_2(sc, VGE_EERDDAT); 271 272 /* Turn off EEPROM access mode. */ 273 CSR_CLRBIT_1(sc, VGE_EECSR, VGE_EECSR_EMBP/*|VGE_EECSR_ECS*/); 274 CSR_CLRBIT_1(sc, VGE_CHIPCFG2, VGE_CHIPCFG2_EELOAD); 275 276 *dest = word; 277 278 return; 279} 280#endif 281 282/* 283 * Read a sequence of words from the EEPROM. 284 */ 285static void 286vge_read_eeprom(sc, dest, off, cnt, swap) 287 struct vge_softc *sc; 288 caddr_t dest; 289 int off; 290 int cnt; 291 int swap; 292{ 293 int i; 294#ifdef VGE_EEPROM 295 u_int16_t word = 0, *ptr; 296 297 for (i = 0; i < cnt; i++) { 298 vge_eeprom_getword(sc, off + i, &word); 299 ptr = (u_int16_t *)(dest + (i * 2)); 300 if (swap) 301 *ptr = ntohs(word); 302 else 303 *ptr = word; 304 } 305#else 306 for (i = 0; i < ETHER_ADDR_LEN; i++) 307 dest[i] = CSR_READ_1(sc, VGE_PAR0 + i); 308#endif 309} 310 311static void 312vge_miipoll_stop(sc) 313 struct vge_softc *sc; 314{ 315 int i; 316 317 CSR_WRITE_1(sc, VGE_MIICMD, 0); 318 319 for (i = 0; i < VGE_TIMEOUT; i++) { 320 DELAY(1); 321 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 322 break; 323 } 324 325 if (i == VGE_TIMEOUT) 326 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 327 328 return; 329} 330 331static void 332vge_miipoll_start(sc) 333 struct vge_softc *sc; 334{ 335 int i; 336 337 /* First, make sure we're idle. */ 338 339 CSR_WRITE_1(sc, VGE_MIICMD, 0); 340 CSR_WRITE_1(sc, VGE_MIIADDR, VGE_MIIADDR_SWMPL); 341 342 for (i = 0; i < VGE_TIMEOUT; i++) { 343 DELAY(1); 344 if (CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) 345 break; 346 } 347 348 if (i == VGE_TIMEOUT) { 349 device_printf(sc->vge_dev, "failed to idle MII autopoll\n"); 350 return; 351 } 352 353 /* Now enable auto poll mode. */ 354 355 CSR_WRITE_1(sc, VGE_MIICMD, VGE_MIICMD_MAUTO); 356 357 /* And make sure it started. */ 358 359 for (i = 0; i < VGE_TIMEOUT; i++) { 360 DELAY(1); 361 if ((CSR_READ_1(sc, VGE_MIISTS) & VGE_MIISTS_IIDL) == 0) 362 break; 363 } 364 365 if (i == VGE_TIMEOUT) 366 device_printf(sc->vge_dev, "failed to start MII autopoll\n"); 367 368 return; 369} 370 371static int 372vge_miibus_readreg(dev, phy, reg) 373 device_t dev; 374 int phy, reg; 375{ 376 struct vge_softc *sc; 377 int i; 378 u_int16_t rval = 0; 379 380 sc = device_get_softc(dev); 381 382 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 383 return(0); 384 385 VGE_LOCK(sc); 386 vge_miipoll_stop(sc); 387 388 /* Specify the register we want to read. */ 389 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 390 391 /* Issue read command. */ 392 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_RCMD); 393 394 /* Wait for the read command bit to self-clear. */ 395 for (i = 0; i < VGE_TIMEOUT; i++) { 396 DELAY(1); 397 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_RCMD) == 0) 398 break; 399 } 400 401 if (i == VGE_TIMEOUT) 402 device_printf(sc->vge_dev, "MII read timed out\n"); 403 else 404 rval = CSR_READ_2(sc, VGE_MIIDATA); 405 406 vge_miipoll_start(sc); 407 VGE_UNLOCK(sc); 408 409 return (rval); 410} 411 412static int 413vge_miibus_writereg(dev, phy, reg, data) 414 device_t dev; 415 int phy, reg, data; 416{ 417 struct vge_softc *sc; 418 int i, rval = 0; 419 420 sc = device_get_softc(dev); 421 422 if (phy != (CSR_READ_1(sc, VGE_MIICFG) & 0x1F)) 423 return(0); 424 425 VGE_LOCK(sc); 426 vge_miipoll_stop(sc); 427 428 /* Specify the register we want to write. */ 429 CSR_WRITE_1(sc, VGE_MIIADDR, reg); 430 431 /* Specify the data we want to write. */ 432 CSR_WRITE_2(sc, VGE_MIIDATA, data); 433 434 /* Issue write command. */ 435 CSR_SETBIT_1(sc, VGE_MIICMD, VGE_MIICMD_WCMD); 436 437 /* Wait for the write command bit to self-clear. */ 438 for (i = 0; i < VGE_TIMEOUT; i++) { 439 DELAY(1); 440 if ((CSR_READ_1(sc, VGE_MIICMD) & VGE_MIICMD_WCMD) == 0) 441 break; 442 } 443 444 if (i == VGE_TIMEOUT) { 445 device_printf(sc->vge_dev, "MII write timed out\n"); 446 rval = EIO; 447 } 448 449 vge_miipoll_start(sc); 450 VGE_UNLOCK(sc); 451 452 return (rval); 453} 454 455static void 456vge_cam_clear(sc) 457 struct vge_softc *sc; 458{ 459 int i; 460 461 /* 462 * Turn off all the mask bits. This tells the chip 463 * that none of the entries in the CAM filter are valid. 464 * desired entries will be enabled as we fill the filter in. 465 */ 466 467 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 468 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 469 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE); 470 for (i = 0; i < 8; i++) 471 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 472 473 /* Clear the VLAN filter too. */ 474 475 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|VGE_CAMADDR_AVSEL|0); 476 for (i = 0; i < 8; i++) 477 CSR_WRITE_1(sc, VGE_CAM0 + i, 0); 478 479 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 480 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 481 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 482 483 sc->vge_camidx = 0; 484 485 return; 486} 487 488static int 489vge_cam_set(sc, addr) 490 struct vge_softc *sc; 491 uint8_t *addr; 492{ 493 int i, error = 0; 494 495 if (sc->vge_camidx == VGE_CAM_MAXADDRS) 496 return(ENOSPC); 497 498 /* Select the CAM data page. */ 499 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 500 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMDATA); 501 502 /* Set the filter entry we want to update and enable writing. */ 503 CSR_WRITE_1(sc, VGE_CAMADDR, VGE_CAMADDR_ENABLE|sc->vge_camidx); 504 505 /* Write the address to the CAM registers */ 506 for (i = 0; i < ETHER_ADDR_LEN; i++) 507 CSR_WRITE_1(sc, VGE_CAM0 + i, addr[i]); 508 509 /* Issue a write command. */ 510 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_WRITE); 511 512 /* Wake for it to clear. */ 513 for (i = 0; i < VGE_TIMEOUT; i++) { 514 DELAY(1); 515 if ((CSR_READ_1(sc, VGE_CAMCTL) & VGE_CAMCTL_WRITE) == 0) 516 break; 517 } 518 519 if (i == VGE_TIMEOUT) { 520 device_printf(sc->vge_dev, "setting CAM filter failed\n"); 521 error = EIO; 522 goto fail; 523 } 524 525 /* Select the CAM mask page. */ 526 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 527 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_CAMMASK); 528 529 /* Set the mask bit that enables this filter. */ 530 CSR_SETBIT_1(sc, VGE_CAM0 + (sc->vge_camidx/8), 531 1<<(sc->vge_camidx & 7)); 532 533 sc->vge_camidx++; 534 535fail: 536 /* Turn off access to CAM. */ 537 CSR_WRITE_1(sc, VGE_CAMADDR, 0); 538 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 539 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 540 541 return (error); 542} 543 544#if __FreeBSD_version < 502113 545static uint32_t 546vge_mchash(addr) 547 uint8_t *addr; 548{ 549 uint32_t crc, carry; 550 int idx, bit; 551 uint8_t data; 552 553 /* Compute CRC for the address value. */ 554 crc = 0xFFFFFFFF; /* initial value */ 555 556 for (idx = 0; idx < 6; idx++) { 557 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) { 558 carry = ((crc & 0x80000000) ? 1 : 0) ^ (data & 0x01); 559 crc <<= 1; 560 if (carry) 561 crc = (crc ^ 0x04c11db6) | carry; 562 } 563 } 564 565 return(crc); 566} 567#endif 568 569/* 570 * Program the multicast filter. We use the 64-entry CAM filter 571 * for perfect filtering. If there's more than 64 multicast addresses, 572 * we use the hash filter insted. 573 */ 574static void 575vge_setmulti(sc) 576 struct vge_softc *sc; 577{ 578 struct ifnet *ifp; 579 int error = 0/*, h = 0*/; 580 struct ifmultiaddr *ifma; 581 u_int32_t h, hashes[2] = { 0, 0 }; 582 583 ifp = sc->vge_ifp; 584 585 /* First, zot all the multicast entries. */ 586 vge_cam_clear(sc); 587 CSR_WRITE_4(sc, VGE_MAR0, 0); 588 CSR_WRITE_4(sc, VGE_MAR1, 0); 589 590 /* 591 * If the user wants allmulti or promisc mode, enable reception 592 * of all multicast frames. 593 */ 594 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 595 CSR_WRITE_4(sc, VGE_MAR0, 0xFFFFFFFF); 596 CSR_WRITE_4(sc, VGE_MAR1, 0xFFFFFFFF); 597 return; 598 } 599 600 /* Now program new ones */ 601 IF_ADDR_LOCK(ifp); 602 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 603 if (ifma->ifma_addr->sa_family != AF_LINK) 604 continue; 605 error = vge_cam_set(sc, 606 LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 607 if (error) 608 break; 609 } 610 611 /* If there were too many addresses, use the hash filter. */ 612 if (error) { 613 vge_cam_clear(sc); 614 615 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 616 if (ifma->ifma_addr->sa_family != AF_LINK) 617 continue; 618#if __FreeBSD_version < 502113 619 h = vge_mchash(LLADDR((struct sockaddr_dl *) 620 ifma->ifma_addr)) >> 26; 621#else 622 h = ether_crc32_be(LLADDR((struct sockaddr_dl *) 623 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 624#endif 625 if (h < 32) 626 hashes[0] |= (1 << h); 627 else 628 hashes[1] |= (1 << (h - 32)); 629 } 630 631 CSR_WRITE_4(sc, VGE_MAR0, hashes[0]); 632 CSR_WRITE_4(sc, VGE_MAR1, hashes[1]); 633 } 634 IF_ADDR_UNLOCK(ifp); 635 636 return; 637} 638 639static void 640vge_reset(sc) 641 struct vge_softc *sc; 642{ 643 register int i; 644 645 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_SOFTRESET); 646 647 for (i = 0; i < VGE_TIMEOUT; i++) { 648 DELAY(5); 649 if ((CSR_READ_1(sc, VGE_CRS1) & VGE_CR1_SOFTRESET) == 0) 650 break; 651 } 652 653 if (i == VGE_TIMEOUT) { 654 device_printf(sc->vge_dev, "soft reset timed out"); 655 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_STOP_FORCE); 656 DELAY(2000); 657 } 658 659 DELAY(5000); 660 661 CSR_SETBIT_1(sc, VGE_EECSR, VGE_EECSR_RELOAD); 662 663 for (i = 0; i < VGE_TIMEOUT; i++) { 664 DELAY(5); 665 if ((CSR_READ_1(sc, VGE_EECSR) & VGE_EECSR_RELOAD) == 0) 666 break; 667 } 668 669 if (i == VGE_TIMEOUT) { 670 device_printf(sc->vge_dev, "EEPROM reload timed out\n"); 671 return; 672 } 673 674 CSR_CLRBIT_1(sc, VGE_CHIPCFG0, VGE_CHIPCFG0_PACPI); 675 676 return; 677} 678 679/* 680 * Probe for a VIA gigabit chip. Check the PCI vendor and device 681 * IDs against our list and return a device name if we find a match. 682 */ 683static int 684vge_probe(dev) 685 device_t dev; 686{ 687 struct vge_type *t; 688 struct vge_softc *sc; 689 690 t = vge_devs; 691 sc = device_get_softc(dev); 692 693 while (t->vge_name != NULL) { 694 if ((pci_get_vendor(dev) == t->vge_vid) && 695 (pci_get_device(dev) == t->vge_did)) { 696 device_set_desc(dev, t->vge_name); 697 return (BUS_PROBE_DEFAULT); 698 } 699 t++; 700 } 701 702 return (ENXIO); 703} 704 705static void 706vge_dma_map_rx_desc(arg, segs, nseg, mapsize, error) 707 void *arg; 708 bus_dma_segment_t *segs; 709 int nseg; 710 bus_size_t mapsize; 711 int error; 712{ 713 714 struct vge_dmaload_arg *ctx; 715 struct vge_rx_desc *d = NULL; 716 717 if (error) 718 return; 719 720 ctx = arg; 721 722 /* Signal error to caller if there's too many segments */ 723 if (nseg > ctx->vge_maxsegs) { 724 ctx->vge_maxsegs = 0; 725 return; 726 } 727 728 /* 729 * Map the segment array into descriptors. 730 */ 731 732 d = &ctx->sc->vge_ldata.vge_rx_list[ctx->vge_idx]; 733 734 /* If this descriptor is still owned by the chip, bail. */ 735 736 if (le32toh(d->vge_sts) & VGE_RDSTS_OWN) { 737 device_printf(ctx->sc->vge_dev, 738 "tried to map busy descriptor\n"); 739 ctx->vge_maxsegs = 0; 740 return; 741 } 742 743 d->vge_buflen = htole16(VGE_BUFLEN(segs[0].ds_len) | VGE_RXDESC_I); 744 d->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 745 d->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 746 d->vge_sts = 0; 747 d->vge_ctl = 0; 748 749 ctx->vge_maxsegs = 1; 750 751 return; 752} 753 754static void 755vge_dma_map_tx_desc(arg, segs, nseg, mapsize, error) 756 void *arg; 757 bus_dma_segment_t *segs; 758 int nseg; 759 bus_size_t mapsize; 760 int error; 761{ 762 struct vge_dmaload_arg *ctx; 763 struct vge_tx_desc *d = NULL; 764 struct vge_tx_frag *f; 765 int i = 0; 766 767 if (error) 768 return; 769 770 ctx = arg; 771 772 /* Signal error to caller if there's too many segments */ 773 if (nseg > ctx->vge_maxsegs) { 774 ctx->vge_maxsegs = 0; 775 return; 776 } 777 778 /* Map the segment array into descriptors. */ 779 780 d = &ctx->sc->vge_ldata.vge_tx_list[ctx->vge_idx]; 781 782 /* If this descriptor is still owned by the chip, bail. */ 783 784 if (le32toh(d->vge_sts) & VGE_TDSTS_OWN) { 785 ctx->vge_maxsegs = 0; 786 return; 787 } 788 789 for (i = 0; i < nseg; i++) { 790 f = &d->vge_frag[i]; 791 f->vge_buflen = htole16(VGE_BUFLEN(segs[i].ds_len)); 792 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[i].ds_addr)); 793 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[i].ds_addr) & 0xFFFF); 794 } 795 796 /* Argh. This chip does not autopad short frames */ 797 798 if (ctx->vge_m0->m_pkthdr.len < VGE_MIN_FRAMELEN) { 799 f = &d->vge_frag[i]; 800 f->vge_buflen = htole16(VGE_BUFLEN(VGE_MIN_FRAMELEN - 801 ctx->vge_m0->m_pkthdr.len)); 802 f->vge_addrlo = htole32(VGE_ADDR_LO(segs[0].ds_addr)); 803 f->vge_addrhi = htole16(VGE_ADDR_HI(segs[0].ds_addr) & 0xFFFF); 804 ctx->vge_m0->m_pkthdr.len = VGE_MIN_FRAMELEN; 805 i++; 806 } 807 808 /* 809 * When telling the chip how many segments there are, we 810 * must use nsegs + 1 instead of just nsegs. Darned if I 811 * know why. 812 */ 813 i++; 814 815 d->vge_sts = ctx->vge_m0->m_pkthdr.len << 16; 816 d->vge_ctl = ctx->vge_flags|(i << 28)|VGE_TD_LS_NORM; 817 818 if (ctx->vge_m0->m_pkthdr.len > ETHERMTU + ETHER_HDR_LEN) 819 d->vge_ctl |= VGE_TDCTL_JUMBO; 820 821 ctx->vge_maxsegs = nseg; 822 823 return; 824} 825 826/* 827 * Map a single buffer address. 828 */ 829 830static void 831vge_dma_map_addr(arg, segs, nseg, error) 832 void *arg; 833 bus_dma_segment_t *segs; 834 int nseg; 835 int error; 836{ 837 bus_addr_t *addr; 838 839 if (error) 840 return; 841 842 KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); 843 addr = arg; 844 *addr = segs->ds_addr; 845 846 return; 847} 848 849static int 850vge_allocmem(dev, sc) 851 device_t dev; 852 struct vge_softc *sc; 853{ 854 int error; 855 int nseg; 856 int i; 857 858 /* 859 * Allocate map for RX mbufs. 860 */ 861 nseg = 32; 862 error = bus_dma_tag_create(sc->vge_parent_tag, ETHER_ALIGN, 0, 863 BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 864 NULL, MCLBYTES * nseg, nseg, MCLBYTES, BUS_DMA_ALLOCNOW, 865 NULL, NULL, &sc->vge_ldata.vge_mtag); 866 if (error) { 867 device_printf(dev, "could not allocate dma tag\n"); 868 return (ENOMEM); 869 } 870 871 /* 872 * Allocate map for TX descriptor list. 873 */ 874 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 875 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 876 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 877 NULL, NULL, &sc->vge_ldata.vge_tx_list_tag); 878 if (error) { 879 device_printf(dev, "could not allocate dma tag\n"); 880 return (ENOMEM); 881 } 882 883 /* Allocate DMA'able memory for the TX ring */ 884 885 error = bus_dmamem_alloc(sc->vge_ldata.vge_tx_list_tag, 886 (void **)&sc->vge_ldata.vge_tx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 887 &sc->vge_ldata.vge_tx_list_map); 888 if (error) 889 return (ENOMEM); 890 891 /* Load the map for the TX ring. */ 892 893 error = bus_dmamap_load(sc->vge_ldata.vge_tx_list_tag, 894 sc->vge_ldata.vge_tx_list_map, sc->vge_ldata.vge_tx_list, 895 VGE_TX_LIST_SZ, vge_dma_map_addr, 896 &sc->vge_ldata.vge_tx_list_addr, BUS_DMA_NOWAIT); 897 898 /* Create DMA maps for TX buffers */ 899 900 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 901 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 902 &sc->vge_ldata.vge_tx_dmamap[i]); 903 if (error) { 904 device_printf(dev, "can't create DMA map for TX\n"); 905 return (ENOMEM); 906 } 907 } 908 909 /* 910 * Allocate map for RX descriptor list. 911 */ 912 error = bus_dma_tag_create(sc->vge_parent_tag, VGE_RING_ALIGN, 913 0, BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, 914 NULL, VGE_TX_LIST_SZ, 1, VGE_TX_LIST_SZ, BUS_DMA_ALLOCNOW, 915 NULL, NULL, &sc->vge_ldata.vge_rx_list_tag); 916 if (error) { 917 device_printf(dev, "could not allocate dma tag\n"); 918 return (ENOMEM); 919 } 920 921 /* Allocate DMA'able memory for the RX ring */ 922 923 error = bus_dmamem_alloc(sc->vge_ldata.vge_rx_list_tag, 924 (void **)&sc->vge_ldata.vge_rx_list, BUS_DMA_NOWAIT | BUS_DMA_ZERO, 925 &sc->vge_ldata.vge_rx_list_map); 926 if (error) 927 return (ENOMEM); 928 929 /* Load the map for the RX ring. */ 930 931 error = bus_dmamap_load(sc->vge_ldata.vge_rx_list_tag, 932 sc->vge_ldata.vge_rx_list_map, sc->vge_ldata.vge_rx_list, 933 VGE_TX_LIST_SZ, vge_dma_map_addr, 934 &sc->vge_ldata.vge_rx_list_addr, BUS_DMA_NOWAIT); 935 936 /* Create DMA maps for RX buffers */ 937 938 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 939 error = bus_dmamap_create(sc->vge_ldata.vge_mtag, 0, 940 &sc->vge_ldata.vge_rx_dmamap[i]); 941 if (error) { 942 device_printf(dev, "can't create DMA map for RX\n"); 943 return (ENOMEM); 944 } 945 } 946 947 return (0); 948} 949 950/* 951 * Attach the interface. Allocate softc structures, do ifmedia 952 * setup and ethernet/BPF attach. 953 */ 954static int 955vge_attach(dev) 956 device_t dev; 957{ 958 u_char eaddr[ETHER_ADDR_LEN]; 959 struct vge_softc *sc; 960 struct ifnet *ifp; 961 int unit, error = 0, rid; 962 963 sc = device_get_softc(dev); 964 unit = device_get_unit(dev); 965 sc->vge_dev = dev; 966 967 mtx_init(&sc->vge_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 968 MTX_DEF | MTX_RECURSE); 969 /* 970 * Map control/status registers. 971 */ 972 pci_enable_busmaster(dev); 973 974 rid = VGE_PCI_LOMEM; 975 sc->vge_res = bus_alloc_resource(dev, SYS_RES_MEMORY, &rid, 976 0, ~0, 1, RF_ACTIVE); 977 978 if (sc->vge_res == NULL) { 979 printf ("vge%d: couldn't map ports/memory\n", unit); 980 error = ENXIO; 981 goto fail; 982 } 983 984 sc->vge_btag = rman_get_bustag(sc->vge_res); 985 sc->vge_bhandle = rman_get_bushandle(sc->vge_res); 986 987 /* Allocate interrupt */ 988 rid = 0; 989 sc->vge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 990 0, ~0, 1, RF_SHAREABLE | RF_ACTIVE); 991 992 if (sc->vge_irq == NULL) { 993 printf("vge%d: couldn't map interrupt\n", unit); 994 error = ENXIO; 995 goto fail; 996 } 997 998 /* Reset the adapter. */ 999 vge_reset(sc); 1000 1001 /* 1002 * Get station address from the EEPROM. 1003 */ 1004 vge_read_eeprom(sc, (caddr_t)eaddr, VGE_EE_EADDR, 3, 0); 1005 1006 sc->vge_unit = unit; 1007 1008#if __FreeBSD_version < 502113 1009 printf("vge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 1010#endif 1011 1012 /* 1013 * Allocate the parent bus DMA tag appropriate for PCI. 1014 */ 1015#define VGE_NSEG_NEW 32 1016 error = bus_dma_tag_create(NULL, /* parent */ 1017 1, 0, /* alignment, boundary */ 1018 BUS_SPACE_MAXADDR_32BIT,/* lowaddr */ 1019 BUS_SPACE_MAXADDR, /* highaddr */ 1020 NULL, NULL, /* filter, filterarg */ 1021 MAXBSIZE, VGE_NSEG_NEW, /* maxsize, nsegments */ 1022 BUS_SPACE_MAXSIZE_32BIT,/* maxsegsize */ 1023 BUS_DMA_ALLOCNOW, /* flags */ 1024 NULL, NULL, /* lockfunc, lockarg */ 1025 &sc->vge_parent_tag); 1026 if (error) 1027 goto fail; 1028 1029 error = vge_allocmem(dev, sc); 1030 1031 if (error) 1032 goto fail; 1033 1034 ifp = sc->vge_ifp = if_alloc(IFT_ETHER); 1035 if (ifp == NULL) { 1036 printf("vge%d: can not if_alloc()\n", sc->vge_unit); 1037 error = ENOSPC; 1038 goto fail; 1039 } 1040 1041 /* Do MII setup */ 1042 if (mii_phy_probe(dev, &sc->vge_miibus, 1043 vge_ifmedia_upd, vge_ifmedia_sts)) { 1044 printf("vge%d: MII without any phy!\n", sc->vge_unit); 1045 error = ENXIO; 1046 goto fail; 1047 } 1048 1049 ifp->if_softc = sc; 1050 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 1051 ifp->if_mtu = ETHERMTU; 1052 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 1053 ifp->if_ioctl = vge_ioctl; 1054 ifp->if_capabilities = IFCAP_VLAN_MTU; 1055 ifp->if_start = vge_start; 1056 ifp->if_hwassist = VGE_CSUM_FEATURES; 1057 ifp->if_capabilities |= IFCAP_HWCSUM|IFCAP_VLAN_HWTAGGING; 1058 ifp->if_capenable = ifp->if_capabilities; 1059#ifdef DEVICE_POLLING 1060 ifp->if_capabilities |= IFCAP_POLLING; 1061#endif 1062 ifp->if_watchdog = vge_watchdog; 1063 ifp->if_init = vge_init; 1064 ifp->if_snd.ifq_maxlen = VGE_IFQ_MAXLEN; 1065 1066 TASK_INIT(&sc->vge_txtask, 0, vge_tx_task, ifp); 1067 1068 /* 1069 * Call MI attach routine. 1070 */ 1071 ether_ifattach(ifp, eaddr); 1072 1073 /* Hook interrupt last to avoid having to lock softc */ 1074 error = bus_setup_intr(dev, sc->vge_irq, INTR_TYPE_NET|INTR_MPSAFE, 1075 vge_intr, sc, &sc->vge_intrhand); 1076 1077 if (error) { 1078 printf("vge%d: couldn't set up irq\n", unit); 1079 ether_ifdetach(ifp); 1080 goto fail; 1081 } 1082 1083fail: 1084 if (error) 1085 vge_detach(dev); 1086 1087 return (error); 1088} 1089 1090/* 1091 * Shutdown hardware and free up resources. This can be called any 1092 * time after the mutex has been initialized. It is called in both 1093 * the error case in attach and the normal detach case so it needs 1094 * to be careful about only freeing resources that have actually been 1095 * allocated. 1096 */ 1097static int 1098vge_detach(dev) 1099 device_t dev; 1100{ 1101 struct vge_softc *sc; 1102 struct ifnet *ifp; 1103 int i; 1104 1105 sc = device_get_softc(dev); 1106 KASSERT(mtx_initialized(&sc->vge_mtx), ("vge mutex not initialized")); 1107 ifp = sc->vge_ifp; 1108 1109#ifdef DEVICE_POLLING 1110 if (ifp->if_capenable & IFCAP_POLLING) 1111 ether_poll_deregister(ifp); 1112#endif 1113 1114 /* These should only be active if attach succeeded */ 1115 if (device_is_attached(dev)) { 1116 vge_stop(sc); 1117 /* 1118 * Force off the IFF_UP flag here, in case someone 1119 * still had a BPF descriptor attached to this 1120 * interface. If they do, ether_ifattach() will cause 1121 * the BPF code to try and clear the promisc mode 1122 * flag, which will bubble down to vge_ioctl(), 1123 * which will try to call vge_init() again. This will 1124 * turn the NIC back on and restart the MII ticker, 1125 * which will panic the system when the kernel tries 1126 * to invoke the vge_tick() function that isn't there 1127 * anymore. 1128 */ 1129 ifp->if_flags &= ~IFF_UP; 1130 ether_ifdetach(ifp); 1131 } 1132 if (sc->vge_miibus) 1133 device_delete_child(dev, sc->vge_miibus); 1134 bus_generic_detach(dev); 1135 1136 if (sc->vge_intrhand) 1137 bus_teardown_intr(dev, sc->vge_irq, sc->vge_intrhand); 1138 if (sc->vge_irq) 1139 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->vge_irq); 1140 if (sc->vge_res) 1141 bus_release_resource(dev, SYS_RES_MEMORY, 1142 VGE_PCI_LOMEM, sc->vge_res); 1143 if (ifp) 1144 if_free(ifp); 1145 1146 /* Unload and free the RX DMA ring memory and map */ 1147 1148 if (sc->vge_ldata.vge_rx_list_tag) { 1149 bus_dmamap_unload(sc->vge_ldata.vge_rx_list_tag, 1150 sc->vge_ldata.vge_rx_list_map); 1151 bus_dmamem_free(sc->vge_ldata.vge_rx_list_tag, 1152 sc->vge_ldata.vge_rx_list, 1153 sc->vge_ldata.vge_rx_list_map); 1154 bus_dma_tag_destroy(sc->vge_ldata.vge_rx_list_tag); 1155 } 1156 1157 /* Unload and free the TX DMA ring memory and map */ 1158 1159 if (sc->vge_ldata.vge_tx_list_tag) { 1160 bus_dmamap_unload(sc->vge_ldata.vge_tx_list_tag, 1161 sc->vge_ldata.vge_tx_list_map); 1162 bus_dmamem_free(sc->vge_ldata.vge_tx_list_tag, 1163 sc->vge_ldata.vge_tx_list, 1164 sc->vge_ldata.vge_tx_list_map); 1165 bus_dma_tag_destroy(sc->vge_ldata.vge_tx_list_tag); 1166 } 1167 1168 /* Destroy all the RX and TX buffer maps */ 1169 1170 if (sc->vge_ldata.vge_mtag) { 1171 for (i = 0; i < VGE_TX_DESC_CNT; i++) 1172 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1173 sc->vge_ldata.vge_tx_dmamap[i]); 1174 for (i = 0; i < VGE_RX_DESC_CNT; i++) 1175 bus_dmamap_destroy(sc->vge_ldata.vge_mtag, 1176 sc->vge_ldata.vge_rx_dmamap[i]); 1177 bus_dma_tag_destroy(sc->vge_ldata.vge_mtag); 1178 } 1179 1180 if (sc->vge_parent_tag) 1181 bus_dma_tag_destroy(sc->vge_parent_tag); 1182 1183 mtx_destroy(&sc->vge_mtx); 1184 1185 return (0); 1186} 1187 1188static int 1189vge_newbuf(sc, idx, m) 1190 struct vge_softc *sc; 1191 int idx; 1192 struct mbuf *m; 1193{ 1194 struct vge_dmaload_arg arg; 1195 struct mbuf *n = NULL; 1196 int i, error; 1197 1198 if (m == NULL) { 1199 n = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); 1200 if (n == NULL) 1201 return (ENOBUFS); 1202 m = n; 1203 } else 1204 m->m_data = m->m_ext.ext_buf; 1205 1206 1207#ifdef VGE_FIXUP_RX 1208 /* 1209 * This is part of an evil trick to deal with non-x86 platforms. 1210 * The VIA chip requires RX buffers to be aligned on 32-bit 1211 * boundaries, but that will hose non-x86 machines. To get around 1212 * this, we leave some empty space at the start of each buffer 1213 * and for non-x86 hosts, we copy the buffer back two bytes 1214 * to achieve word alignment. This is slightly more efficient 1215 * than allocating a new buffer, copying the contents, and 1216 * discarding the old buffer. 1217 */ 1218 m->m_len = m->m_pkthdr.len = MCLBYTES - VGE_ETHER_ALIGN; 1219 m_adj(m, VGE_ETHER_ALIGN); 1220#else 1221 m->m_len = m->m_pkthdr.len = MCLBYTES; 1222#endif 1223 1224 arg.sc = sc; 1225 arg.vge_idx = idx; 1226 arg.vge_maxsegs = 1; 1227 arg.vge_flags = 0; 1228 1229 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, 1230 sc->vge_ldata.vge_rx_dmamap[idx], m, vge_dma_map_rx_desc, 1231 &arg, BUS_DMA_NOWAIT); 1232 if (error || arg.vge_maxsegs != 1) { 1233 if (n != NULL) 1234 m_freem(n); 1235 return (ENOMEM); 1236 } 1237 1238 /* 1239 * Note: the manual fails to document the fact that for 1240 * proper opration, the driver needs to replentish the RX 1241 * DMA ring 4 descriptors at a time (rather than one at a 1242 * time, like most chips). We can allocate the new buffers 1243 * but we should not set the OWN bits until we're ready 1244 * to hand back 4 of them in one shot. 1245 */ 1246 1247#define VGE_RXCHUNK 4 1248 sc->vge_rx_consumed++; 1249 if (sc->vge_rx_consumed == VGE_RXCHUNK) { 1250 for (i = idx; i != idx - sc->vge_rx_consumed; i--) 1251 sc->vge_ldata.vge_rx_list[i].vge_sts |= 1252 htole32(VGE_RDSTS_OWN); 1253 sc->vge_rx_consumed = 0; 1254 } 1255 1256 sc->vge_ldata.vge_rx_mbuf[idx] = m; 1257 1258 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1259 sc->vge_ldata.vge_rx_dmamap[idx], 1260 BUS_DMASYNC_PREREAD); 1261 1262 return (0); 1263} 1264 1265static int 1266vge_tx_list_init(sc) 1267 struct vge_softc *sc; 1268{ 1269 bzero ((char *)sc->vge_ldata.vge_tx_list, VGE_TX_LIST_SZ); 1270 bzero ((char *)&sc->vge_ldata.vge_tx_mbuf, 1271 (VGE_TX_DESC_CNT * sizeof(struct mbuf *))); 1272 1273 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1274 sc->vge_ldata.vge_tx_list_map, BUS_DMASYNC_PREWRITE); 1275 sc->vge_ldata.vge_tx_prodidx = 0; 1276 sc->vge_ldata.vge_tx_considx = 0; 1277 sc->vge_ldata.vge_tx_free = VGE_TX_DESC_CNT; 1278 1279 return (0); 1280} 1281 1282static int 1283vge_rx_list_init(sc) 1284 struct vge_softc *sc; 1285{ 1286 int i; 1287 1288 bzero ((char *)sc->vge_ldata.vge_rx_list, VGE_RX_LIST_SZ); 1289 bzero ((char *)&sc->vge_ldata.vge_rx_mbuf, 1290 (VGE_RX_DESC_CNT * sizeof(struct mbuf *))); 1291 1292 sc->vge_rx_consumed = 0; 1293 1294 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 1295 if (vge_newbuf(sc, i, NULL) == ENOBUFS) 1296 return (ENOBUFS); 1297 } 1298 1299 /* Flush the RX descriptors */ 1300 1301 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1302 sc->vge_ldata.vge_rx_list_map, 1303 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1304 1305 sc->vge_ldata.vge_rx_prodidx = 0; 1306 sc->vge_rx_consumed = 0; 1307 sc->vge_head = sc->vge_tail = NULL; 1308 1309 return (0); 1310} 1311 1312#ifdef VGE_FIXUP_RX 1313static __inline void 1314vge_fixup_rx(m) 1315 struct mbuf *m; 1316{ 1317 int i; 1318 uint16_t *src, *dst; 1319 1320 src = mtod(m, uint16_t *); 1321 dst = src - 1; 1322 1323 for (i = 0; i < (m->m_len / sizeof(uint16_t) + 1); i++) 1324 *dst++ = *src++; 1325 1326 m->m_data -= ETHER_ALIGN; 1327 1328 return; 1329} 1330#endif 1331 1332/* 1333 * RX handler. We support the reception of jumbo frames that have 1334 * been fragmented across multiple 2K mbuf cluster buffers. 1335 */ 1336static void 1337vge_rxeof(sc) 1338 struct vge_softc *sc; 1339{ 1340 struct mbuf *m; 1341 struct ifnet *ifp; 1342 int i, total_len; 1343 int lim = 0; 1344 struct vge_rx_desc *cur_rx; 1345 u_int32_t rxstat, rxctl; 1346 1347 VGE_LOCK_ASSERT(sc); 1348 ifp = sc->vge_ifp; 1349 i = sc->vge_ldata.vge_rx_prodidx; 1350 1351 /* Invalidate the descriptor memory */ 1352 1353 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1354 sc->vge_ldata.vge_rx_list_map, 1355 BUS_DMASYNC_POSTREAD); 1356 1357 while (!VGE_OWN(&sc->vge_ldata.vge_rx_list[i])) { 1358 1359#ifdef DEVICE_POLLING 1360 if (ifp->if_capenable & IFCAP_POLLING) { 1361 if (sc->rxcycles <= 0) 1362 break; 1363 sc->rxcycles--; 1364 } 1365#endif 1366 1367 cur_rx = &sc->vge_ldata.vge_rx_list[i]; 1368 m = sc->vge_ldata.vge_rx_mbuf[i]; 1369 total_len = VGE_RXBYTES(cur_rx); 1370 rxstat = le32toh(cur_rx->vge_sts); 1371 rxctl = le32toh(cur_rx->vge_ctl); 1372 1373 /* Invalidate the RX mbuf and unload its map */ 1374 1375 bus_dmamap_sync(sc->vge_ldata.vge_mtag, 1376 sc->vge_ldata.vge_rx_dmamap[i], 1377 BUS_DMASYNC_POSTWRITE); 1378 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1379 sc->vge_ldata.vge_rx_dmamap[i]); 1380 1381 /* 1382 * If the 'start of frame' bit is set, this indicates 1383 * either the first fragment in a multi-fragment receive, 1384 * or an intermediate fragment. Either way, we want to 1385 * accumulate the buffers. 1386 */ 1387 if (rxstat & VGE_RXPKT_SOF) { 1388 m->m_len = MCLBYTES - VGE_ETHER_ALIGN; 1389 if (sc->vge_head == NULL) 1390 sc->vge_head = sc->vge_tail = m; 1391 else { 1392 m->m_flags &= ~M_PKTHDR; 1393 sc->vge_tail->m_next = m; 1394 sc->vge_tail = m; 1395 } 1396 vge_newbuf(sc, i, NULL); 1397 VGE_RX_DESC_INC(i); 1398 continue; 1399 } 1400 1401 /* 1402 * Bad/error frames will have the RXOK bit cleared. 1403 * However, there's one error case we want to allow: 1404 * if a VLAN tagged frame arrives and the chip can't 1405 * match it against the CAM filter, it considers this 1406 * a 'VLAN CAM filter miss' and clears the 'RXOK' bit. 1407 * We don't want to drop the frame though: our VLAN 1408 * filtering is done in software. 1409 */ 1410 if (!(rxstat & VGE_RDSTS_RXOK) && !(rxstat & VGE_RDSTS_VIDM) 1411 && !(rxstat & VGE_RDSTS_CSUMERR)) { 1412 ifp->if_ierrors++; 1413 /* 1414 * If this is part of a multi-fragment packet, 1415 * discard all the pieces. 1416 */ 1417 if (sc->vge_head != NULL) { 1418 m_freem(sc->vge_head); 1419 sc->vge_head = sc->vge_tail = NULL; 1420 } 1421 vge_newbuf(sc, i, m); 1422 VGE_RX_DESC_INC(i); 1423 continue; 1424 } 1425 1426 /* 1427 * If allocating a replacement mbuf fails, 1428 * reload the current one. 1429 */ 1430 1431 if (vge_newbuf(sc, i, NULL)) { 1432 ifp->if_ierrors++; 1433 if (sc->vge_head != NULL) { 1434 m_freem(sc->vge_head); 1435 sc->vge_head = sc->vge_tail = NULL; 1436 } 1437 vge_newbuf(sc, i, m); 1438 VGE_RX_DESC_INC(i); 1439 continue; 1440 } 1441 1442 VGE_RX_DESC_INC(i); 1443 1444 if (sc->vge_head != NULL) { 1445 m->m_len = total_len % (MCLBYTES - VGE_ETHER_ALIGN); 1446 /* 1447 * Special case: if there's 4 bytes or less 1448 * in this buffer, the mbuf can be discarded: 1449 * the last 4 bytes is the CRC, which we don't 1450 * care about anyway. 1451 */ 1452 if (m->m_len <= ETHER_CRC_LEN) { 1453 sc->vge_tail->m_len -= 1454 (ETHER_CRC_LEN - m->m_len); 1455 m_freem(m); 1456 } else { 1457 m->m_len -= ETHER_CRC_LEN; 1458 m->m_flags &= ~M_PKTHDR; 1459 sc->vge_tail->m_next = m; 1460 } 1461 m = sc->vge_head; 1462 sc->vge_head = sc->vge_tail = NULL; 1463 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1464 } else 1465 m->m_pkthdr.len = m->m_len = 1466 (total_len - ETHER_CRC_LEN); 1467 1468#ifdef VGE_FIXUP_RX 1469 vge_fixup_rx(m); 1470#endif 1471 ifp->if_ipackets++; 1472 m->m_pkthdr.rcvif = ifp; 1473 1474 /* Do RX checksumming if enabled */ 1475 if (ifp->if_capenable & IFCAP_RXCSUM) { 1476 1477 /* Check IP header checksum */ 1478 if (rxctl & VGE_RDCTL_IPPKT) 1479 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1480 if (rxctl & VGE_RDCTL_IPCSUMOK) 1481 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1482 1483 /* Check TCP/UDP checksum */ 1484 if (rxctl & (VGE_RDCTL_TCPPKT|VGE_RDCTL_UDPPKT) && 1485 rxctl & VGE_RDCTL_PROTOCSUMOK) { 1486 m->m_pkthdr.csum_flags |= 1487 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1488 m->m_pkthdr.csum_data = 0xffff; 1489 } 1490 } 1491 1492 if (rxstat & VGE_RDSTS_VTAG) { 1493 VLAN_INPUT_TAG(ifp, m, 1494 ntohs((rxctl & VGE_RDCTL_VLANID))); 1495 if (m == NULL) 1496 continue; 1497 } 1498 1499 VGE_UNLOCK(sc); 1500 (*ifp->if_input)(ifp, m); 1501 VGE_LOCK(sc); 1502 1503 lim++; 1504 if (lim == VGE_RX_DESC_CNT) 1505 break; 1506 1507 } 1508 1509 /* Flush the RX DMA ring */ 1510 1511 bus_dmamap_sync(sc->vge_ldata.vge_rx_list_tag, 1512 sc->vge_ldata.vge_rx_list_map, 1513 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1514 1515 sc->vge_ldata.vge_rx_prodidx = i; 1516 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, lim); 1517 1518 1519 return; 1520} 1521 1522static void 1523vge_txeof(sc) 1524 struct vge_softc *sc; 1525{ 1526 struct ifnet *ifp; 1527 u_int32_t txstat; 1528 int idx; 1529 1530 ifp = sc->vge_ifp; 1531 idx = sc->vge_ldata.vge_tx_considx; 1532 1533 /* Invalidate the TX descriptor list */ 1534 1535 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1536 sc->vge_ldata.vge_tx_list_map, 1537 BUS_DMASYNC_POSTREAD); 1538 1539 while (idx != sc->vge_ldata.vge_tx_prodidx) { 1540 1541 txstat = le32toh(sc->vge_ldata.vge_tx_list[idx].vge_sts); 1542 if (txstat & VGE_TDSTS_OWN) 1543 break; 1544 1545 m_freem(sc->vge_ldata.vge_tx_mbuf[idx]); 1546 sc->vge_ldata.vge_tx_mbuf[idx] = NULL; 1547 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 1548 sc->vge_ldata.vge_tx_dmamap[idx]); 1549 if (txstat & (VGE_TDSTS_EXCESSCOLL|VGE_TDSTS_COLL)) 1550 ifp->if_collisions++; 1551 if (txstat & VGE_TDSTS_TXERR) 1552 ifp->if_oerrors++; 1553 else 1554 ifp->if_opackets++; 1555 1556 sc->vge_ldata.vge_tx_free++; 1557 VGE_TX_DESC_INC(idx); 1558 } 1559 1560 /* No changes made to the TX ring, so no flush needed */ 1561 1562 if (idx != sc->vge_ldata.vge_tx_considx) { 1563 sc->vge_ldata.vge_tx_considx = idx; 1564 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1565 ifp->if_timer = 0; 1566 } 1567 1568 /* 1569 * If not all descriptors have been released reaped yet, 1570 * reload the timer so that we will eventually get another 1571 * interrupt that will cause us to re-enter this routine. 1572 * This is done in case the transmitter has gone idle. 1573 */ 1574 if (sc->vge_ldata.vge_tx_free != VGE_TX_DESC_CNT) { 1575 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1576 } 1577 1578 return; 1579} 1580 1581static void 1582vge_tick(xsc) 1583 void *xsc; 1584{ 1585 struct vge_softc *sc; 1586 struct ifnet *ifp; 1587 struct mii_data *mii; 1588 1589 sc = xsc; 1590 ifp = sc->vge_ifp; 1591 VGE_LOCK(sc); 1592 mii = device_get_softc(sc->vge_miibus); 1593 1594 mii_tick(mii); 1595 if (sc->vge_link) { 1596 if (!(mii->mii_media_status & IFM_ACTIVE)) { 1597 sc->vge_link = 0; 1598 if_link_state_change(sc->vge_ifp, 1599 LINK_STATE_DOWN); 1600 } 1601 } else { 1602 if (mii->mii_media_status & IFM_ACTIVE && 1603 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1604 sc->vge_link = 1; 1605 if_link_state_change(sc->vge_ifp, 1606 LINK_STATE_UP); 1607#if __FreeBSD_version < 502114 1608 if (ifp->if_snd.ifq_head != NULL) 1609#else 1610 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1611#endif 1612 taskqueue_enqueue(taskqueue_swi, 1613 &sc->vge_txtask); 1614 } 1615 } 1616 1617 VGE_UNLOCK(sc); 1618 1619 return; 1620} 1621 1622#ifdef DEVICE_POLLING 1623static void 1624vge_poll (struct ifnet *ifp, enum poll_cmd cmd, int count) 1625{ 1626 struct vge_softc *sc = ifp->if_softc; 1627 1628 VGE_LOCK(sc); 1629 if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1630 goto done; 1631 1632 sc->rxcycles = count; 1633 vge_rxeof(sc); 1634 vge_txeof(sc); 1635 1636#if __FreeBSD_version < 502114 1637 if (ifp->if_snd.ifq_head != NULL) 1638#else 1639 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1640#endif 1641 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1642 1643 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1644 u_int32_t status; 1645 status = CSR_READ_4(sc, VGE_ISR); 1646 if (status == 0xFFFFFFFF) 1647 goto done; 1648 if (status) 1649 CSR_WRITE_4(sc, VGE_ISR, status); 1650 1651 /* 1652 * XXX check behaviour on receiver stalls. 1653 */ 1654 1655 if (status & VGE_ISR_TXDMA_STALL || 1656 status & VGE_ISR_RXDMA_STALL) 1657 vge_init(sc); 1658 1659 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1660 vge_rxeof(sc); 1661 ifp->if_ierrors++; 1662 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1663 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1664 } 1665 } 1666done: 1667 VGE_UNLOCK(sc); 1668} 1669#endif /* DEVICE_POLLING */ 1670 1671static void 1672vge_intr(arg) 1673 void *arg; 1674{ 1675 struct vge_softc *sc; 1676 struct ifnet *ifp; 1677 u_int32_t status; 1678 1679 sc = arg; 1680 1681 if (sc->suspended) { 1682 return; 1683 } 1684 1685 VGE_LOCK(sc); 1686 ifp = sc->vge_ifp; 1687 1688 if (!(ifp->if_flags & IFF_UP)) { 1689 VGE_UNLOCK(sc); 1690 return; 1691 } 1692 1693#ifdef DEVICE_POLLING 1694 if (ifp->if_capenable & IFCAP_POLLING) { 1695 VGE_UNLOCK(sc); 1696 return; 1697 } 1698#endif 1699 1700 /* Disable interrupts */ 1701 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 1702 1703 for (;;) { 1704 1705 status = CSR_READ_4(sc, VGE_ISR); 1706 /* If the card has gone away the read returns 0xffff. */ 1707 if (status == 0xFFFFFFFF) 1708 break; 1709 1710 if (status) 1711 CSR_WRITE_4(sc, VGE_ISR, status); 1712 1713 if ((status & VGE_INTRS) == 0) 1714 break; 1715 1716 if (status & (VGE_ISR_RXOK|VGE_ISR_RXOK_HIPRIO)) 1717 vge_rxeof(sc); 1718 1719 if (status & (VGE_ISR_RXOFLOW|VGE_ISR_RXNODESC)) { 1720 vge_rxeof(sc); 1721 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 1722 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 1723 } 1724 1725 if (status & (VGE_ISR_TXOK0|VGE_ISR_TIMER0)) 1726 vge_txeof(sc); 1727 1728 if (status & (VGE_ISR_TXDMA_STALL|VGE_ISR_RXDMA_STALL)) 1729 vge_init(sc); 1730 1731 if (status & VGE_ISR_LINKSTS) 1732 vge_tick(sc); 1733 } 1734 1735 /* Re-enable interrupts */ 1736 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 1737 1738 VGE_UNLOCK(sc); 1739 1740#if __FreeBSD_version < 502114 1741 if (ifp->if_snd.ifq_head != NULL) 1742#else 1743 if (!IFQ_DRV_IS_EMPTY(&ifp->if_snd)) 1744#endif 1745 taskqueue_enqueue(taskqueue_swi, &sc->vge_txtask); 1746 1747 return; 1748} 1749 1750static int 1751vge_encap(sc, m_head, idx) 1752 struct vge_softc *sc; 1753 struct mbuf *m_head; 1754 int idx; 1755{ 1756 struct mbuf *m_new = NULL; 1757 struct vge_dmaload_arg arg; 1758 bus_dmamap_t map; 1759 int error; 1760 struct m_tag *mtag; 1761 1762 if (sc->vge_ldata.vge_tx_free <= 2) 1763 return (EFBIG); 1764 1765 arg.vge_flags = 0; 1766 1767 if (m_head->m_pkthdr.csum_flags & CSUM_IP) 1768 arg.vge_flags |= VGE_TDCTL_IPCSUM; 1769 if (m_head->m_pkthdr.csum_flags & CSUM_TCP) 1770 arg.vge_flags |= VGE_TDCTL_TCPCSUM; 1771 if (m_head->m_pkthdr.csum_flags & CSUM_UDP) 1772 arg.vge_flags |= VGE_TDCTL_UDPCSUM; 1773 1774 arg.sc = sc; 1775 arg.vge_idx = idx; 1776 arg.vge_m0 = m_head; 1777 arg.vge_maxsegs = VGE_TX_FRAGS; 1778 1779 map = sc->vge_ldata.vge_tx_dmamap[idx]; 1780 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1781 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1782 1783 if (error && error != EFBIG) { 1784 printf("vge%d: can't map mbuf (error %d)\n", 1785 sc->vge_unit, error); 1786 return (ENOBUFS); 1787 } 1788 1789 /* Too many segments to map, coalesce into a single mbuf */ 1790 1791 if (error || arg.vge_maxsegs == 0) { 1792 m_new = m_defrag(m_head, M_DONTWAIT); 1793 if (m_new == NULL) 1794 return (1); 1795 else 1796 m_head = m_new; 1797 1798 arg.sc = sc; 1799 arg.vge_m0 = m_head; 1800 arg.vge_idx = idx; 1801 arg.vge_maxsegs = 1; 1802 1803 error = bus_dmamap_load_mbuf(sc->vge_ldata.vge_mtag, map, 1804 m_head, vge_dma_map_tx_desc, &arg, BUS_DMA_NOWAIT); 1805 if (error) { 1806 printf("vge%d: can't map mbuf (error %d)\n", 1807 sc->vge_unit, error); 1808 return (EFBIG); 1809 } 1810 } 1811 1812 sc->vge_ldata.vge_tx_mbuf[idx] = m_head; 1813 sc->vge_ldata.vge_tx_free--; 1814 1815 /* 1816 * Set up hardware VLAN tagging. 1817 */ 1818 1819 mtag = VLAN_OUTPUT_TAG(sc->vge_ifp, m_head); 1820 if (mtag != NULL) 1821 sc->vge_ldata.vge_tx_list[idx].vge_ctl |= 1822 htole32(htons(VLAN_TAG_VALUE(mtag)) | VGE_TDCTL_VTAG); 1823 1824 sc->vge_ldata.vge_tx_list[idx].vge_sts |= htole32(VGE_TDSTS_OWN); 1825 1826 return (0); 1827} 1828 1829static void 1830vge_tx_task(arg, npending) 1831 void *arg; 1832 int npending; 1833{ 1834 struct ifnet *ifp; 1835 1836 ifp = arg; 1837 vge_start(ifp); 1838 1839 return; 1840} 1841 1842/* 1843 * Main transmit routine. 1844 */ 1845 1846static void 1847vge_start(ifp) 1848 struct ifnet *ifp; 1849{ 1850 struct vge_softc *sc; 1851 struct mbuf *m_head = NULL; 1852 int idx, pidx = 0; 1853 1854 sc = ifp->if_softc; 1855 VGE_LOCK(sc); 1856 1857 if (!sc->vge_link || ifp->if_drv_flags & IFF_DRV_OACTIVE) { 1858 VGE_UNLOCK(sc); 1859 return; 1860 } 1861 1862#if __FreeBSD_version < 502114 1863 if (ifp->if_snd.ifq_head == NULL) { 1864#else 1865 if (IFQ_DRV_IS_EMPTY(&ifp->if_snd)) { 1866#endif 1867 VGE_UNLOCK(sc); 1868 return; 1869 } 1870 1871 idx = sc->vge_ldata.vge_tx_prodidx; 1872 1873 pidx = idx - 1; 1874 if (pidx < 0) 1875 pidx = VGE_TX_DESC_CNT - 1; 1876 1877 1878 while (sc->vge_ldata.vge_tx_mbuf[idx] == NULL) { 1879#if __FreeBSD_version < 502114 1880 IF_DEQUEUE(&ifp->if_snd, m_head); 1881#else 1882 IFQ_DRV_DEQUEUE(&ifp->if_snd, m_head); 1883#endif 1884 if (m_head == NULL) 1885 break; 1886 1887 if (vge_encap(sc, m_head, idx)) { 1888#if __FreeBSD_version >= 502114 1889 IFQ_DRV_PREPEND(&ifp->if_snd, m_head); 1890#else 1891 IF_PREPEND(&ifp->if_snd, m_head); 1892#endif 1893 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1894 break; 1895 } 1896 1897 sc->vge_ldata.vge_tx_list[pidx].vge_frag[0].vge_buflen |= 1898 htole16(VGE_TXDESC_Q); 1899 1900 pidx = idx; 1901 VGE_TX_DESC_INC(idx); 1902 1903 /* 1904 * If there's a BPF listener, bounce a copy of this frame 1905 * to him. 1906 */ 1907 BPF_MTAP(ifp, m_head); 1908 } 1909 1910 if (idx == sc->vge_ldata.vge_tx_prodidx) { 1911 VGE_UNLOCK(sc); 1912 return; 1913 } 1914 1915 /* Flush the TX descriptors */ 1916 1917 bus_dmamap_sync(sc->vge_ldata.vge_tx_list_tag, 1918 sc->vge_ldata.vge_tx_list_map, 1919 BUS_DMASYNC_PREWRITE|BUS_DMASYNC_PREREAD); 1920 1921 /* Issue a transmit command. */ 1922 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_WAK0); 1923 1924 sc->vge_ldata.vge_tx_prodidx = idx; 1925 1926 /* 1927 * Use the countdown timer for interrupt moderation. 1928 * 'TX done' interrupts are disabled. Instead, we reset the 1929 * countdown timer, which will begin counting until it hits 1930 * the value in the SSTIMER register, and then trigger an 1931 * interrupt. Each time we set the TIMER0_ENABLE bit, the 1932 * the timer count is reloaded. Only when the transmitter 1933 * is idle will the timer hit 0 and an interrupt fire. 1934 */ 1935 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_TIMER0_ENABLE); 1936 1937 VGE_UNLOCK(sc); 1938 1939 /* 1940 * Set a timeout in case the chip goes out to lunch. 1941 */ 1942 ifp->if_timer = 5; 1943 1944 return; 1945} 1946 1947static void 1948vge_init(xsc) 1949 void *xsc; 1950{ 1951 struct vge_softc *sc = xsc; 1952 struct ifnet *ifp = sc->vge_ifp; 1953 struct mii_data *mii; 1954 int i; 1955 1956 VGE_LOCK(sc); 1957 mii = device_get_softc(sc->vge_miibus); 1958 1959 /* 1960 * Cancel pending I/O and free all RX/TX buffers. 1961 */ 1962 vge_stop(sc); 1963 vge_reset(sc); 1964 1965 /* 1966 * Initialize the RX and TX descriptors and mbufs. 1967 */ 1968 1969 vge_rx_list_init(sc); 1970 vge_tx_list_init(sc); 1971 1972 /* Set our station address */ 1973 for (i = 0; i < ETHER_ADDR_LEN; i++) 1974 CSR_WRITE_1(sc, VGE_PAR0 + i, IF_LLADDR(sc->vge_ifp)[i]); 1975 1976 /* 1977 * Set receive FIFO threshold. Also allow transmission and 1978 * reception of VLAN tagged frames. 1979 */ 1980 CSR_CLRBIT_1(sc, VGE_RXCFG, VGE_RXCFG_FIFO_THR|VGE_RXCFG_VTAGOPT); 1981 CSR_SETBIT_1(sc, VGE_RXCFG, VGE_RXFIFOTHR_128BYTES|VGE_VTAG_OPT2); 1982 1983 /* Set DMA burst length */ 1984 CSR_CLRBIT_1(sc, VGE_DMACFG0, VGE_DMACFG0_BURSTLEN); 1985 CSR_SETBIT_1(sc, VGE_DMACFG0, VGE_DMABURST_128); 1986 1987 CSR_SETBIT_1(sc, VGE_TXCFG, VGE_TXCFG_ARB_PRIO|VGE_TXCFG_NONBLK); 1988 1989 /* Set collision backoff algorithm */ 1990 CSR_CLRBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_CRANDOM| 1991 VGE_CHIPCFG1_CAP|VGE_CHIPCFG1_MBA|VGE_CHIPCFG1_BAKOPT); 1992 CSR_SETBIT_1(sc, VGE_CHIPCFG1, VGE_CHIPCFG1_OFSET); 1993 1994 /* Disable LPSEL field in priority resolution */ 1995 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_LPSEL_DIS); 1996 1997 /* 1998 * Load the addresses of the DMA queues into the chip. 1999 * Note that we only use one transmit queue. 2000 */ 2001 2002 CSR_WRITE_4(sc, VGE_TXDESC_ADDR_LO0, 2003 VGE_ADDR_LO(sc->vge_ldata.vge_tx_list_addr)); 2004 CSR_WRITE_2(sc, VGE_TXDESCNUM, VGE_TX_DESC_CNT - 1); 2005 2006 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 2007 VGE_ADDR_LO(sc->vge_ldata.vge_rx_list_addr)); 2008 CSR_WRITE_2(sc, VGE_RXDESCNUM, VGE_RX_DESC_CNT - 1); 2009 CSR_WRITE_2(sc, VGE_RXDESC_RESIDUECNT, VGE_RX_DESC_CNT); 2010 2011 /* Enable and wake up the RX descriptor queue */ 2012 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_RUN); 2013 CSR_WRITE_1(sc, VGE_RXQCSRS, VGE_RXQCSR_WAK); 2014 2015 /* Enable the TX descriptor queue */ 2016 CSR_WRITE_2(sc, VGE_TXQCSRS, VGE_TXQCSR_RUN0); 2017 2018 /* Set up the receive filter -- allow large frames for VLANs. */ 2019 CSR_WRITE_1(sc, VGE_RXCTL, VGE_RXCTL_RX_UCAST|VGE_RXCTL_RX_GIANT); 2020 2021 /* If we want promiscuous mode, set the allframes bit. */ 2022 if (ifp->if_flags & IFF_PROMISC) { 2023 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_PROMISC); 2024 } 2025 2026 /* Set capture broadcast bit to capture broadcast frames. */ 2027 if (ifp->if_flags & IFF_BROADCAST) { 2028 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_BCAST); 2029 } 2030 2031 /* Set multicast bit to capture multicast frames. */ 2032 if (ifp->if_flags & IFF_MULTICAST) { 2033 CSR_SETBIT_1(sc, VGE_RXCTL, VGE_RXCTL_RX_MCAST); 2034 } 2035 2036 /* Init the cam filter. */ 2037 vge_cam_clear(sc); 2038 2039 /* Init the multicast filter. */ 2040 vge_setmulti(sc); 2041 2042 /* Enable flow control */ 2043 2044 CSR_WRITE_1(sc, VGE_CRS2, 0x8B); 2045 2046 /* Enable jumbo frame reception (if desired) */ 2047 2048 /* Start the MAC. */ 2049 CSR_WRITE_1(sc, VGE_CRC0, VGE_CR0_STOP); 2050 CSR_WRITE_1(sc, VGE_CRS1, VGE_CR1_NOPOLL); 2051 CSR_WRITE_1(sc, VGE_CRS0, 2052 VGE_CR0_TX_ENABLE|VGE_CR0_RX_ENABLE|VGE_CR0_START); 2053 2054 /* 2055 * Configure one-shot timer for microsecond 2056 * resulution and load it for 500 usecs. 2057 */ 2058 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_TIMER0_RES); 2059 CSR_WRITE_2(sc, VGE_SSTIMER, 400); 2060 2061 /* 2062 * Configure interrupt moderation for receive. Enable 2063 * the holdoff counter and load it, and set the RX 2064 * suppression count to the number of descriptors we 2065 * want to allow before triggering an interrupt. 2066 * The holdoff timer is in units of 20 usecs. 2067 */ 2068 2069#ifdef notyet 2070 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_TXINTSUP_DISABLE); 2071 /* Select the interrupt holdoff timer page. */ 2072 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2073 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_INTHLDOFF); 2074 CSR_WRITE_1(sc, VGE_INTHOLDOFF, 10); /* ~200 usecs */ 2075 2076 /* Enable use of the holdoff timer. */ 2077 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_HOLDOFF); 2078 CSR_WRITE_1(sc, VGE_INTCTL1, VGE_INTCTL_SC_RELOAD); 2079 2080 /* Select the RX suppression threshold page. */ 2081 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2082 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_RXSUPPTHR); 2083 CSR_WRITE_1(sc, VGE_RXSUPPTHR, 64); /* interrupt after 64 packets */ 2084 2085 /* Restore the page select bits. */ 2086 CSR_CLRBIT_1(sc, VGE_CAMCTL, VGE_CAMCTL_PAGESEL); 2087 CSR_SETBIT_1(sc, VGE_CAMCTL, VGE_PAGESEL_MAR); 2088#endif 2089 2090#ifdef DEVICE_POLLING 2091 /* 2092 * Disable interrupts if we are polling. 2093 */ 2094 if (ifp->if_capenable & IFCAP_POLLING) { 2095 CSR_WRITE_4(sc, VGE_IMR, 0); 2096 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2097 } else /* otherwise ... */ 2098#endif 2099 { 2100 /* 2101 * Enable interrupts. 2102 */ 2103 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2104 CSR_WRITE_4(sc, VGE_ISR, 0); 2105 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2106 } 2107 2108 mii_mediachg(mii); 2109 2110 ifp->if_drv_flags |= IFF_DRV_RUNNING; 2111 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 2112 2113 sc->vge_if_flags = 0; 2114 sc->vge_link = 0; 2115 2116 VGE_UNLOCK(sc); 2117 2118 return; 2119} 2120 2121/* 2122 * Set media options. 2123 */ 2124static int 2125vge_ifmedia_upd(ifp) 2126 struct ifnet *ifp; 2127{ 2128 struct vge_softc *sc; 2129 struct mii_data *mii; 2130 2131 sc = ifp->if_softc; 2132 mii = device_get_softc(sc->vge_miibus); 2133 mii_mediachg(mii); 2134 2135 return (0); 2136} 2137 2138/* 2139 * Report current media status. 2140 */ 2141static void 2142vge_ifmedia_sts(ifp, ifmr) 2143 struct ifnet *ifp; 2144 struct ifmediareq *ifmr; 2145{ 2146 struct vge_softc *sc; 2147 struct mii_data *mii; 2148 2149 sc = ifp->if_softc; 2150 mii = device_get_softc(sc->vge_miibus); 2151 2152 mii_pollstat(mii); 2153 ifmr->ifm_active = mii->mii_media_active; 2154 ifmr->ifm_status = mii->mii_media_status; 2155 2156 return; 2157} 2158 2159static void 2160vge_miibus_statchg(dev) 2161 device_t dev; 2162{ 2163 struct vge_softc *sc; 2164 struct mii_data *mii; 2165 struct ifmedia_entry *ife; 2166 2167 sc = device_get_softc(dev); 2168 mii = device_get_softc(sc->vge_miibus); 2169 ife = mii->mii_media.ifm_cur; 2170 2171 /* 2172 * If the user manually selects a media mode, we need to turn 2173 * on the forced MAC mode bit in the DIAGCTL register. If the 2174 * user happens to choose a full duplex mode, we also need to 2175 * set the 'force full duplex' bit. This applies only to 2176 * 10Mbps and 100Mbps speeds. In autoselect mode, forced MAC 2177 * mode is disabled, and in 1000baseT mode, full duplex is 2178 * always implied, so we turn on the forced mode bit but leave 2179 * the FDX bit cleared. 2180 */ 2181 2182 switch (IFM_SUBTYPE(ife->ifm_media)) { 2183 case IFM_AUTO: 2184 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2185 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2186 break; 2187 case IFM_1000_T: 2188 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2189 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2190 break; 2191 case IFM_100_TX: 2192 case IFM_10_T: 2193 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_MACFORCE); 2194 if ((ife->ifm_media & IFM_GMASK) == IFM_FDX) { 2195 CSR_SETBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2196 } else { 2197 CSR_CLRBIT_1(sc, VGE_DIAGCTL, VGE_DIAGCTL_FDXFORCE); 2198 } 2199 break; 2200 default: 2201 device_printf(dev, "unknown media type: %x\n", 2202 IFM_SUBTYPE(ife->ifm_media)); 2203 break; 2204 } 2205 2206 return; 2207} 2208 2209static int 2210vge_ioctl(ifp, command, data) 2211 struct ifnet *ifp; 2212 u_long command; 2213 caddr_t data; 2214{ 2215 struct vge_softc *sc = ifp->if_softc; 2216 struct ifreq *ifr = (struct ifreq *) data; 2217 struct mii_data *mii; 2218 int error = 0; 2219 2220 switch (command) { 2221 case SIOCSIFMTU: 2222 if (ifr->ifr_mtu > VGE_JUMBO_MTU) 2223 error = EINVAL; 2224 ifp->if_mtu = ifr->ifr_mtu; 2225 break; 2226 case SIOCSIFFLAGS: 2227 if (ifp->if_flags & IFF_UP) { 2228 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2229 ifp->if_flags & IFF_PROMISC && 2230 !(sc->vge_if_flags & IFF_PROMISC)) { 2231 CSR_SETBIT_1(sc, VGE_RXCTL, 2232 VGE_RXCTL_RX_PROMISC); 2233 vge_setmulti(sc); 2234 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 2235 !(ifp->if_flags & IFF_PROMISC) && 2236 sc->vge_if_flags & IFF_PROMISC) { 2237 CSR_CLRBIT_1(sc, VGE_RXCTL, 2238 VGE_RXCTL_RX_PROMISC); 2239 vge_setmulti(sc); 2240 } else 2241 vge_init(sc); 2242 } else { 2243 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2244 vge_stop(sc); 2245 } 2246 sc->vge_if_flags = ifp->if_flags; 2247 break; 2248 case SIOCADDMULTI: 2249 case SIOCDELMULTI: 2250 vge_setmulti(sc); 2251 break; 2252 case SIOCGIFMEDIA: 2253 case SIOCSIFMEDIA: 2254 mii = device_get_softc(sc->vge_miibus); 2255 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 2256 break; 2257 case SIOCSIFCAP: 2258 { 2259 int mask = ifr->ifr_reqcap ^ ifp->if_capenable; 2260#ifdef DEVICE_POLLING 2261 if (mask & IFCAP_POLLING) { 2262 if (ifr->ifr_reqcap & IFCAP_POLLING) { 2263 error = ether_poll_register(vge_poll, ifp); 2264 if (error) 2265 return(error); 2266 VGE_LOCK(sc); 2267 /* Disable interrupts */ 2268 CSR_WRITE_4(sc, VGE_IMR, 0); 2269 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2270 ifp->if_capenable |= IFCAP_POLLING; 2271 VGE_UNLOCK(sc); 2272 } else { 2273 error = ether_poll_deregister(ifp); 2274 /* Enable interrupts. */ 2275 VGE_LOCK(sc); 2276 CSR_WRITE_4(sc, VGE_IMR, VGE_INTRS); 2277 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2278 CSR_WRITE_1(sc, VGE_CRS3, VGE_CR3_INT_GMSK); 2279 ifp->if_capenable &= ~IFCAP_POLLING; 2280 VGE_UNLOCK(sc); 2281 } 2282 } 2283#endif /* DEVICE_POLLING */ 2284 if (mask & IFCAP_HWCSUM) { 2285 ifp->if_capenable |= ifr->ifr_reqcap & (IFCAP_HWCSUM); 2286 if (ifp->if_capenable & IFCAP_TXCSUM) 2287 ifp->if_hwassist = VGE_CSUM_FEATURES; 2288 else 2289 ifp->if_hwassist = 0; 2290 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 2291 vge_init(sc); 2292 } 2293 } 2294 break; 2295 default: 2296 error = ether_ioctl(ifp, command, data); 2297 break; 2298 } 2299 2300 return (error); 2301} 2302 2303static void 2304vge_watchdog(ifp) 2305 struct ifnet *ifp; 2306{ 2307 struct vge_softc *sc; 2308 2309 sc = ifp->if_softc; 2310 VGE_LOCK(sc); 2311 printf("vge%d: watchdog timeout\n", sc->vge_unit); 2312 ifp->if_oerrors++; 2313 2314 vge_txeof(sc); 2315 vge_rxeof(sc); 2316 2317 vge_init(sc); 2318 2319 VGE_UNLOCK(sc); 2320 2321 return; 2322} 2323 2324/* 2325 * Stop the adapter and free any mbufs allocated to the 2326 * RX and TX lists. 2327 */ 2328static void 2329vge_stop(sc) 2330 struct vge_softc *sc; 2331{ 2332 register int i; 2333 struct ifnet *ifp; 2334 2335 VGE_LOCK(sc); 2336 ifp = sc->vge_ifp; 2337 ifp->if_timer = 0; 2338 2339 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 2340 2341 CSR_WRITE_1(sc, VGE_CRC3, VGE_CR3_INT_GMSK); 2342 CSR_WRITE_1(sc, VGE_CRS0, VGE_CR0_STOP); 2343 CSR_WRITE_4(sc, VGE_ISR, 0xFFFFFFFF); 2344 CSR_WRITE_2(sc, VGE_TXQCSRC, 0xFFFF); 2345 CSR_WRITE_1(sc, VGE_RXQCSRC, 0xFF); 2346 CSR_WRITE_4(sc, VGE_RXDESC_ADDR_LO, 0); 2347 2348 if (sc->vge_head != NULL) { 2349 m_freem(sc->vge_head); 2350 sc->vge_head = sc->vge_tail = NULL; 2351 } 2352 2353 /* Free the TX list buffers. */ 2354 2355 for (i = 0; i < VGE_TX_DESC_CNT; i++) { 2356 if (sc->vge_ldata.vge_tx_mbuf[i] != NULL) { 2357 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2358 sc->vge_ldata.vge_tx_dmamap[i]); 2359 m_freem(sc->vge_ldata.vge_tx_mbuf[i]); 2360 sc->vge_ldata.vge_tx_mbuf[i] = NULL; 2361 } 2362 } 2363 2364 /* Free the RX list buffers. */ 2365 2366 for (i = 0; i < VGE_RX_DESC_CNT; i++) { 2367 if (sc->vge_ldata.vge_rx_mbuf[i] != NULL) { 2368 bus_dmamap_unload(sc->vge_ldata.vge_mtag, 2369 sc->vge_ldata.vge_rx_dmamap[i]); 2370 m_freem(sc->vge_ldata.vge_rx_mbuf[i]); 2371 sc->vge_ldata.vge_rx_mbuf[i] = NULL; 2372 } 2373 } 2374 2375 VGE_UNLOCK(sc); 2376 2377 return; 2378} 2379 2380/* 2381 * Device suspend routine. Stop the interface and save some PCI 2382 * settings in case the BIOS doesn't restore them properly on 2383 * resume. 2384 */ 2385static int 2386vge_suspend(dev) 2387 device_t dev; 2388{ 2389 struct vge_softc *sc; 2390 2391 sc = device_get_softc(dev); 2392 2393 vge_stop(sc); 2394 2395 sc->suspended = 1; 2396 2397 return (0); 2398} 2399 2400/* 2401 * Device resume routine. Restore some PCI settings in case the BIOS 2402 * doesn't, re-enable busmastering, and restart the interface if 2403 * appropriate. 2404 */ 2405static int 2406vge_resume(dev) 2407 device_t dev; 2408{ 2409 struct vge_softc *sc; 2410 struct ifnet *ifp; 2411 2412 sc = device_get_softc(dev); 2413 ifp = sc->vge_ifp; 2414 2415 /* reenable busmastering */ 2416 pci_enable_busmaster(dev); 2417 pci_enable_io(dev, SYS_RES_MEMORY); 2418 2419 /* reinitialize interface if necessary */ 2420 if (ifp->if_flags & IFF_UP) 2421 vge_init(sc); 2422 2423 sc->suspended = 0; 2424 2425 return (0); 2426} 2427 2428/* 2429 * Stop all chip I/O so that the kernel's probe routines don't 2430 * get confused by errant DMAs when rebooting. 2431 */ 2432static void 2433vge_shutdown(dev) 2434 device_t dev; 2435{ 2436 struct vge_softc *sc; 2437 2438 sc = device_get_softc(dev); 2439 2440 vge_stop(sc); 2441} 2442